Tamar Christina fab7c86ea4 AArch64: Add SVE DWARF registers ... The SVE DRAWF register names are missing from binutils, this may cause objdump and readelf to ignore certain DRAWF output as the registers are unknown (most notably CIEs). This patch adds the registers in accordance to the "DWARF for ARM(r) 64-bit Architecture (AARch64) with SVE support" documentation [1]. [1] https://developer.arm.com/docs/100985/latest/dwarf-for-the-arm-64-bit-architecture-aarch64-with-sve-support binutils/ChangeLog: * dwarf.c (dwarf_regnames_aarch64): Add SVE registers. * testsuite/binutils-all/aarch64/sve-dwarf-registers.d: New test. * testsuite/binutils-all/aarch64/sve-dwarf-registers.s: New test.		2019-05-21 11:05:22 +01:00
..
aarch64.exp	Update year range in copyright notice of binutils files	2019-01-01 22:06:53 +10:30
illegal.d
illegal.s
in-order-all.d	AArch64/Arm: Update testcases fixing endiannes and linux targets	2019-03-26 16:47:14 +00:00
in-order.d	AArch64/Arm: Update testcases fixing endiannes and linux targets	2019-03-26 16:47:14 +00:00
objdump.d	[Binutils][Objdump]Check symbol section information while search a mapping symbol backward.	2017-12-11 15:42:47 +00:00
objdump.s	[Binutils][Objdump]Check symbol section information while search a mapping symbol backward.	2017-12-11 15:42:47 +00:00
out-of-order-all.d	AArch64/Arm: Update testcases fixing endiannes and linux targets	2019-03-26 16:47:14 +00:00
out-of-order.d	AArch64/Arm: Update testcases fixing endiannes and linux targets	2019-03-26 16:47:14 +00:00
out-of-order.s	AArch64/Arm: Update testcases fixing endiannes and linux targets	2019-03-26 16:47:14 +00:00
out-of-order.T	AArch64: Fix disassembler bug with out-of-order sections	2019-03-25 15:05:53 +00:00
sve-dwarf-registers.d	AArch64: Add SVE DWARF registers	2019-05-21 11:05:22 +01:00
sve-dwarf-registers.s	AArch64: Add SVE DWARF registers	2019-05-21 11:05:22 +01:00
unallocated-encoding.d
unallocated-encoding.s