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Author SHA1 Message Date
Mike Frysinger
22215ae09b opcodes/gas: blackfin: handle more ASTAT flags 
Support a few more ASTAT bits with the standard insns that operate on
ASTAT bits directly.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
 2010-09-22 21:05:03 +00:00
Mike Frysinger
73a63ccf2f opcodes/gas: blackfin: support OUTC debug insn 
The disassembler has partial (but incomplete/broken) support already for
the pseudo debug insn OUTC, so let's fix it up and finish it.  And now
that the disassembler can handle it, make sure our assembler can output
it too.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
 2010-09-22 20:59:00 +00:00
Mike Frysinger
59a82d2333 opcodes: blackfin: fix decoding of LSHIFT insns 
The Blackfin ISA does not have a "SHIFT" insn, it has either LSHIFT,
ASHIFT, or BXORSHIFT.  So be specific when disassembling.

As fall out of this change, we need to update some assembler tests.

Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
 2010-09-22 20:37:25 +00:00
Mike Frysinger
528c6277f7 opcodes: blackfin: constify formatting related structures 
No need for these local structures related to formatting of output to
be writable, so constify the whole shebang.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
 2010-09-22 20:32:40 +00:00
Matthew Gretton-Dann
db472d6ff0 2010-09-17 Tejas Belagod <tejas.belagod@arm.com> 
* config/tc-arm.c (insns): Change MRC entry to accept APSR_RR instead
	of just RR.

2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>

	* gas/arm/copro.s: Add test for APSR_nzcv as a MRC operand.
	* gas/arm/copro.d: Change pc in MRC to disassemble as APSR_nzcv.  Also
	add disassembly for test added in copro.s

2010-09-17  Tejas Belagod  <tejas.belagod@arm.com>

	* arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
 2010-09-17 10:13:41 +00:00
Maciej W. Rozycki
f6690563bb opcodes/ 
* mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
	"sync_mb", "sync_release", "sync_rmb" and "sync_wmb".

	gas/testsuite/
	* gas/mips/mips32r2-sync.d: New test for MIPS32r2 "sync"
	instruction variants.
	* gas/mips/octeon@mips32r2-sync.d: Likewise, Octeon version.
	* gas/mips/mips32r2-sync.s: Source for the new test.
	* gas/mips/mips.exp: Run the new test.
 2010-09-14 23:49:04 +00:00
Pierre Muller
8901a3cd7d * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for 
dlx_insn_type array.
 2010-09-10 13:00:54 +00:00
H.J. Lu
d9e3625e37 Fix "pushw imm16" for x86-64 disassembler. 
gas/testsuite/

2010-08-31  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/11960
	* gas/i386/opcode-intel.d: Updated.
	* gas/i386/x86-64-opcode.d: Likewise.

	* gas/i386/x86-64-opcode.s: Add a "pushw imm16" test.

opcodes/

2010-08-31  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/11960
	* i386-dis.c (sIv): New.
	(dis386): Replace Iq with sIv on "pushT".
	(reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
	(x86_64_table): Replace {T|}/{P|} with P.
	(putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
	(OP_sI): Update v_mode.  Remove w_mode.
 2010-08-31 21:56:57 +00:00
Nathan Froyd
f383de6633 opcodes/ 
* ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
	on E500 and E500MC.
 2010-08-27 13:59:55 +00:00
H.J. Lu
1ab03f4b26 Replace Eb with Mb on prefetch and prefetchw. 
2010-08-17  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
	prefetchw.
 2010-08-17 20:37:26 +00:00
H.J. Lu
2210942396 Don't generate multi-byte NOPs for i686. 
gas/

2010-08-06  Quentin Neill <quentin.neill@amd.com>

	* config/tc-i386.c (arch_entry): Add negated bit to
	  disambiguate flag names starting with "no".
	  (cpu_arch): Add negated bit definitions.  Add
	  ".nop" CPU extension.
	  (i386_align_code): Use new .cpunop bit to decide
	  when to generate alignment using nops.
	  (set_cpu_arch): Use negated bit instead to decide
	  when to use cpu_flags or vs. cpu_flags_and_not.
	  (md_parse_option): Likewise.

gas/testsuite/

2010-08-06  Quentin Neill <quentin.neill@amd.com>

	* gas/i386/arch-10-1.l: Add nopl instruction.
	* gas/i386/arch-10-2.l: Likewise.
	* gas/i386/arch-10-3.l: Likewise.
	* gas/i386/arch-10-4.l: Likewise.
	* gas/i386/arch-10.s: Likewise.
	* gas/i386/arch-10.d: Add nopl instruction, and +nopl extension
	flag to as flags.
	* gas/i386/nops-5-i686.d: Change alignment code generated for
	-mtune=i686.
	* gas/i386/nops-5.d: Change alignment code generated for
	.arch i686.
	* gas/i386/x86-64-nops-5-k8.d: Likewise.
	* gas/i386/x86-64-nops-5.d: Likewise.

opcodes/

2010-08-06  Quentin Neill <quentin.neill@amd.com>

	* i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
	to processor flags for PENTIUMPRO processors and later.
	* i386-opc.h (enum): Add CpuNop.
	(i386_cpu_flags): Add cpunop bit.
	* i386-opc.tbl: Change nop cpu_flags.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
 2010-08-06 18:22:50 +00:00
H.J. Lu
b49dfb4a38 Fix typos in comments in i386-opc.h. 
2010-08-06  Quentin Neill <quentin.neill@amd.com>

	* i386-opc.h (enum): Fix typos in comments.
 2010-08-06 16:33:43 +00:00
Alan Modra
6ca4eb7789 * disassemble.c: Formatting. 
(disassemble_init_for_target <ARCH_m32c>): Comment on endian.
 2010-08-06 03:59:49 +00:00
H.J. Lu
92d4d42efb Add Cpu186 to ud1/ud2/ud2a/ud2b. 
2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
	* i386-tbl.h: Regenerated.
 2010-08-06 01:03:17 +00:00
H.J. Lu
b414985b9e Add ud1 to x86. 
gas/testsuite/

2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>

	* gas/i386/i386.exp: Run arch-4.

	* gas/i386/arch-4.d: New.
	* gas/i386/arch-4.s: Likewise.

	* gas/i386/intel.d: Replace ud2a/ud2b with ud2/ud1.
	* gas/i386/opcode-intel.d: Likewise.
	* gas/i386/opcode-suffix.d: Likewise.
	* gas/i386/opcode.d: Likewise.

opcodes/

2010-08-05  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.

	* i386-opc.tbl: Add ud1.  Remove Cpu686 from ud2/ud2a/ud2b.
	* i386-tbl.h: Regenerated.
 2010-08-06 00:52:57 +00:00
DJ Delorie
f9c7014e9c [include/opcode] 
* rx.h (RX_Operand_Type): Add TwoReg.
(RX_Opcode_ID): Remove ediv and ediv2.

[opcodes]

* rx-decode.opc (SRR): New.
(rx_decode_opcode): Use it for movbi and movbir.  Decode NOP2 (mov
r0,r0) and NOP3 (max r0,r0) special cases.
* rx-decode.c: Regenerate.

[sim/rx]

* rx.c (decode_cache_base): New.
(id_names): Remove ediv and edivu.
(optype_names): Add TwoReg.
(maybe_get_mem_page): New.
(rx_get_byte): Call it.
(get_op): Add TwoReg support.
(put_op): Likewise.
(PD, PS, PS2, GD, GS, GS2, DSZ, SSZ, S2SZ, US1, US2, OM): "opcode"
is a pointer now.
(DO_RETURN): New.  We use longjmp to return an exception result.
(decode_opcode): Make opcode a pointer to the decode cache.  Save
decoded opcode information and re-use.  Call DO_RETURN instead of
return throughout.  Remove ediv and edivu.
* mem.c (ptdc): New.  Adds decode cache.
(rx_mem_ptr): Support it.
(rx_mem_decode_cache): New.
* mem.h (enum mem_ptr_action): add MPA_DECODE_CACHE.
(rx_mem_decode_cache): Declare.
* gdb-if.c (sim_resume): Add decode_opcode's setjmp logic here...
* main.c (main): ...and here.  Use a fast loop if neither trace
nor disassemble is given.
* cpu.h (RX_MAKE_STEPPED, RX_MAKE_HIT_BREAK, RX_MAKE_EXITED,
RX_MAKE_STOPPED, RX_EXITED, RX_STOPPED): Adjust so that 0 is not a
valid code for anything.
 2010-07-29 18:41:28 +00:00
H.J. Lu
592a252b66 Add 0F to VEX opcode enums. 
2010-07-28  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c: Add 0F to VEX opcode enums.
 2010-07-28 21:54:34 +00:00
DJ Delorie
3cf79a015d * rx-decode.opc (store_flags): Remove, replace with F_* macros. 
(rx_decode_opcode): Likewise.
* rx-decode.c: Regenerate.
 2010-07-28 00:36:46 +00:00
Nick Clifton
1cd986c585 Add support for v850E2 and v850E2V3 2010-07-23 14:52:54 +00:00
Richard Earnshaw
52e7f43db0 2010-07-08 Tejas Belagod <tejas.belagod@arm.com> 
gas/testsuite
	* gas/arm/barrier.s: New file.
	* gas/arm/barrier.d: New file.
	* gas/arm/barrier-thumb.s: New file.
	* gas/arm/barrier-thumb.d: New file.
	* gas/arm/barrier-bad.s: New file.
	* gas/arm/barrier-bad.d: New file.
	* gas/arm/barrier-bad.l: New file.
	* gas/arm/barrier-bad-thumb.s: New file.
	* gas/arm/barrier-bad-thumb.d: New file.
	* gas/arm/barrier-bad-thumb.l: New file.

	gas/config
	* tc-arm.c (OP_oBARRIER): Remove.
	(OP_oBARRIER_I15): Add.
	(po_barrier_or_imm): Add macro.
	(parse_operands): Improve OP_oBARRIER_I15 operand parsing.
	(do_barrier): Check correct immediate range.
	(do_t_barrier): Likewise.
	(barrier_opt_names): Add entries for more symbolic operands.
	(insns): Replace OP_oBARRIER with OP_oBARRIER_I15 for barriers.

	opcodes/
	* arm-dis.c (print_insn_arm): Add cases for printing more
	symbolic operands.
	(print_insn_thumb32): Likewise.
 2010-07-08 22:40:28 +00:00
Maciej W. Rozycki
c680e7f672 * mips-dis.c (print_insn_mips): Correct branch instruction type 
determination.
 2010-07-06 00:06:04 +00:00
Maciej W. Rozycki
9a2c708887 gas/ 
* config/tc-mips.c (nops_for_insn_or_target): Replace
	MIPS16_INSN_BRANCH with MIPS16_INSN_UNCOND_BRANCH and
	MIPS16_INSN_COND_BRANCH.

	include/opcode/
	* mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro.
	(MIPS16_INSN_BRANCH): Rename to...
	(MIPS16_INSN_COND_BRANCH): ... this.

	opcodes/
	* mips-dis.c (print_mips16_insn_arg): Remove branch instruction
	type and delay slot determination.
	(print_insn_mips16): Extend branch instruction type and delay
	slot determination to cover all instructions.
	* mips16-opc.c (BR): Remove macro.
	(UBR, CBR): New macros.
	(mips16_opcodes): Update branch annotation for "b", "beqz",
	"bnez", "bteqz" and "btnez".  Add branch annotation for "jalrc"
	and "jrc".
 2010-07-06 00:02:46 +00:00
H.J. Lu
d7d9a9f820 Replace rdrnd with rdrand. 
gas/testsuite/

2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2010)
	* gas/i386/rdrnd.s: Replace rdrnd with rdrand.
	* gas/i386/rdrnd-intel.d: Likewise.
	* gas/i386/rdrnd.d: Likewise.
	* gas/i386/x86-64-rdrnd-intel.d: Likewise.
	* gas/i386/x86-64-rdrnd.d: Likewise.
	* gas/i386/x86-64-rdrnd.s: Likewise.

opcodes/

2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2010)
	* i386-dis.c (mod_table): Replace rdrnd with rdrand.
	* i386-opc.tbl: Likewise.
	* i386-tbl.h: Regenerated.
 2010-07-05 17:14:22 +00:00
H.J. Lu
77321f5360 Fix a typo in comments for CpuFSGSBase. 
2010-07-05  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.h (CpuFSGSBase): Fix a typo in comments.
 2010-07-05 16:40:32 +00:00
Andreas Schwab
3a5530eaab Update. 2010-07-03 08:29:51 +00:00
Andreas Schwab
7102e95e49 gas/: 
* config/tc-ppc.c (ppc_set_cpu): Cast PPC_OPCODE_xxx to ppc_cpu_t
before inverting.

binutils/:
* ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
ppc_cpu_t before inverting.
 2010-07-03 08:27:23 +00:00
Alan Modra
bdc70b4a03 include/opcode/ 
* ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete.
	Renumber other PPC_OPCODE defines.
gas/
	* config/tc-ppc.c (ppc_set_cpu): Remove old opcode flags.
	(ppc_setup_opcodes): Likewise.  Simplify opcode selection.
opcodes/
	* ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
	* ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
	(PPC64, MFDEC2): Update.
	(NON32, NO371): Define.
	(powerpc_opcode): Update to not use old opcode flags, and avoid
	-m601 duplicates.
 2010-07-03 06:51:56 +00:00
DJ Delorie
21375995bd * m32c.cpu (f-dsp-8-s24): Mask high byte after shifting it. 
* m32c-ibld.c: Regenerate.
 2010-07-03 04:09:56 +00:00
Alan Modra
81a0b7e2ae * ppc-opc.c (PWR2COM): Define. 
(PPCPWR2): Add PPC_OPCODE_COMMON.
	(powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
	"fcirz", "fcirz." to -mcom opcodes.  Remove "mfsri", "dclst",
	"rac" from -mcom.
 2010-07-03 03:33:17 +00:00
H.J. Lu
a00eb5e843 Update ChangeLog entry. 2010-07-01 21:57:04 +00:00
H.J. Lu
c7b8aa3a72 Support AVX Programming Reference (June, 2010) 
gas/

2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2010)
	* config/tc-i386.c (cpu_arch): Add .xsaveopt, .fsgsbase, .rdrnd
	and .f16c.

	* doc/c-i386.texi: Document xsaveopt, fsgsbase, rdrnd and f16c.

gas/testsuite/

2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2010)
	* gas/i386/arch-10.s: Add xsaveopt.
	* gas/i386/x86-64-arch-2.s: Likwise.

	* gas/i386/arch-10.d: Updated.
	* gas/i386/arch-10-1.l: Likewise.
	* gas/i386/arch-10-2.l: Likewise.
	* gas/i386/arch-10-3.l: Likewise.
	* gas/i386/arch-10-4.l: Likewise.
	* gas/i386/x86-64-arch-2.d: Likewise.

	* gas/i386/f16c-intel.d: New.
	* gas/i386/f16c.d: Likewise.
	* gas/i386/f16c.s: Likewise.
	* gas/i386/fsgs-intel.d: Likewise.
	* gas/i386/fsgs.d: Likewise.
	* gas/i386/fsgs.s: Likewise.
	* gas/i386/rdrnd-intel.d: Likewise.
	* gas/i386/rdrnd.d: Likewise.
	* gas/i386/rdrnd.s: Likewise.
	* gas/i386/x86-64-f16c-intel.d: Likewise.
	* gas/i386/x86-64-f16c.d: Likewise.
	* gas/i386/x86-64-f16c.s: Likewise.
	* gas/i386/x86-64-fsgs-intel.d: Likewise.
	* gas/i386/x86-64-fsgs.d: Likewise.
	* gas/i386/x86-64-fsgs.s: Likewise.
	* gas/i386/x86-64-rdrnd-intel.d: Likewise.
	* gas/i386/x86-64-rdrnd.d: Likewise.
	* gas/i386/x86-64-rdrnd.s: Likewise.

	* gas/i386/i386.exp: Run f16c, f16c-intel, fsgs, fsgs-intel,
	rdrnd, rdrnd-intel, x86-64-f16c, x86-64-f16c-intel, x86-64-fsgs,
	x86-64-fsgs-intel, x86-64-rdrnd, x86-64-rdrnd-intel.

	* gas/i386/x86-64-xsave.s: Add tests for xsaveopt64.

	* gas/i386/x86-64-xsave-intel.d: Updated.
	* gas/i386/x86-64-xsave.d: Likewise.

opcodes/

2010-07-01  H.J. Lu  <hongjiu.lu@intel.com>

	AVX Programming Reference (June, 2010)
	* i386-dis.c (PREFIX_0FAE_REG_0): New.
	(PREFIX_0FAE_REG_1): Likewise.
	(PREFIX_0FAE_REG_2): Likewise.
	(PREFIX_0FAE_REG_3): Likewise.
	(PREFIX_VEX_3813): Likewise.
	(PREFIX_VEX_3A1D): Likewise.
	(prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
	PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
	PREFIX_VEX_3A1D.
	(vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
	(mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
	PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.

	* i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
	CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
	(cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.

	* i386-opc.h (CpuXsaveopt): New.
	(CpuFSGSBase):Likewise.
	(CpuRdRnd): Likewise.
	(CpuF16C): Likewise.
	(i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
	cpuf16c.

	* i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
	wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
 2010-07-01 21:55:02 +00:00
Alan Modra
09a8ad8d8f * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf 
and mtocrf on EFS.
 2010-07-01 02:29:12 +00:00
Alan Modra
360cfc9c8b remove maxq-coff port 2010-06-29 04:17:34 +00:00
Alan Modra
dc898d5e26 cgen/ 
* cpu/mep.opc (mep_examine_ivc2_insns): Delete set but unused var.
opcodes/
	* mep-dis.c: Regenerate.
 2010-06-28 14:41:59 +00:00
Matthew Gretton-Dann
8e56076649 * gas/config/tc-arm.c (parse_neon_alignment): New function. 
(parse_address_main): Fix Neon load/store alignment parsing.
	* gas/testsuite/gas/arm/neon-ldst-align-bad.l: Update for Neon alignment syntax fix.
	* gas/testsuite/gas/arm/neon-ldst-align-bad.s: Likewise.
	* gas/testsuite/gas/arm/neon-ldst-es.d: Likewise.
	* gas/testsuite/gas/arm/neon-ldst-es.s: Likewise.
	* opcodes/arm-disc.c (parse_insn_neon):  Fix Neon alignment syntax.
 2010-06-28 09:10:25 +00:00
Alan Modra
c7e2358a88 fix set but unused variable warnings 2010-06-27 04:07:55 +00:00
Nick Clifton
6ffe3d995f PR gas/11673 
* m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.

        * gas/m68k/p11673.s: New test.
        * gas/m68k/all.exp: Run the new test.
 2010-06-16 16:27:37 +00:00
Nick Clifton
09ec0d177a 2010-06-16 Vincent Rivire <vincent.riviere@freesbee.fr> 
PR binutils/11676
        * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.

2010-06-16  Nick Clifton  <nickc@redhat.com>

        PR binutils/11676
        * gas/m68k/pr11676.s: New test.
        * gas/m68k/pr11676.d: Expected disassembly.
        * gas/m68k/all.exp: Run the new test.
 2010-06-16 15:12:51 +00:00
Alan Modra
e01d869a3b gas/ 
* config/tc-ppc.c (md_assemble): Emit APUinfo section for
	PPC_OPCODE_E500.
gas/testsuite/
	* gas/ppc/e500.s: Add eieio, mbar and lwsync
	* gas/ppc/e500.d: Likewise.
include/opcode/
	* ppc.h (PPC_OPCODE_E500): Define.
opcodes/
	* ppc-dis.c (ppc_opts):  Remove PPC_OPCODE_E500MC from e500 and
	e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
	* ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
	touch floating point regs and are enabled by COM, PPC or PPCCOM.
	Treat sync as msync on e500.  Treat eieio as mbar 1 on e500.
	Treat lwsync as msync on e500.
 2010-06-14 14:48:05 +00:00
Matthew Gretton-Dann
1f4e495053 * gas/testsuite/gas/arm/thumb-eabi.d: Add case for divided syntax encoding of movs. 
* gas/testsuite/gas/arm/thumb.d: Likewise.
	* gas/testsuite/gas/arm/thumb.s: Likewise.
	* gas/testsuite/gas/arm/thumb2_it.d: Update for change in lsls/movs disassembly.
	* gas/testsuite/gas/arm/thumb2_it_auto.d: Liekwise.
	* gas/testsuite/gas/arm/thumb32.d: Likewise.
	* ld/testsuite/ld-arm/arm-call.d: Handle change in lsls/movs disassembly.
	* ld/testsuite/ld-arm/farcall-thumb-arm-short.d: Likewise.
	* ld/testsuite/ld-arm/farcall-thumb-thumb-blx-pic-veneer.d: Likewise.
	* ld/testsuite/ld-arm/farcall-thumb-thumb-blx.d: Likewise.
	* ld/testsuite/ld-arm/farcall-thumb-thumb-m-pic-veneer.d: Likewise.
	* ld/testsuite/ld-arm/farcall-thumb-thumb-m.d: Likewise.
	* ld/testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d: Likewise.
	* ld/testsuite/ld-arm/farcall-thumb-thumb.d: Likewise.
	* ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad-noeabi.d: Likewise.
	* ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.d: Likewise.
	* ld/testsuite/ld-arm/thumb2-bl-bad-noeabi.d: Likewise.
	* ld/testsuite/ld-arm/thumb2-bl-bad.d: Likewise.
	* opcodes/arm-dis.c (thumb-opcodes): Add disassembly for movs.
 2010-06-07 10:43:52 +00:00
Matthew Gretton-Dann
9d82ec3801 * opcodes/arm-dis.c (print_insn_neon): Ensure disassembly of Neon 
constants is the same on 32-bit and 64-bit hosts.
 2010-05-28 16:04:21 +00:00
Nick Clifton
c3a6ea62fc Fix typo in ChangeLog entry. 2010-05-27 10:45:52 +00:00
Nick Clifton
d8b24b9569 * m68k-dis.c (print_insn_m68k): Emit undefined instructions as 
.short directives so that they can be reassembled.
 2010-05-27 10:43:27 +00:00
Catherine Moore
9db8dccb17 2010-05-26 Catherine Moore <clm@codesourcery.com> 
David Ung  <davidu@mips.com>

        * mips-opc.c: Change membership to I1 for instructions ssnop and
        ehb.

2010-05-26  Catherine Moore  <clm@codesoucery.com>
            Maxim Kuvyrkov  <maxim@codesourcery.com>

        * gas/mips/set-arch.d: Expect ehb.
 2010-05-26 21:49:30 +00:00
H.J. Lu
dfc8cf43a1 Add SIB. 
2010-05-26  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (sib): New.
	(get_sib): Likewise.
	(print_insn): Call get_sib.
	OP_E_memory): Use sib.
 2010-05-26 16:08:23 +00:00
Catherine Moore
f79e2745b2 gas/ 
* config/tc-mips.c (is_opcode_valid): Remove expansionp.
	(macro_build): Change invocation of is_opcode_valid.
	(mips_ip): Likewise.

	gas/testsuite/
	* gas/mips/mips-no-jalx.l: Delete.
	* gas/mips/mips-no-jalx.s: Delete.
	* gas/mips/mips-jalx-2.d: New.
	* gas/mips/mips-jalx-2.s: New.
	* gas/mips/mips.exp (mips-jalx-2): Run new test.
	(mips-no-jalx): Remove deleted test.

	include/
	* opcode/mips.h (INSN_MIPS16): Remove.

	opcodes/
	* mips-dis.c (mips_arch): Remove INSN_MIPS16.
	* mips-opc.c (I16): Remove.
	(mips_builtin_op): Reclassify jalx.
 2010-05-26 12:59:56 +00:00
Alan Modra
51b5d4a8c5 * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde, 
divwe, divdeuo, divweuo, divdeo, divweo for A2.  Add icswepx.
 2010-05-19 03:44:36 +00:00
Alan Modra
85d4ac0b3c Correct wclr encoding. 2010-05-13 06:30:09 +00:00
Nick Clifton
4547cb569c 2010-05-10 Andrew Stubbs <ams@codesourcery.com> 
gas/
        * config/tc-arm.c (aeabi_set_public_attributes): Set Tag_DIV_use.

        gas/testsuite/
        * gas/arm/attr-cpu-directive.d: Add Tag_DIV_use.
        * gas/arm/attr-default.d: Likewise.
        * gas/arm/attr-march-armv1.d: Likewise.
        * gas/arm/attr-march-armv2.d: Likewise.
        * gas/arm/attr-march-armv2a.d: Likewise.
        * gas/arm/attr-march-armv2s.d: Likewise.
        * gas/arm/attr-march-armv3.d: Likewise.
        * gas/arm/attr-march-armv3m.d: Likewise.
        * gas/arm/attr-march-armv4.d: Likewise.
        * gas/arm/attr-march-armv4t.d: Likewise.
        * gas/arm/attr-march-armv4txm.d: Likewise.
        * gas/arm/attr-march-armv4xm.d: Likewise.
        * gas/arm/attr-march-armv5.d: Likewise.
        * gas/arm/attr-march-armv5t.d: Likewise.
        * gas/arm/attr-march-armv5te.d: Likewise.
        * gas/arm/attr-march-armv5tej.d: Likewise.
        * gas/arm/attr-march-armv5texp.d: Likewise.
        * gas/arm/attr-march-armv5txm.d: Likewise.
        * gas/arm/attr-march-armv6-m.d: Likewise.
        * gas/arm/attr-march-armv6.d: Likewise.
        * gas/arm/attr-march-armv6j.d: Likewise.
        * gas/arm/attr-march-armv6k.d: Likewise.
        * gas/arm/attr-march-armv6kt2.d: Likewise.
        * gas/arm/attr-march-armv6t2.d: Likewise.
        * gas/arm/attr-march-armv6z.d: Likewise.
        * gas/arm/attr-march-armv6zk.d: Likewise.
        * gas/arm/attr-march-armv6zkt2.d: Likewise.
        * gas/arm/attr-march-armv6zt2.d: Likewise.
        * gas/arm/attr-march-armv7-a.d: Likewise.
        * gas/arm/attr-march-armv7.d: Likewise.
        * gas/arm/attr-march-armv7a.d: Likewise.
        * gas/arm/attr-march-iwmmxt.d: Likewise.
        * gas/arm/attr-march-iwmmxt2.d: Likewise.
        * gas/arm/attr-march-marvell-f.d: Likewise.
        * gas/arm/attr-march-xscale.d: Likewise.
        * gas/arm/attr-mcpu.d: Likewise.
        * gas/arm/attr-mfpu-arm1020e.d: Likewise.
        * gas/arm/attr-mfpu-arm1020t.d: Likewise.
        * gas/arm/attr-mfpu-arm1136jf-s.d: Likewise.
        * gas/arm/attr-mfpu-arm1136jfs.d: Likewise.
        * gas/arm/attr-mfpu-arm7500fe.d: Likewise.
        * gas/arm/attr-mfpu-fpa.d: Likewise.
        * gas/arm/attr-mfpu-fpa10.d: Likewise.
        * gas/arm/attr-mfpu-fpa11.d: Likewise.
        * gas/arm/attr-mfpu-fpe.d: Likewise.
        * gas/arm/attr-mfpu-fpe2.d: Likewise.
        * gas/arm/attr-mfpu-fpe3.d: Likewise.
        * gas/arm/attr-mfpu-maverick.d: Likewise.
        * gas/arm/attr-mfpu-neon-fp16.d: Likewise.
        * gas/arm/attr-mfpu-neon.d: Likewise.
        * gas/arm/attr-mfpu-softfpa.d: Likewise.
        * gas/arm/attr-mfpu-softvfp+vfp.d: Likewise.
        * gas/arm/attr-mfpu-softvfp.d: Likewise.
        * gas/arm/attr-mfpu-vfp.d: Likewise.
        * gas/arm/attr-mfpu-vfp10-r0.d: Likewise.
        * gas/arm/attr-mfpu-vfp10.d: Likewise.
        * gas/arm/attr-mfpu-vfp3.d: Likewise.
        * gas/arm/attr-mfpu-vfp9.d: Likewise.
        * gas/arm/attr-mfpu-vfpv2.d: Likewise.
        * gas/arm/attr-mfpu-vfpv3-d16.d: Likewise.
        * gas/arm/attr-mfpu-vfpv3.d: Likewise.
        * gas/arm/attr-mfpu-vfpv4-d16.d: Likewise.
        * gas/arm/attr-mfpu-vfpv4.d: Likewise.
        * gas/arm/attr-mfpu-vfpxd.d: Likewise.
        * gas/arm/attr-order.d: Likewise.
        * gas/arm/attr-override-cpu-directive.d: Likewise.
        * gas/arm/attr-override-mcpu.d: Likewise.
        * gas/arm/eabi_attr_1.d: Likewise.

        ld/testsuite/
        * ld-arm/attr-merge-2.attr: Add Tag_DIV_use.
        * ld-arm/attr-merge-2a.s: Likewise.
        * ld-arm/attr-merge-2b.s: Likewise.
        * ld-arm/attr-merge-3a.s: Likewise.
        * ld-arm/attr-merge-3b.s: Likewise.
        * ld-arm/attr-merge-4.attr: Likewise.
        * ld-arm/attr-merge-5.attr: Likewise.
        * ld-arm/attr-merge-6.attr: Likewise.
        * ld-arm/attr-merge-7.attr: Likewise.
        * ld-arm/attr-merge-arch-1.attr: Likewise.
        * ld-arm/attr-merge-arch-2.attr: Likewise.
        * ld-arm/attr-merge-unknown-2.d: Likewise.
        * ld-arm/attr-merge-unknown-2r.d: Likewise.
        * ld-arm/attr-merge-unknown-3.d: Likewise.
        * ld-arm/attr-merge-vfp-1.d: Likewise.
        * ld-arm/attr-merge-vfp-1r.d: Likewise.
        * ld-arm/attr-merge-vfp-2.d: Likewise.
        * ld-arm/attr-merge-vfp-2r.d: Likewise.
        * ld-arm/attr-merge-vfp-3.d: Likewise.
        * ld-arm/attr-merge-vfp-3r.d: Likewise.
        * ld-arm/attr-merge-vfp-4.d: Likewise.
        * ld-arm/attr-merge-vfp-4r.d: Likewise.
        * ld-arm/attr-merge-vfp-5.d: Likewise.
        * ld-arm/attr-merge-vfp-5r.d: Likewise.
        * ld-arm/attr-merge-wchar-00-nowarn.d: Likewise.
        * ld-arm/attr-merge-wchar-00.d: Likewise.
        * ld-arm/attr-merge-wchar-02-nowarn.d: Likewise.
        * ld-arm/attr-merge-wchar-02.d: Likewise.
        * ld-arm/attr-merge-wchar-04-nowarn.d: Likewise.
        * ld-arm/attr-merge-wchar-04.d: Likewise.
        * ld-arm/attr-merge-wchar-20-nowarn.d: Likewise.
        * ld-arm/attr-merge-wchar-20.d: Likewise.
        * ld-arm/attr-merge-wchar-22-nowarn.d: Likewise.
        * ld-arm/attr-merge-wchar-22.d: Likewise.
        * ld-arm/attr-merge-wchar-24-nowarn.d: Likewise.
        * ld-arm/attr-merge-wchar-40-nowarn.d: Likewise.
        * ld-arm/attr-merge-wchar-40.d: Likewise.
        * ld-arm/attr-merge-wchar-42-nowarn.d: Likewise.
        * ld-arm/attr-merge-wchar-44-nowarn.d: Likewise.
        * ld-arm/attr-merge-wchar-44.d: Likewise.
        * ld-arm/attr-merge.attr: Likewise.

2010-04-07  Jie Zhang  <jie@codesourcery.com>

        gas/
        * config/tc-arm.c (aeabi_set_public_attributes): Set
        Tag_ABI_HardFP_use to 1 if a single precision FPU is selected.

        gas/testsuite/
        * gas/arm/attr-mfpu-vfpxd.d: New test.

        bfd/
        * elf32-arm.c (elf32_arm_merge_eabi_attributes): Merge
        Tag_ABI_HardFP_use correctly.

        ld/testsuite/
        * ld-arm/attr-merge-vfp-6.d: New test.
        * ld-arm/attr-merge-vfp-6r.d: New test.
        * ld-arm/attr-merge-vfpv3xd.s: New test.
        * ld-arm/arm-elf.exp: Add attr-merge-vfp-6 and attr-merge-vfp-6r.

2010-05-11  Matthew Gretton-Dann  <matthew.gretton-dann@arm.com>

        * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
        format.
        (print_insn_thumb16): Add support for new %W format.

        * gas/arm/thumb32.d: Fix expected disassembly of ldmia
          instruction.
 2010-05-11 17:36:33 +00:00
Tristan Gingold
6540b386f0 bfd/ 
2010-05-07  Tristan Gingold  <gingold@adacore.com>

	* Makefile.in: Regenerate with automake 1.11.1.
	* aclocal.m4: Ditto.

bfd/doc/
2010-05-07  Tristan Gingold  <gingold@adacore.com>

	* Makefile.in: Regenerate with automake 1.11.1.

binutils/
2010-05-07  Tristan Gingold  <gingold@adacore.com>

	* Makefile.in: Regenerate with automake 1.11.1.
	* aclocal.m4: Ditto.
	* doc/Makefile.in: Ditto.

gas/
2010-05-07  Tristan Gingold  <gingold@adacore.com>

	* Makefile.in: Regenerate with automake 1.11.1.
	* aclocal.m4: Ditto.
	* doc/Makefile.in: Ditto.

gprof/
2010-05-07  Tristan Gingold  <gingold@adacore.com>

	* Makefile.in: Regenerate with automake 1.11.1.
	* aclocal.m4: Ditto.

ld/
2010-05-07  Tristan Gingold  <gingold@adacore.com>

	* Makefile.in: Regenerate with automake 1.11.1.
	* aclocal.m4: Ditto.

opcodes/
2010-05-07  Tristan Gingold  <gingold@adacore.com>

	* Makefile.in: Regenerate with automake 1.11.1.
	* aclocal.m4: Ditto.
 2010-05-07 12:28:50 +00:00