The element index range for the following MIPS MSA instructions: sldi, splati,
copy_s, copy_u, insert and insve is 1 bit too large. This patch fixes this issue.
ChangeLog:
gas/testsuite/gas/mips/
* msa.s: Reduced maximum element index range for sldi, splati,
copy_s, copy_u, insert and insve instructions.
* msa64.s: Likewise.
* micromips@msa.d: Likewise.
* micromips@msa64.d: Likewise.
* msa.d: Likewise.
* msa64.d: Likewise.
include/opcode/
* mips.h: Updated description of +o, +u, +v and +w for MIPS and
microMIPS.
opcodes/
* micromips-opc.c (decode_micromips_operand): Reduced range of +o, +u,
+v and +w.
(micromips_opcodes): Reduced element index range for sldi, splati,
copy_s, copy_u, insert and insve instructions.
* opcodes/mips-opc.c (decode_mips_operand): Reduced range of +o, +u,
+v and +w.
(mips_builtin_opcodes): Reduced element index range for sldi, splati,
copy_s, copy_u, insert and insve instructions.
* config/tc-aarch64.c (set_other_error): New function.
(parse_sys_reg): Add new parameter 'sys_reg' and if non-NULL set
the variable to which it points with 'o'.
(parse_operands): Update; check for write to read-only system
registers or read from write-only ones.
gas/testsuite/
* gas/aarch64/diagnostic.s: Add tests.
* gas/aarch64/diagnostic.l: Update.
* gas/aarch64/tracereg-illegal.d: New file.
* gas/aarch64/tracereg-illegal.l: Ditto.
* gas/aarch64/tracereg-illegal.s: Ditto.
* gas/aarch64/tracereg.d: Ditto.
* gas/aarch64/tracereg.s: Ditto.
include/opcode
* aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
(aarch64_sys_reg_writeonly_p): Ditto.
opcodes/
* aarch64-opc.c (CPENT): New define.
(F_READONLY, F_WRITEONLY): Likewise.
(aarch64_sys_regs): Add trace unit registers.
(aarch64_sys_reg_readonly_p): New function.
(aarch64_sys_reg_writeonly_p): Ditto.
* config/tc-aarch64.c (parse_sys_reg): Update to use aarch64_sys_reg;
call aarch64_sys_reg_deprecated_p and warn about the deprecated
system registers.
gas/testsuite/
* gas/aarch64/deprecated.d: New file.
* gas/aarch64/deprecated.l: New file.
* gas/aarch64/deprecated.s: New file.
* gas/aarch64/sysreg-1.s: Add tests.
* gas/aarch64/sysreg-1.d: Add tests.
include/opcode/
* aarch64.h (aarch64_sys_reg): New typedef.
(aarch64_sys_regs): Change to define with the new type.
(aarch64_sys_reg_deprecated_p): Declare.
opcodes/
* aarch64-opc.c (F_DEPRECATED): New macro.
(aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
F_DEPRECATED.
(aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
AARCH64_OPND_SYSREG.
Currently the disassembler for s390 (by default) assumes that a 31-bit
binary was compiled in "ESA" mode -- and then only disassembles a
limited opcode set. The change upgrades the default to the full "zarch"
opcode set even for 31-bit binaries.
opcodes/
* s390-dis.c (init_disasm): Default to full 'zarch' opcode
availability even for 31-bit programs.
opcodes/
* nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
as the primary name of r30.
gas/
* config/tc-nios2.c (nios2_consume_arg): Make the "ba" warning
also test/refer to "sstatus". Reformat the warning message.
gas/testsuite/
* gas/nios2/warn_nobreak.l: Update text of warning messages.
* gas/nios2/registers.s: Use "sstatus" rather than "ba"
as the primary name of r30.
* gas/nios2/registers.d: Likewise.
* cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
possible compiler warnings when the union's initializer is
actually meant for the 'preg' enum typed member.
* crx-opc.c (REG): Likewise.
2013-10-08 Jan Beulich <jbeulich@suse.com>
* i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
(clflush): Use Anysize instead of Byte|Unspecified.
(prefetch*): Likewise.
* i386-tbl.h: Re-generate.
* config/tc-arm.c (T16_32_TAB): Add _udf.
(do_t_udf): New function.
(insns): Add "udf".
* gas/arm/udf-bad.s: New file.
* gas/arm/udf-bad.d: New file.
* gas/arm/udf-bad.l: New file.
* gas/arm/udf.s: New file.
* gas/arm/udf.d: New file.
* gas/arm/udf.l: New file.
* arm-dis.c (arm_opcodes): Add udf.
(thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
(thumb32_opcodes): Add udf.w.
(print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
* s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
For the load fp integer instructions only the suppression flag was
new with z196 version.
immediate is not suitable for the 32-bit ABI.
* gas/aarch64/illegal.s: Add illegal constant for logical
operation.
* gas/aarch64/illegal.l: Add expected error message.
* mips.h (M_DEXT, M_DINS): Delete.
opcodes/
* micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
Use +H rather than +C for the real "dext".
* mips-opc.c (mips_builtin_opcodes): Likewise.
gas/
* config/tc-mips.c (report_bad_range, report_bad_field): Delete.
(macro): Remove M_DEXT and M_DINS handling.
gas/testsuite/
* gas/mips/ext-ill.l, gas/mips/mips64r2-ill.l: Expect DEXT and DINS
error messages to have the same form as the EXT and INS ones.
* gas/mips/micromips-insn32.d, gas/mips/micromips-noinsn32.d,
gas/mips/micromips-trap.d, gas/mips/micromips.d,
gas/mips/micromips@mips64r2.d, gas/mips/mips64r2.d: Expect
"dext" and "dins" instead of "dextm", "dextu", "dinsm" and "dinsu".
2013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
* mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
VCLIPW.
gas/
2013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
* config/tc-mips.c (match_vu0_suffix_operand): Allow single-channel
suffixes to be elided too.
(mips_lookup_insn): Don't reject INSN2_VU0_CHANNEL_SUFFIX here.
(mips_ip): Assume .xyzw if no VU0 suffix is specified. Allow +N
to be omitted too.
gas/testsuite/
2013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
* gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l,
gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d: Allow
single-channel suffixes to be elided.
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com>
* mips.h: Document new VU0 operand characters.
(OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
(OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
(OP_REG_R5900_ACC): New mips_reg_operand_types.
(INSN2_VU0_CHANNEL_SUFFIX): New macro.
(mips_vu0_channel_mask): Declare.
opcodes/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com>
* mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
(print_vu0_channel): New function.
(print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
(print_insn_args): Handle '#'.
(print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
* mips-opc.c (mips_vu0_channel_mask): New constant.
(decode_mips_operand): Handle new VU0 operand types.
(VU0, VU0CH): New macros.
(mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
Use "+6" rather than "G" for QMFC2 and QMTC2.
gas/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
Richard Sandiford <rdsandiford@googlemail.com>
* config/tc-mips.c (MAX_OPERANDS): Bump to 6.
(RWARN): Bump to 0x8000000.
(RTYPE_VI, RTYPE_VF, RTYPE_R5900_I, RTYPE_R5900_Q, RTYPE_R5900_R)
(RTYPE_R5900_ACC): New register types.
(RTYPE_MASK): Include them.
(R5900_I_NAMES, R5900_Q_NAMES, R5900_R_NAMES, R5900_ACC_NAMES): New
macros.
(reg_names): Include them.
(mips_parse_register_1): New function, split out from...
(mips_parse_register): ...here. Add a channels_ptr parameter.
Look for VU0 channel suffixes when nonnull.
(reg_lookup): Update the call to mips_parse_register.
(mips_parse_vu0_channels): New function.
(OT_CHANNELS, OT_DOUBLE_CHAR): New mips_operand_token_types.
(mips_operand_token): Add a "channels" field to the union.
Extend the comment above "ch" to OT_DOUBLE_CHAR.
(mips_parse_base_start): Match -- and ++. Handle channel suffixes.
(mips_parse_argument_token): Handle channel suffixes here too.
(validate_mips_insn): Handle INSN2_VU0_CHANNEL_SUFFIX.
Ignore OP_VU0_MATCH_SUFFIX when calculating the used bits.
Handle '#' formats.
(md_begin): Register $vfN and $vfI registers.
(operand_reg_mask): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
(convert_reg_type): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
(match_vu0_suffix_operand): New function.
(match_operand): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
(macro): Use "+7" rather than "E" for LDQ2 and STQ2.
(mips_lookup_insn): New function.
(mips_ip): Use it. Allow "+K" operands to be elided at the end
of an instruction. Handle '#' sequences.
gas/testsuite/
2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
* gas/mips/r5900-vu0.d: Expect $vfN and $viN instead of numeric
coprocessor registers.
* gas/mips/r5900-all-vu0.s, gas/mips/r5900-all-vu0.d,
gas/mips/r5900-full-vu0.s, gas/mips/r5900-full-vu0.d,
gas/mips/r5900-error-vu0.s, gas/mips/r5900-error-vu0.l: New tests.
* gas/mips/mips.exp: Run them.
* mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
(mips_int_operand_min, mips_int_operand_max): New functions.
(mips_decode_pcrel_operand): Use mips_decode_int_operand.
opcodes/
* mips-formats.h (PCREL): Reorder parameters and update the definition
to match new mips_pcrel_operand layout.
(JUMP, JALX, BRANCH): Update accordingly.
* mips16-opc.c (decode_mips16_operand): Likewise.
gas/
* config/tc-mips.c (match_int_operand): Use mips_int_operand_min
and mips_int_operand_max.
(mips16_immed_operand, mips16_immed_operands, MIPS16_NUM_IMMED):
Delete.
(mips16_immed_operand, mips16_immed_in_range_p): New functions.
(mips16_immed, mips16_extended_frag): Use them. Use mips_int_operand
instead of mips16_immed_operand.
* mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
(MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
(MIPS16_INSN_COND_BRANCH): Delete.
opcodes/
* mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
(WR_SP): Replace with...
(MOD_SP): ...this.
(mips16_opcodes): Update accordingly.
* mips-dis.c (print_insn_mips16): Likewise.
gas/
* config/tc-mips.c (compact_branch_p, uncond_branch_p): Use the same
flags for MIPS16 and non-MIPS16 instructions.
(gpr_mod_mask): Move the INSN2_MOD_SP case outside the micromips block.
(gpr_read_mask): Use INSN2_READ_GPR_31 for MIPS16 instructions too.
(gpr_write_mask): Remove MIPS16_INSN_WRITE_SP handling.
(can_swap_branch_p, get_append_method): Use the same flags for MIPS16
and non-MIPS16 instructions. Fix formatting.
* mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
for operands that are hard-coded to $0.
* micromips-opc.c (micromips_opcodes): Likewise.
* mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
for the single-operand forms of JALR and JALR.HB.
* micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
and JALRS.HB.
