Nick Clifton
917bca4f21
Add support for disabling alignment checks when performing GDB interface
...
calls or SWI emulaiton routines. (Alignment checking code has not yet been
contributed).
2001-02-28 01:04:24 +00:00
Nick Clifton
2ef048fc9f
Remove Prefetch abort for breakpoints. Instead set the state to RESUME.
2001-02-16 22:04:22 +00:00
Nick Clifton
44e23e575b
Add code to preserve processor mode when a prefetch
...
abort is signalled after processing a breakpoint.
2001-02-15 02:38:15 +00:00
Nick Clifton
fae0bf59e6
Add parentheses ready for future conbtribution
2001-02-01 20:56:35 +00:00
Nick Clifton
dda308f5fd
Update base address register after restoring register bank.
2001-02-01 20:39:51 +00:00
Nick Clifton
ac1c9d3aad
Fix test for StoreDouble Instruction.
2000-12-19 00:58:04 +00:00
Nick Clifton
df38a86eec
oops - remove redundant prototype introduced in previous delta
2000-12-08 01:39:48 +00:00
Nick Clifton
760a7bbec5
Add emulation of double word load and store instructions.
2000-12-08 01:38:47 +00:00
Nick Clifton
f1129fb8ff
Add support for ARM's v5TE architecture and Intel's XScale extenstions
2000-11-30 01:55:12 +00:00
Nick Clifton
4bc1de7b2d
Compute write back value for post increment loads before
...
performing the load in case the offset register is overwritten.
2000-08-15 00:10:52 +00:00
Alexandre Oliva
66210567f0
* armemu.c (ARMul_Emulate, t_undefined): Proceed to next insn.
2000-07-04 06:54:48 +00:00
Alexandre Oliva
e063aa3bd8
* armemu.h (INSN_SIZE): New macro.
...
(SET_ABORT): Save CPSR in SPSR and set LR.
* armemu.c (ARMul_Emulate, isize): Set to INSN_SIZE.
(WriteR15, WriteSR15): Do not discard bit 1 in Thumb mode.
* arminit.c (ARMul_Abort): Use new SETABORT and INSN_SIZE.
2000-07-04 06:52:30 +00:00
Alexandre Oliva
13b6dd6f68
* armemu.c (LoadSMult): Use WriteR15() to discard the least
...
significant bits of PC.
2000-07-04 06:39:39 +00:00
Alexandre Oliva
892c6b9d8f
* armemu.h (WRITEDESTB): New macro.
...
* armemu.c (ARMul_Emulate26, bl): Use WriteR15Branch() to
modify PC. Moved the existing logic...
(WriteR15Branch): ... here. New function.
(WriteR15, WriteSR15): Drop the two least significant bits.
(LoadSMult): Use WriteR15Branch() to modify PC.
(LoadMult): Use WRITEDESTB() instead of WRITEDEST().
2000-07-04 06:35:36 +00:00
Alexandre Oliva
4ef2594f4e
* armemu.h (PSR_FBITS, PSR_SBITS, PSR_XBITS, PSR_CBITS): New.
...
(SETPSR_F, SETPSR_S, SETPSR_X, SETPSR_C): New macros.
(SETPSR, SET_INTMODE, SETCC): Removed.
* armsupp.c (ARMul_FixCPSR, ARMul_FixSPSR): Do not test bit
mask. Use SETPSR_* to modify PSR.
(ARMul_SetCPSR): Load all bits from value.
* armemu.c (ARMul_Emulate, msr): Do not test bit mask.
2000-07-04 06:06:30 +00:00
Alexandre Oliva
e62263b8ec
* armemu.c (ARMul_Emulate): Compute writeback value before
...
loading, since the offset register may be the destination
register.
2000-07-04 05:30:43 +00:00
Alexandre Oliva
f9c22bc3a4
* armemu.c (Multiply64): Fix computation of flag N.
2000-06-22 20:42:34 +00:00
Alexandre Oliva
ee9a777240
* armemu.c (MultiplyAdd64): Fix computation of flag N.
2000-06-22 20:03:32 +00:00
Nick Clifton
c1a72ffdd6
Add support for v4 SystemMode.
2000-05-30 17:13:37 +00:00
Frank Ch. Eigler
5d0d395e94
* arm abort fix
...
2000-03-11 Philip Blundell <philb@gnu.org>
* armemu.c (LoadSMult, LoadMult): Correct handling of aborts.
Patch from Allan Skillman <Allan.Skillman@arm.com>.
2000-04-10 15:35:56 +00:00
Nick Clifton
6d358e869b
Fix compile time warning messages.
2000-02-08 20:54:27 +00:00
Jason Molenda
dfcd3bfb6f
import gdb-2000-02-04 snapshot
2000-02-05 07:30:26 +00:00
Jason Molenda
c2d11a7da0
import gdb-1999-12-06 snapshot
1999-12-07 03:56:43 +00:00
Jason Molenda
43e526b9b4
import gdb-1999-07-12 snapshot
1999-07-12 11:15:22 +00:00
Stan Shebs
7a292a7adf
import gdb-19990422 snapshot
1999-04-26 18:34:20 +00:00
Stan Shebs
c906108c21
Initial creation of sourceware repository
1999-04-16 01:35:26 +00:00
