* configure: Regenerated.
* configure.ac: Add test for System V shared memory and semaphore.
* debug.c, debug.h: Add trace support for new devices.
* hw_sem.c, hw_shm.c: New files.
* Makefile.in: Add hw_sem.c and hw_shm.c.
command interpreter to use to run the input file. This is
necessary because otherwise SHELL is taken from the user's
environment, and not from the makefile that invoked this script
and the user might not be running an sh-like shell.
* cris/Makefile.in: Pass -shell parameter to genmloop.sh.
* fr30/Makefile.in: Likewise.
* frv/Makefile.in: Likewise.
* i960/Makefile.in: Likewise.
* iq2000/Makefile.in: Likewise.
* m32r/Makefile.in: Likewise.
* frv/mloop.in: Add missing start of line comment marker.
* main.c (main): Add option to set raw console.
* mem.h (m32c_use_raw_console): Declare.
* mem.c (m32c_sim_restore_console): Only restore console if it's
been previously set.
(m32c_use_raw_console): Define.
(mem_get_byte): Set raw console if m32c_use_raw_console is set.
2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
* cris/configure: Regenerate.
sim/common:
2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
* aclocal.m4: Include ../../config/acx.m4.
* common.m4: Use ACX_PKGVERSION and ACX_BUGURL.
* configure, config.in: Regenerate.
* Make-common.in (LIB_OBJS): Add version.o.
(version.c, version.o): New rules.
* run.c: Include version.h.
(usage): Add help parameter. Print output either to stdout or
stderr depending on that parameter.
(print_version): New.
(main): Check for --help and --version.
* run-sim.h (sim_target_display_usage): Add help parameter.
* version.h: New.
sim/arm:
2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
* configure: Regenerate.
* wrapper.c (sim_target_display_usage): Add help parameter.
sim/cr16:
2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
* configure: Regenerate.
sim/d10v:
2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
* configure: Regenerate.
sim/erc32:
2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
* configure: Regenerate.
sim/frv:
2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
* configure: Regenerate.
sim/h8300:
2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
* configure: Regenerate.
sim/iq2000:
2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
* configure: Regenerate.
sim/m32c:
2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
* configure: Regenerate.
sim/m32r:
2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
* configure: Regenerate.
sim/m68hc11:
2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
* configure: Regenerate.
sim/mcore:
2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
* configure: Regenerate.
sim/mips:
2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
* configure: Regenerate.
sim/mn10300:
2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
* configure: Regenerate.
sim/ppc:
2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
* configure.ac: Use ACX_PKGVERSION and ACX_BUGURL.
* configure, config.in: Regenerated.
* Makefile.in (LIB_OBJ): Add version.o.
(version.c, version.o): New rules.
* psim.c (psim_usage): Add help parameter. Print the bug URL.
Exit with code 0 for help.
(psim_options): Update calls to psim_usage. Handle --help and
--version.
* psim.h (psim_usage): Update prototype.
* main.c (main): Update psim_usage call.
sim/sh:
2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
* configure: Regenerate.
sim/sh64:
2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
* configure: Regenerate.
sim/v850:
2008-06-06 Vladimir Prus <vladimir@codesourcery.com>
Daniel Jacobowitz <dan@codesourcery.com>
Joseph Myers <joseph@codesourcery.com>
* configure: Regenerate.
* cpu.h (m32c_opcode_pc): New.
(in_gdb): New.
* gdb-if.c (sim_open): Add Timer A support. Support unbuffered
console.
* int.c (trigger_interrupt): Manage the U flag properly.
(trigger_based_interrupt): Likewise.
(trigger_fixed_interrupt): New.
(trigger_peripheral_interrupt): New.
* int.h (trigger_peripheral_interrupt): New.
* m32c.opc: Use m32c_opcode_pc throughout, as needed.
(decode_m32c): Detect jump-to-zero with traceback.
(BRK): Try to do the right thing, keeping track of whether we're
in gdb or not, and if the user has provided a handler or not.
(GBRK): Alternate break opcode for gdb, in case the user's app
needs to use BRK for itself.
(BRK2): Implement.
* main.c: Add Timer A support. Support TCP-based console.
(setup_tcp_console): New.
(main): Add Timer A support. Support TCP-based console.
* mem.c: Add Timer A support. Support TCP-based console.
(mem_ptr): Enhance NULL pointer detection.
(stdin_ready): New.
(m32c_sim_restore_console): New.
(mem_get_byte): Check for console input ready.
(update_timer_a): New.
* r8c.opc (SSTR): Use r0l, not r0h.
(REIT): Fix return frame logic.
* reg.c (print_flags): New.
(trace_register_changes): Use it.
(m32c_dump_all_registers): New.
* timer_a.h: New.
* load.c: Fix indentation.
* trace.c: Fix indentation.
* trace.h: Fix indentation.
ChangeLog:
Add simulator for National cr16 processor.
* cr16: New directory with cr16 simulator files.
* configure.ac: Add an entry for National cr16 target.
* configure: Regenerate.
* mips.igen (check_fmt_p): Provide a separate mips32r2 definition
that unconditionally allows fmt_ps.
(ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, CVT.S.PU)
(FLOOR.L.fmt, LWXC1, MADD.fmt, MSUB.fmt, NMADD.fmt, NMSUB.fmt)
(PLL.PS, PLU.PS, PUL.PS, PUU.PS, ROUND.L.fmt, TRUNC.L.fmt): Change
filter from 64,f to 32,f.
(PREFX): Change filter from 64 to 32.
(LDXC1, LUXC1): Provide separate mips32r2 implementations
that use do_load_double instead of do_load. Make both LUXC1
versions unpredictable if SizeFGR () != 64.
(SDXC1, SUXC1): Extend to mips32r2, using do_store_double
instead of do_store. Remove unused variable. Make both SUXC1
versions unpredictable if SizeFGR () != 64.
(display_mem_info): New static variable.
(mips_option_handler): Handle OPTION_INFO_MEMORY.
(mips_options): Add info-memory and memory-info.
(sim_open): After processing the command line and board specification, check display_mem_info.
If it is set then call the real handler for the --memory-info command line switch.
(parse_size): Handle a suffix on the size value.
* sim-options.c (standard_options): Mention that the mem-size switch accepts suffixes.
(standard_option_handler): Handle a suffix on the size value.
* configure.ac (sim_mipsisa3264_configs): New variable.
(mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make
every configuration support all four targets, using the triplet to
determine the default.
* configure: Regenerate.
* config/tc-mips.c (mips_set_options, mips_opts, file_ase_dspr2,
ISA_SUPPORTS_DSPR2_ASE, MIPS_CPU_ASE_DSPR2): Add DSP R2 ASE support.
(macro_build): Add case '2'.
(macro): Expand M_BALIGN to nop, packrl.ph or balign.
(validate_mips_insn): Add support for balign instruction.
(mips_ip): Handle DSP R2 instructions. Support balign instruction.
(OPTION_DSPR2, OPTION_NO_DSPR2, OPTION_COMPAT_ARCH_BASE,
md_parse_option, mips_after_parse_args): Add -mdspr2 and -mno-dspr2
command line options.
(s_mipsset): Add support for .set dspr2 and .set nodspr2 directives.
(md_show_usage): Add -mdspr2 and -mno-dspr2 help output.
* doc/c-mips.texi, doc/as.texinfo: Document -mdspr2, -mno-dspr2,
.set dspr2, .set nodspr2.
[ gas/testsuite/ChangeLog ]
* gas/mips/mips32-dspr2.s, gas/mips/mips32-dspr2.d: New test for
DSP R2.
* gas/mips/mips.exp: Run new test.
[ include/opcode/Changelog ]
* mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction.
(INSN_DSPR2): Add flag for DSP R2 instructions.
(M_BALIGN): New macro.
[ opcodes/ChangeLog ]
* mips-dis.c (mips_arch_choices): Add DSP R2 support.
(print_insn_args): Add support for balign instruction.
* mips-opc.c (D33): New shortcut for DSP R2 instructions.
(mips_builtin_opcodes): Add DSP R2 instructions.
[ sim/mips/ChangeLog ]
* Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
* configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
Add dsp2 to sim_igen_machine.
* configure: Regenerate.
* dsp.igen (do_ph_op): Add MUL support when op = 2.
(do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
(mulq_rs.ph): Use do_ph_mulq.
(MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
* mips.igen: Add dsp2 model and include dsp2.igen.
(MFHI, MFLO, MTHI, MTLO): Extend these instructions for
for *mips32r2, *mips64r2, *dsp.
(MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
for *mips32r2, *mips64r2, *dsp2.
* dsp2.igen: New file for MIPS DSP REV 2 ASE.
[ sim/testsuite/sim/mips/ChangeLog ]
* basic.exp: Run the dsp2 test.
* utils-dsp.inc (dspckacc_astio, dspck_tsimm): New macro.
* mips32-dsp2.s: New test.
uninterpreted formats. If fmt is one of the uninterpreted types
don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
fmt_word, and fmt_uninterpreted_64 like fmt_long.
(store_fpr): When writing an invalid odd register, set the
matching even register to fmt_unknown, not the following register.
* interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
the the memory window at offset 0 set by --memory-size command
line option.
(sim_store_register): Handle storing 4 bytes to an 8 byte floating
point register.
(sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
register.
(sim_monitor): When returning the memory size to the MIPS
application, use the value in STATE_MEM_SIZE, not an arbitrary
hardcoded value.
(cop_lw): Don' mess around with FPR_STATE, just pass
fmt_uninterpreted_32 to StoreFPR.
(cop_sw): Similarly.
(cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
(cop_sd): Similarly.
* mips.igen (not_word_value): Single version for mips32, mips64
and mips16.
* gdb/target.c (target_flash_erase): Do not return void value.
(target_flash_done): Likewise.
* gdb/cli/cli-cmds.c (source_command): Likewise.
Reported by timeless@gmail.com:
* wrapper.c (sim_target_parse_arg_array): Do not return void value.
(cris_unknown_syscall_action): Declare.
* cris/sim-if.c (cris_unknown_syscall_action): Define.
(cris_options): Add cris-unknown-syscall option.
(cris_option_handler): Correct comment about and error message for
invalid --cris-cycles argument. Handle --cris-unknown-syscall.
* cris/traps.c: Include stdarg.h
(cris_unknown_syscall): New function.
(cris_break_13_handler): Instead of sim_io_eprintf and
sim_engine_halt, call cris_unknown_syscall to handle more or less
unknown syscalls. Adjust code as necessary to handle return
value.
(process): Don't write as much to the pipe as to trig the
inordinate-amount test in the sim pipe machinery. Correct test of
write return-value; check only that pipemax bytes were
successfully written. For error-case, emit strerror as well.
(main): Add a second read.
* cris/Makefile.in (CONFIG_DEVICES): Remove redundant setting.
(dv-cris.o, dv-rv.o rvdummy$(EXEEXT), rvdummy.o): New rules.
(all): Depend on rvdummy$(EXEEXT).
* cris/configure.ac: Call SIM_AC_OPTION_WARNINGS. Check for
sys/socket.h and sys/select.h. Call SIM_AC_OPTION_HARDWARE,
default off.
* cris/configure: Regenerate.
* cris/cris-sim.h (cris_have_900000xxif): Declare here.
(enum cris_interrupt_type, crisv10deliver_interrupt)
(crisv32deliver_interrupt: New declarations.
* cris/cris-tmpl.c [WITH_HW] (MY (f_model_insn_after)): Call
sim_events_tickn and set state-events member work_pending when it's
time for the next event.
[WITH_HW] (MY (f_specific_init)): Set CPU-model-specific
interrupt-delivery function.
* cris/crisv10f.c (MY (deliver_interrupt)): New function.
* cris/crisv32f.c (MY (deliver_interrupt)): New function.
* cris/devices.c: Include hw-device.h.
(device_io_read_buffer) [WITH_HW]: Call hw_io_read_buffer.
(device_io_write_buffer): Only perform 0x900000xx-functions if
cris_have_900000xxif is nonzero. Else if WITH_HW defined,
call hw_io_write_buffer. Add return 0 last in function.
* cris/sim-if.c (cris_have_900000xxif): Now global.
(sim_open) [WITH_HW]: Clear deliver_interrupt cpu member.
Force "-model" option, effectively.
* cris/sim-main.h (cris_interrupt_delivery_fn): New type.
(struct _sim_cpu) [WITH_HW]: New member deliver_interrupt.
(mem_put_hi): Hook in simulated trace port.
(mem_get_byte): Hook in simulated uart control port.
* opc2c: Be more picky about matching special comments.
* r8c.opc (shift_op): Limit shift counts to -16..16.
(BMcnd): Map conditional codes.
* reg.c (condition_true): Mask condition code to 4 bits.
* syscalls.c: Include local syscall.h.
* syscall.h: New, copied from libgloss.
sim_resume. Expect target signal numbers from sim_stop_reason.
* wrapper.c (gdb/signals.h): Include it.
(SIGTRAP): Don't define.
(SIGBUS): Likewise.
(sim_stop_reason): Use TARGET_SIGNAL_* instead of SIG*.
* sim-reason.c (sim_stop_reason): Use
sim_signal_to_target, not sim_signal_to_host.
* sim-signal.c (sim_signal_to_host): Fix typo.
(sim_signal_to_target): New function.
* interp.c (gdb/signals.h): Include it.
(sim_stop_reason): Use TARGET_SIGNAL_*.
* interf.c: (gdb/signals.h): Include it.
(sim_stop_reason): Use TARGET_SIGNAL_*.
* sim_calls.c (gdb/signals.h): Include it.
(sim_stop_reason): Use TARGET_SIGNAL_*.
* psim.c (cntrl_c_simulation): Use TARGET_SIGNAL_*.
(open_map): Use TARGET_O_ACCMODE, TARGET_O_RDONLY and
TARGET_O_WRONLY.
(cris_break_13_handler) <case TARGET_SYS_fcntl>: Add support for
F_GETFL on fd 0, 1 and 2.
last_open_fd, last_open_flags.
* cris/traps.c: Don't include targ-vals.h.
(TARGET_O_ACCMODE): Define.
(cris_break_13_handler): Set new _sim_cpu members.
<case TARGET_SYS_fcntl>: Support special case of F_GETFL.
Rearrange code as switch. Emit "unimplemented" abort for
unimplemented fcntl calls.
* sim/arm/armos.c: Include limits.h
(unlink): Remove this macro. It is unused in this file and
conflicts with sim_callback->unlink.
(PATH_MAX): Define as 1024 if not already defined.
(ReadFileName): New function.
(SWIopen): Fix a potential buffer overflow.
(SWIremove): New function.
(SWIrename): Ditto.
(ARMul_OSHandleSWI): Handle the RDP calls SWI_IsTTY,
SWI_Remove, and SWI_Rename, as well as the RDI calls
AngelSWI_Reason_IsTTY, AngelSWI_Reason_Remove, and
AngelSWI_Reason_Rename.
* cpu.c,cpu.h,decode.c,decode.h,model.c,sem.c: Regenerate.
Contribute the following changes:
2003-09-29 Dave Brolley <brolley@redhat.com>
* frv-sim.h: Use CGEN_ATTR_VALUE_ENUM_TYPE in place of
CGEN_ATTR_VALUE_TYPE.
* mloop.in: Ditto.
* pipeline.c: Ditto.
* traps.c: Ditto.
* armdefs.h: Define ARMsword and ARMsdword. Use stdint.h when
available.
* armemu.c: Use them.
* armvirt.c (ARMul_MemoryInit): Use correct type for size.
* configure.ac: Check for stdint.h.
* config.in: Regenerate.
* configure: Regenerate.
* mips.igen (mips32r2, mips64r2): New ISA models. Add new model
tags to all instructions which are applicable to the new ISAs.
(do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
vr.igen.
* mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
instructions.
* vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
to mips.igen.
* configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
* configure: Regenerate.
* common/callback.c (PIPE_BUF): Provide default refinition.
(os_lstat): Use stat if lstat is not available on the host.
(os_ftruncate): Return EINVAL if not available on the host.
(os_truncate): Ditto.
* common/configure.ac: Check for lstat, truncate and ftruncate.
* common/configure: Regenerate.
* common/config.in: Regenerate.
(ARMulEmulate32): Call handle_v6_insn when a possible v6 insn is found.
* armdefs.h (struct ARMul_State): Add new field: is_v6.#
(ARM_v6_Prop): Define.
* arminit.c (ARMul_NewState): Initialise the v6 flag.
(ARMul_SelectProcessor): Determine if the v6 flag should be set.
* wrapper.c (sim_create_inferior): For unknown architectures, default to allowing the v6 instructions.
2005-02-28 Jim Blandy <jimb@redhat.com>
* aclocal.m4 (SIM_AC_OPTION_WARNINGS): Don't include
-Wuninitialized in the default list of build warnings if CFLAGS is
set, and doesn't include -O. (Using -Wuninitialized without
optimization produces a warning, which interferes with compilation
with -Werror.)
sim/ChangeLog:
2005-02-28 Jim Blandy <jimb@redhat.com>
* d10v/configure.ac, igen/configure.ac, m68hc11/configure.ac,
mips/configure.ac, mn10300/configure.ac, v850/configure.ac:
Regenerated, after change to common/aclocal.m4.
* sim/erc32/float.c (set_fsr): Do not use deprecated multi-line
strings.
(clear_accex): Ditto.
* sim/erc32/interf.c: Remove the redeclaration of fprintf.
* sim/erc32/sis.c: Ditto.
* sim/erc32/exec.c: Add missing semicolon.
* sim/erc32/func.c: Remove definitions of generic_print_address,
generic_symbol_at_address, buffer_read_memory and perror_memory, as
they are already defined in opcodes/dis-buf.c.
2005-02-09 Jim Blandy <jimb@redhat.com>
* cgen-sim.scm (load-files): Don't load fixup.scm. (See
corresponding change in the sim/common directory.)
sim/common/ChangeLog:
2005-02-09 Jim Blandy <jimb@redhat.com>
* Make-common.in (CGEN): Load guile.scm, and include a trailing
'-s' argument.
(CGEN_FLAGS_TO_PASS): Include single quotes around the reference
to $(CGEN), to ensure that the command substitution happens where
the variable is referenced in the submake, not when the submake's
arguments are expanded.
(cgen.sh): Be prepared for the 'cgen' argument to contain spaces.
(arch, cpu, decode, cpu-decode, defs, desc): Place the name of the
application Scheme script directly after ${cgen}; don't precede it
with a -s.
* callback.c [HAVE_LIMITS_H]: Include limits.h.
Include libiberty.h.
(os_close, os_read, os_write, os_fstat, os_ftruncate): Support fd
being either end of a pipe.
(os_pipe, os_pipe_empty, os_pipe_nonempty): New functions.
(os_shutdown): Clear pipe state.
(default_callback): Initialize new members.
(cb_store_target_endian): Renamed from store, new first parameter
host_callback *cb, drop last parameter big_p. Take endianness
from cb.
(cb_host_to_target_stat): Change to use cb_store_target_endian.
Remove variable big_p.
* nrun.c (main): Initialize default_callback.target_endian.
2005-01-12 Andrew Cagney <cagney@gnu.org>
* configure.ac: Update to use ../common/common.m4.
* configure: Re-generate.
Index: mn10300/ChangeLog
2005-01-12 Andrew Cagney <cagney@gnu.org>
* configure.ac: Update to use ../common/common.m4.
* configure: Re-generate.
Index: d10v/ChangeLog
2005-01-12 Andrew Cagney <cagney@gnu.org>
* configure.ac: Update to use ../common/common.m4.
* configure: Re-generate.
Index: erc32/ChangeLog
2005-01-12 Andrew Cagney <cagney@gnu.org>
* configure.ac: Update to use ../common/common.m4.
* configure: Re-generate.
Index: frv/ChangeLog
2005-01-12 Andrew Cagney <cagney@gnu.org>
* configure.ac: Update to use ../common/common.m4.
* configure: Re-generate.
Index: h8300/ChangeLog
2005-01-12 Andrew Cagney <cagney@gnu.org>
* configure.ac: Update to use ../common/common.m4.
* configure: Re-generate.
Index: m32r/ChangeLog
2005-01-12 Andrew Cagney <cagney@gnu.org>
* configure.ac: Update to use ../common/common.m4.
* configure: Re-generate.
Index: mcore/ChangeLog
2005-01-12 Andrew Cagney <cagney@gnu.org>
* configure.ac: Update to use ../common/common.m4.
* configure: Re-generate.
Index: mips/ChangeLog
2005-01-12 Andrew Cagney <cagney@gnu.org>
* configure.ac: Update to use ../common/common.m4.
* configure: Re-generate.
Index: v850/ChangeLog
2005-01-12 Andrew Cagney <cagney@gnu.org>
* configure.ac: Update to use ../common/common.m4.
* configure: Re-generate.
Index: common/ChangeLog
2005-01-12 Andrew Cagney <cagney@gnu.org>
* common.m4: New file, based on of aclocal.m4.
Index: arm/ChangeLog
2005-01-12 Andrew Cagney <cagney@gnu.org>
* configure.ac: Update to use ../common/common.m4.
* configure: Re-generate.
Committed by Kei Sakamoto.
* traps-linux.c (m32r_trap): Add entries of the following dummy system
calls: __NR_mmap2, __NR_lchown32, __NR_getuid32, __NR_getgid32,
__NR_geteuid32, __NR_getegid32, __NR_getgroups32, __NR_fchown32,
__NR_setfsuid32, __NR_setfsgid32, __NR_getresuid32,
__NR_getresgid32 and __NR_chown32.
* syscall.h: Add new definitions of system call number.
* sim-options.c (STANDARD_OPTIONS): New member OPTION_SYSROOT.
(standard_options): Support --sysroot=<path>.
(standard_option_handler): Handle OPTION_SYSROOT.
* syscall.c (simulator_sysroot): Define, initialized empty.
(get_path): Prepend simulator_sysroot to absolute file path.
[HAVE_STRING_H]: Include string.h.
[!HAVE_STRING_H && HAVE_STRINGS_H]: Include strings.h.
* nrun.c [HAVE_UNISTD_H]: Include unistd.h.
(main): If simulator_sysroot is not empty, chdir there.
* sim-config.h (simulator_sysroot): Declare.
st_dev, st_ino, st_mode, st_nlink, st_uid, st_gid, st_rdev,
st_size, st_blksize, st_blocks, st_atime, st_mtime and st_ctime.
* aclocal.m4 (SIM_CHECK_MEMBER, SIM_CHECK_MEMBERS_1)
(SIM_CHECK_MEMBERS): New macros.
* callback.c (cb_host_to_target_stat): Use temporary macro ST_x
for struct stat member test and write. Add ST_x calls for each
struct stat member tested in configure.in. Wrap each ST_x call in
#ifdef of configure macro for that member.
* configure, config.in: Regenerate.
add sub-dependencies for other sim files that they include.
(sim_main_headers): Use sim-*_h rules.
(sim-load.o): Depend on sim-basics_h, not sim_main_headers.
Committed by Andrew Cagney.
* traps-linux.c: Don't include linux/module.h.
(m32r_trap): Remove dummy systemcall's entry of __NR_ustat and
__NR_get_kernel_syms.
Committed by Andrew Cagney.
* configure.in: Check for sys/mount.h, sys/vfs.h, sys/statfs.h.
Check for struct statfs.
* emul_netbsd.c: If not HAVE_STRUCT_STATFS, #undef HAVE_FSTATFS.
* configure, config.in: Regenerate.
* bandor.s: New file.
* bandornot.s: New file.
* bclr.s: New file.
* bld.s: New file.
* bldnot.s: New file.
* bset.s: New file.
* bst.s: New file.
* bxor.s: New file.
* clip.s: New file.
* div.s: New file.
* fail.s: New file, make sure fail works.
* fsca.s: New file.
* fsrra.s: New file.
* mov.s: New file.
* mulr.s: New file.
* pass.s: New file, make sure pass works.
* pushpop.s: New file.
* resbank.s: New file.
* testutils.inc (bf8k, bt8k, assertmem): New macros.
* interp.c (RAISE_EXCEPTION_IF_IN_DELAY_SLOT): New macro.
(in_delay_slot): New flag variable.
(Delay_Slot): Set in_delay_slot.
(sim_resume): Reset in_delay_slot after leaving code switch.
* gencode.c (op tab): Call RAISE_EXCEPTION_IF_IN_DELAY_SLOT for all
instructions not allowed in delay slots.
Commited by Corinna Vinschen <vinschen@redhat.com>
Introduce SH2a support.
* interp.c: Change type of jump table to short. Add various macros.
(sim_load): Save the bfd machine code.
(sim_create_inferior): Ditto.
(union saved_state_type): Add tbr, ibnr and ibcr registers.
Move bfd_mach to end of struct. Add regstack pointer.
(init_dsp): Don't swap contents of sh_dsp_table any more. Instead
use it directly in its own switch statement. Allocate space for 512
register banks.
(do_long_move_insn): New function.
(do_blog_insn): Ditto.
(trap): Use trap #13 and trap #14 to set ibnr and ibcr.
* gencode.c: Move movx/movy insns into separate switch statement.
(op tab): Add sh2a insns. Reject instructions that are disabled
on that chip.
(gensim_caselist): Generate default case here instead of in caller.
(gensim): Generate two separate switch statements. Call
gensim_caselist once for each (for movsxy_tab and for tab).
Add tokens for r15 and multiple regs.
(conflict_warn, warn_conflicts): Add for debugging.
2004-07-20 Jim Blandy <jimb@redhat.com>
Use a fixed register numbering when communicating with the PowerPC
simulator.
* ppc-tdep.h (struct gdbarch_tdep): New member: 'sim_regno'.
* rs6000-tdep.c: #include "sim-regno.h" and "gdb/sim-ppc.h".
(set_sim_regno, init_sim_regno_table, rs6000_register_sim_regno):
New functions.
(rs6000_gdbarch_init): Register rs6000_register_sim_regno. Call
init_sim_regno_table.
* Makefile.in (gdb_sim_ppc_h): New variable.
(rs6000-tdep.o): Update dependencies.
include/gdb/ChangeLog:
2004-07-20 Jim Blandy <jimb@redhat.com>
* sim-ppc.h: New file.
sim/ppc/ChangeLog:
2004-07-20 Jim Blandy <jimb@redhat.com>
Use a fixed register numbering when communicating with the PowerPC
simulator.
* sim_calls.c: #include "registers.h" and "gdb/sim-ppc.h"; do not
include GDB's "defs.h".
(gdb_register_name_table): New variable.
(gdb_register_name_table_size): New enum constant.
(gdb_register_name): New function.
(sim_fetch_register, sim_store_register): Use gdb_register_name,
instead of calling gdbarch_register_name.
* Makefile.in (GDB_SIM_PPC_H): New variable.
(DEFS_H): Delete variable.
(sim_calls.o): Update dependencies.
2004-07-26 Andrew Cagney <cagney@gnu.org>
Problem from Olaf Hering <olh@suse.de>.
* Makefile.in (install-man, installdirs): Add DESTDIR prefix.
Index: ppc/ChangeLog
2004-07-26 Andrew Cagney <cagney@gnu.org>
Problem from Olaf Hering <olh@suse.de>.
* Makefile.in (install, installdirs): Add DESTDIR.
2003-07-23 Richard Sandiford <rsandifo@redhat.com>
* compile.c (sim_resume): Make sure that dst.reg refers to the
right register byte in mova/sz.l @(dd,RnL),ERn.
2003-07-21 Richard Sandiford <rsandifo@redhat.com>
* compile.c (sim_resume): Zero-extend immediate to muls, mulsu,
mulxs, divs and divxs.
sim/testsuite/sim/h8300/ChangeLog:
2003-07-22 Michael Snyder <msnyder@redhat.com>
* mul.s: Don't try to use negative immediate (it's always
unsigned).
* div.s: Ditto.
* utils-fpu.inc (enable_fpu, ckm_fp_cc): New macros.
(clrset_fp_cc): Fix mask used for upper 7 condition codes.
* utils-mdmx.inc: Include utils-fpu.inc.
(enable_mdmx): Use enable_fpu.
* utils-fpu.inc: New file.
* utils-mdmx.inc: New file.
* mdmx-ob.s: New file.
* mdmx-ob-sb1.s: New file.
* basic.exp: Run new mdmx-ob and mdmx-ob-sb1 tests.
* sim/mips/basic.exp (run_hilo_test): New procedure.
(models): Only list models that are included in the configuration.
(submodels): New variable, set to submodels of the above.
(mips64vr-*-elf, mips64vrel-*-elf): New configuration stanza.
Run hilo-hazard-[123].s.
(MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
* mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
separate implementations for mipsIV and mipsV. Use new macros to
determine whether the restrictions apply.
* frv.c (frvbf_iacc_cut): Rework, taking rounding into account.
testsuite/
* sim/frv/fr400/scutss.cgs: Fix tests to account for rounding.
Add some new ones.
* gencode.c (table): Change from char to short.
(dumptable): Change generated table from char to short.
* interp.c (sh_jump_table, sh_dsp_table, ppi_table): char to short.
(init_dsp): Compute size of sh_dsp_table.
(sim_resume): Change jump_table from char to short.
Committed by Andrew Cagney.
* mloopx.in: Update copyright.
(xextract-pbb): Fixed trap for system calls operation in parallel.
* mloop2.in (xextract-pbb): Ditto.
2004-01-26 Chris Demetriou <cgd@broadcom.com>
* configure.in (mips*-*-*): Configure in testsuite.
* configure: Regenerate.
[ sim/testsuite/ChangeLog ]
2004-01-26 Chris Demetriou <cgd@broadcom.com>
* sim/mips: New directory. Tests for the MIPS simulator.
[ sim/testsuite/sim/mips/ChangeLog ]
2004-01-26 Chris Demetriou <cgd@broadcom.com>
* basic.exp: New file.
* testutils.inc: New file.
* sanity.s: New file.
* mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
(check_mult_hilo): Improve comments.
(check_div_hilo): Likewise. Also, fork off a new version
to handle mips32/mips64 (since there are no hazards to check
in MIPS32/MIPS64).
* gencode.c (expand_opcode): Simplify and reorganize.
Eliminate "shift" parameter. Eliminate "4 bits at a time"
assumption. Flatten switch statement to a single level.
Add "eeee" token for even-numbered registers.
(bton): Delete.
(fsca): Use "eeee" token.
(ppi_moves): Rename to "expand_ppi_movxy". Do the ddt
[movx/movy] expansion here, as well as the ppi expansion.
(gensim_caselist): Accept 'eeee' along with 'nnnn'.
(O_RDONLY): Do not define.
(O_WRONLY): Likewise.
(O_RDWR): Likewise.
(targ-vals.h): Include it.
(translate_open_mode): Use TARGET_O_* instead of O_*.
(SWIopen): Likewise.
* Makefile.in (armos.o): Depend on targ-vals.h.
(SPR_REGNUM_MAX): Delete.
* frv.c (gdb/sim-frv.h): Include.
(frvbf_fetch_register, frvbf_store_register): Use register number
constants from gdb/sim-frv.h. Check availability of general
purpose and float registers.
* frv-sim.h (REGNUM_LR): Removed.
(REGNUM_SPR_MIN,REGNUM_SPR_MAX): New macros.
* frv.c (frvbf_fetch_register): Fetch SPR registers based on
REGNUM_SPR_MIN and REGNUM_SPR_MAX. Check whether SPRs are implemented.
Return 0 for an unimplemented register. Return the length of the data
for an implemented register.
(frvbf_store_register): Ditto.
* h8300/compile.c : Addition of extern variable h8300_normal_mode
(SP) : Handle normal mode
(bitfrom) : Use normal mode flag to return suitable value
(lvalue) : Use normal mode flag to return command line location
(decode) : Decode instruction correctly for normal mode
(init_pointers) : Initialise memory correctly for normal mode
(sim_resume) : Handle cases for normal mode using h8300_normal_mode flag
(sim_store_register) : Handle 2 byte PC for normal mode
(sim_fetch_register) : Handle 2 byte PC for normal mode
(set_h8300h) : Set normal mode flag as per architechture
(sim_load) : Allocate 64K for normal mode instead of bigger memory
* callback.h (struct host_callback_struct): New members ftruncate
and truncate.
gdb:
sim/common:
* callback.c (os_ftruncate, os_truncate): New functions.
(default_callback): Initialize ftruncate and truncate members.
sim/sh:
* syscall.h (SYS_truncate, SYS_ftruncate): Define.
* interp.c (trap): Add support for SYS_ftruncate and SYS_truncate.
* sim/frv/testutils.inc (or_gr_immed): New macro.
* sim/frv/fp_exception-fr550.cgs: Write insns using
unaligned registers into the program in order to
cause the required exceptions.
* sim/frv/fp_exception.cgs: Ditto.
* sim/frv/regalign.cgs: Ditto.
* sim/frv/fr550: New subdirectory.
* sim/frv/fr400/*.cgs: Add fr550 as appropriate.
* sim/frv/fr500/*.cgs: Add fr550 as appropriate.
* sim/frv/interrupts/*.cgs: Add fr550 as appropriate.
* sim/frv/interrupts/*-fr550.cgs: New test cases for fr550.
* profile.h (update_FR_ptime): New prototype.
(update_FRdouble_ptime): Ditto.
(update_SPR_ptime): Ditto.
(increase_ACC_busy): Ditto.
(enforce_full_acc_latency): Ditto.
(post_wait_for_SPR): Ditto.
* profile.c (update_FR_ptime): Moved here from profile-fr500.c.
(update_FRdouble_ptime): Ditto.
(update_SPR_ptime): New function.
(increase_ACC_busy): Ditto.
(enforce_full_acc_latency): Ditto.
(vliw_wait_for_fdiv_resource): Correct resource name.
(vliw_wait_for_fsqrt_resource): Ditto.
(post_wait_for_SPR): New function.
* profile-fr500.c (frvbf_model_fr500_u_commit): New function.
(frvbf_model_fr500_u_gr2fr): Pass out_FRk as output register to
adjust_float_register_busy.
(frvbf_model_fr500_u_gr_load): Record latency of SPR registers.
(frvbf_model_fr500_u_fr_load): Wait for and record latency of SPR
registers.
(frvbf_model_fr500_u_float_arith): Ditto.
(frvbf_model_fr500_u_float_dual_arith): Ditto.
(frvbf_model_fr500_u_float_div): Ditto.
(frvbf_model_fr500_u_float_sqrt): Ditto.
(frvbf_model_fr500_u_float_convert): Ditto.
(update_FR_ptime): Moved to profile.c
(update_FRdouble_ptime): Moved to profile.c
* profile-fr400.c (update_FR_ptime): Removed. Identical to functions
for other machines.
(update_FRdouble_ptime): Ditto.
* arch.h,cpu.h,sem.c,decode.[ch],model.c,sem.c: Regenerated.
* registers.c (frv_check_spr_read_access): Check for access to
ACC4-ACC63 and ACCG4-ACCG63.
* profile.h (frv-desc.h): #include it.
(spr_busy): New member of FRV_PROFILE_STATE.
(spr_latency): Ditto.
(GNER_FOR_GR): New macro.
(FNER_FOR_FR): New maccro.
(update_SPR_latency): New function.
(vliw_wait_for_SPR): New function.
* profile.c (profile-fr550.h): #include it.
(update_latencies): Update SPR latencies.
(update_target_latencies): Ditto.
(update_SPR_latency): New function.
(vliw_wait_for_SPR): New function.
* profile-fr500.c (frvbf_model_fr500_u_idiv): Record GNER latency.
(frvbf_model_fr500_u_trap): Removed unused variable, ps.
(frvbf_model_fr500_u_check): Ditto.
(frvbf_model_fr500_u_clrgr): New unit modeller for fr500.
(frvbf_model_fr500_u_clrfr): Ditto.
(frvbf_model_fr500_u_spr2gr): Wait for SPR.
(frvbf_model_fr500_u_gr2spr): Ditto.
* frv-sim.h (H_SPR_ACC4): New macro.
(H_SPR_ACCG4): New macro;
(H_SPR_ACC0): Removed.
(H_SPR_ACCG0): Removed.
* arch.h,model.c,sem[ch],decode.[ch]: Regenerated.
* profile.c (slot_names): FM1 was listed twice. Changed first
instance to FM0. Added IALL, FMALL and FMLOW.
(print_parallel): Don't examine slots with no insns.
On behalf of Doug Evans <dje@sebabeach.org>
* Makefile.in (stamp-arch,stamp-cpu): Pass archfile to cgen.
Remove copying of .cpu file to cgen/cpu, no longer needed.
On behalf of Doug Evans <dje@sebabeach.org>
* cgen.sh: New arg archfile.
* Make-common.in (cgen-arch,cgen-cpu,cgen-defs,cgen-decode,
cgen-cpu-decode,cgen-desc): Update call to cgen.sh.
* sim/frv/interrupts/Ipipe-fr400.cgs: New file.
* sim/frv/interrupts/Ipipe-fr500.cgs: New file.
* sim/frv/interrupts/Ipipe.cgs: Remove (replaced by above).
Dave Brolley <brolley@redhat.com>
* frv/: New directory, simulator for the Fujitsu FR-V.
* testsuite/frv-elf/: New directory.
* testsuite/sim/frv/: New directory.
* configure.in: Add frv configury.
* configure: Regenerate.
2003-08-28 Andrew Cagney <cagney@redhat.com>
* dv-glue.c (hw_glue_finish): Change %d to %ld to match sizeof.
* sim-options.c (print_help): Cast the format with specifier to
"int".
Index: mn10300/ChangeLog
2003-08-28 Andrew Cagney <cagney@redhat.com>
* dv-mn103ser.c (do_polling_event): Change type of "serial_reg" to
"long".
(read_status_reg): Cast "serial_reg" to "long".
* dv-mn103tim.c (do_counter_event): Change type of "timer_nr" to
"long".
(do_counter6_event, write_mode_reg, write_tm6md): Ditto.
* sim/sh/gencode.c ( tab[] ): Addition of MAC.L handler and
correction for MAC.W handler
* sim/sh/interp.c ( macl ): New Function. Implementation of
MAC.L handler.
* MAINTAINERS: Andrew Cagney (mips) and Geoff Keating (ppc) drop
maintenance. List igen and sh maintainers. Mention that target
and global maintainers pick up the slack.
the physical address in virtual address.
(struct _sim_cpu): Add memory bank members.
* m68hc11_sim.c (cpu_initialize): Clear memory bank parameters.
* interp.c (sim_hw_configure): Create memory bank according to memory
bank parameters.
(sim_get_bank_parameters): New function to obtain memory bank config
from the symbol table.
(sim_prepare_for_program): Call it to obtain the memory bank parameters.
(sim_open): Call sim_prepare_for_program.
* dv-m68hc11.c (m68hc11cpu_io_write_buffer): Use memory bank parameters
to check if address is within bank window.
(m68hc11cpu_io_read_buffer): Likewise.
(attach_m68hc11_regs): Map the memory bank according to memory bank
parameters.
* cmpw.s: Add test for less-than-zero immediate.
* shll.s: Test for shll reg, reg.
* shlr.s: Test for shlr reg, reg.
* mova.s: Add dozens of new mova tests.
* compile.c (decode): Enhancements for mova.
Initialize cst, reg, and rdisp inside the loop, for each
new instruction. Defer correction of the disp2 values until
later, and then adjust them by the size of the first operand,
rather than the size of the instruction.
(sim_resume): For mova, adjust the size of the second operand
according to the type of the first operand (INDEXB vs. INDEXW).
In cases where there is only one operand, the other two must
both be composed on the fly.
* gencode.c (pshl): Change < to <= (shift by 16 is allowed).
Cast argument of >> to unsigned to prevent sign extension.
(psha): Change < to <= (shift by 32 is allowed).
* gencode.c: A few more fix-ups of refs and defs.
(frchg): Raise SIGILL if in double-precision mode.
(ldtlb): We don't simulate cache, so this is a no-op.
(movsxy_tab): Correct a few bit pattern errors.
* gencode.c (ppi_gensim): For a conditional ppi insn, if the
condition is false, we want to return (not break). A break
will take us to the end of the function where registers will
be updated, whereas the desired outcome is for nothing to change.
* gencode.c (op tab): Some fix-ups of refs and defs.
(ocbi, ocbp): Cache not simulated, but may cause memory fault.
(gensym_caselist): Add default case to switch statement.
(expand_ppi_code): Add default case to switch statement.
Written by matthew green <mrg@redhat.com>, with fixes from Aldy
Hernandez <aldyh@redhat.com>, Jim Wilson <wilson@redhat.com>, and
Nick Clifton <nickc@redhat.com>.
* ppc-instructions: Include altivec.igen and e500.igen.
(model_busy, model_data): Add vr_busy and vscr_busy.
(model_trace_release): Trace vr_busy and vscr_busy.
(model_new_cycle): Update vr_busy and vscr_busy.
(model_make_busy): Update vr_busy and vscr_busy.
* registers.c (register_description): Add Altivec and e500
registers.
* psim.c (psim_read_register, psim_read_register): Handle Altivec
and e500 registers.
* ppc-spr-table (SPEFSCR): Add VRSAVE and SPEFSCR registers.
* configure.in (sim_filter): When *altivec* add "av". When *spe*
or *simd* add e500.
(sim_float): When *altivec* define WITH_ALTIVEC. When *spe* add
WITH_E500.
* configure: Re-generate.
* e500.igen, altivec.igen: New files.
* e500_expression.h, altivec_expression.h: New files.
* idecode_expression.h: Update copyright. Include
"e500_expression.h" and "altivec_expression.h".
* e500_registers.h, altivec_registers.h: New files.
* registers.h: Update copyright. Include "e500_registers.h" and
"altivec_registers.h".
(registers): Add Altivec and e500 specific registers.
* Makefile.in (IDECODE_H): Add "idecode_e500.h" and
"idecode_altivec.h".
(REGISTERS_H): Add "e500_registers.h" and "altivec_registers.h".
(tmp-igen): Add dependencies on altivec.igen and e500.igen .
From matthew green <mrg@redhat.com>:
* sim-fpu.h: Update copyright.
(sim_fpu_fraction, sim_fpu_guard): New prototypes.
* sim-fpu.c: Update copyright.
(sim_fpu_fraction, sim_fpu_guard): New inline functions.
* cgen-trace.h (sim_disasm_read_memory): Update args to be compatible
with disassemble_info:read_memory_func.
* cgen-trace.c (sim_disasm_read_memory): Ditto.
* compile.c: Replace "Hitachi" with "Renesas".
(decode): Distinguish AV_H8S from AV_H8H.
(sim_resume): H8SX can use any register for TAS.
(decode): Add support for VECIND.
(sim_resume): Implement rte/l and rts/l.
(GETSR): New macro (actually old macro reincarnated).
(decode): Add handling for IMM2.
(sim_resume): Drop extra block around jmp, jsr, rts.
Add handling for trapa and rte.
For divxu.b, change 0xffff mask to 0xff.
(set_h8300h): Add bfd_mach_h8300sxn machine.
* compile.c (sim_info): Fix typo in output.
* h8300/compile.c (set_h8300h): Replace 'flag' arguments
with a bfd_machine argument, and decode it inline.
Check for bfd_mach_h8300hn and bfd_mach_h8300sn.
2003-03-20 D.Venkatasubramanian <dvenkat@noida.hcltech.com>
* compile.c (cmdline_location): Added function to
return the location of 8-bit (256 locations) where the
Command Line arguments would be stored.
(decode): Added a TRAP to 0xcc for Commandline
processing using pseudo opcode O_SYS_CMDLINE.
(sim_resume): Added handling of O_SYS_CMDLINE Trap.
(sim_create_inferior): Setting a pointer to
Commandline Args array.
* inst.h: Added a new variable ptr_command_line for
storing pointer to Commandline array.
2003-03-14 D.Venkatasubramanian <dvenkat@noida.hcltech.com>
* compile.c (decode): Added code for some more magic traps.
* compile.c (sim_resume): Added support for File I/O system
calls through callback to host_system.
System calls provided support for :
open, read, write, lseek, close, stat, fstat
Only basic support for stat and fstat.
* gen-engine.c (print_engine_issue_prefix_hook): Don't add the
global prefix to ENGINE_ISSUE_PREFIX_HOOK.
(print_engine_issue_postfix_hook): Likewise ENGINE_ISSUE_POSTFIX_HOOK.
This patch fixes the gcc.dg/nest.c failures for sh-elf.
Fri Oct 11 16:22:28 2002 J"orn Rennecke <joern.rennecke@superh.com>
* interp.c (trap): Return int. Take extra parameter for address
of the trap instruction. Changed all callers.
Add case 33 for profiling.
* gencode.c (trapa): Handle trap 33 using the trap function.
Add read of vector for generic traps.
bank window to some virtual address to read from extended memory.
(m68hc11cpu_io_write_buffer): Likewise for writing.
(attach_m68hc11_regs): When use_bank property is defined, attached
to the 68HC12 16K memory bank window.
* interp.c (sim_hw_configure): Create memory region for banked
memory.
* sim-main.h (M6812_CALL_INDIRECT): Add to enum.
(m6811_regs): Add page register.
(cpu_set_page, cpu_get_page): New macros.
(phys_to_virt): New function.
(cpu_get_indexed_operand_addr, cpu_return): Declare.
* gencode.c: Identify indirect addressing mode for call and fix daa.
(gen_function_entry): New param to tell if src8/dst8 locals are
necessary.
(gen_interpreter): Use it to avoid generation of unused variables.
* interp.c (sim_fetch_register): Allow to read page register; page
register, A, B and CCR are only 1 byte wide.
(sim_store_register): Likewise for writing.
* mips.igen (do_load_double, do_store_double): New functions.
(LDC1, SDC1): Rename to...
(LDC1b, SDC1b): respectively.
(LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
* sim-sh.h: Add enum constants for sh[1-4], sh3e, sh3?-dsp,
renumbering the sh-dsp registers to use distinct numbers.
sim/sh:
* Makefile.in (interp.o): Depend on $(srcroot)/include/gdb/sim-sh.h.
* interp.c: Include "gdb/sim-sh.h".
(sim_store_register, sim_fetch_register): Use constants defined there.
gdb:
* sh-tdep.c (sh_dsp_register_sim_regno): New function.
(sh_gdbarch_init): Use it for sh-dsp.
* mdmx.c (SD_): Delete.
(Unpredictable): Re-define, for now, to directly invoke
unpredictable_action().
(mdmx_acc_op): Fix error in .ob immediate handling.
Ed Satterthwaite <ehs@broadcom.com>
* mips3d.igen: New file which contains MIPS-3D ASE instructions.
* Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
* mips.igen: Include mips3d.igen.
(mips3d): New model name for MIPS-3D ASE instructions.
(CVT.W.fmt): Don't use this instruction for word (source) format
instructions.
* cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
(fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
(fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
(NR_FRAC_GUARD, IMPLICIT_1): New macros.
* sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
(RSquareRoot1, RSquareRoot2): New macros.
(fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
(fp_rsqrt2): New functions.
* configure.in: Add MIPS-3D support to mipsisa64 simulator.
* configure: Regenerate.
* cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
(value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
(fp_inv_sqrt, fpu_format_name): Add paired-single support.
(convert): Note that this function is not used for paired-single
format conversions.
(ps_lower, ps_upper, pack_ps, convert_ps): New functions.
* mips.igen (FMT, MOVtf.fmt): Add paired-single support.
(check_fmt_p): Enable paired-single support.
(ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
(PUU.PS): New instructions.
(CVT.S.fmt): Don't use this instruction for paired-single format
destinations.
* sim-main.h (FP_formats): New value 'fmt_ps.'
(ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
(PSLower, PSUpper, PackPS, ConvertPS): New macros.
* mips.igen (MOVN, MOVZ): Trace result.
(TNEI): Print "tnei" as the opcode name in traces.
(CEIL.W): Add disassembly string for traces.
(RSQRT.fmt): Make location of disassembly string consistent
with other instructions.
Ed Satterthwaite <ehs@broadcom.com>
* cp1.c: Fix more comment spelling and formatting.
(value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
(denorm_mode): New function.
(fpu_unary, fpu_binary): Round results after operation, collect
status from rounding operations, and update the FCSR.
(convert): Collect status from integer conversions and rounding
operations, and update the FCSR. Adjust NaN values that result
from conversions. Convert to use sim_io_eprintf rather than
fprintf, and remove some debugging code.
* cp1.h (fenr_FS): New define.
(z8k_inv_list): Delete global.
(DIRTY_HACK): Delete macro.
(makelist): Delete global.
(main): Delete code making a list. Delete dirty hack code. Use
lookup_inst instead of z8k_inv_list.
* list.c: Delete file.
* Makefile.in (writecode): Do not link in list.o.
(list.o): Delete target.
* sim-main.h (FGRIDX): Remove, replace all uses with...
(FGR_BASE): New macro.
(FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
(_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
(NR_FGR, FGR): Likewise.
* interp.c: Replace all uses of FGRIDX with FGR_BASE.
* mips.igen: Likewise.
* sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
(Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
file, remove PARAMS from prototypes.
(value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide
simulator state arguments.
(ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to
pass simulator state arguments.
* cp1.c (SD): Redefine as CPU_STATE(cpu).
(store_fpr, convert): Remove 'sd' argument.
(value_fpr): Likewise. Convert to use 'SD' instead.
Ed Satterthwaite <ehs@broadcom.com>
* configure.in (mipsisa64sb1*-*-*): New target for supporting
Broadcom SiByte SB-1 processor configurations.
* configure: Regenerate.
* sb1.igen: New file.
* mips.igen: Include sb1.igen.
(sb1): New model.
* Makefile.in (IGEN_INCLUDE): Add sb1.igen.
* mdmx.igen: Add "sb1" model to all appropriate functions and
instructions.
* mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
(ob_func, ob_acc): Reference the above.
(qh_acc): Adjust to keep the same size as ob_acc.
* sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
(MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
* interp.c (sim_create_inferior): Add comment.
From Alan Matsuoka <alanm@redhat.com>:
From 2001-04-27 Jason Eckhardt <jle@cygnus.com>:
* simops.c (OP_4400): Output "mvf0f" instead of "mf0f".
(OP_4401): Output "mvf0t" instead of "mf0t".
(OP_460B): Do not output a flag register.
(OP_4609): Do not output a flag register.
* sim-d10v.h: New file. Moved from include/sim-d10v.h.
* Makefile.in (INCLUDE): Add "gdb/sim-d10v.h".
* interp.c: Include "gdb/sim-d10v.h" instead of "sim-d10v.h".
* d10v-tdep.c: Include "gdb/sim-d10v.h" instead of "sim-d10v.h".
* Makefile.in (sim_d10v_h): Update definition.
include:
* dis-asm.h (print_insn_shl, print_insn_sh64l): Remove prototype.
gdb:
* sh-tdep.c (gdb_print_insn_sh64): Delete.
(gdb_print_insn_sh): Just set info->endian and use print_insn_sh.
(sh_gdbarch_init): Always use gdb_print_insn_sh.
opcodes:
* disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh.
* sh-dis.c (LITTLE_BIT): Delete.
(print_insn_sh, print_insn_shl): Deleted.
(print_insn_shx): Renamed to
(print_insn_sh). No longer static. Handle SHmedia instructions.
Use info->endian to determine endianness.
* sh64-dis.c (print_insn_sh64, print_insn_sh64l): Delete.
(print_insn_sh64x): No longer static. Renamed to
(print_insn_sh64). Removed pfun_compact and endian arguments.
If we got an uneven address to indicate SHmedia, adjust it.
Return -2 for SHcompact instructions.
sim/sh64:
* sim-if.c (sh64_disassemble_insn): Use print_insn_sh instead of
print_insn_shl.
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* callback.c: Use 'deprecated' rather than 'depreciated.'
[ igen/ChangeLog ]
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* igen.c: Use 'deprecated' rather than 'depreciated.'
[ mips/ChangeLog ]
2002-05-01 Chris Demetriou <cgd@broadcom.com>
* interp.c: Use 'deprecated' rather than 'depreciated.'
* sim-main.h: Likewise.
* cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
which wouldn't compile anyway.
* sim-main.h (unpredictable_action): New function prototype.
(Unpredictable): Define to call igen function unpredictable().
(NotWordValue): New macro to call igen function not_word_value().
(UndefinedResult): Remove.
* interp.c (undefined_result): Remove.
(unpredictable_action): New function.
* mips.igen (not_word_value, unpredictable): New functions.
(ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
(do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
NotWordValue() to check for unpredictable inputs, then
Unpredictable() to handle them.
* ppc-instructions (lswx): Do the register control with the
register count. Initialize the right register in the loop.
(mtfsfi) : Correct prefix for the instruction.
* cp1.c (fpu_format_name): New function to replace...
(DOFMT): This. Delete, and update all callers.
(fpu_rounding_mode_name): New function to replace...
(RMMODE): This. Delete, and update all callers.
* interp.c: Move FPU support routines from here to...
* cp1.c: Here. New file.
* Makefile.in (SIM_OBJS): Add cp1.o to object list.
(cp1.o): New target.
* configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
* mips.igen (mips32, mips64): New models, add to all instructions
and functions as appropriate.
(loadstore_ea, check_u64): New variant for model mips64.
(check_fmt_p): New variant for models mipsV and mips64, remove
mipsV model marking fro other variant.
(SLL) Rename to...
(SLLa) this.
(CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
for mips32 and mips64.
(DCLO, DCLZ): New instructions for mips64.
* mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
immediate or code as a hex value with the "%#lx" format.
(ANDI): Likewise, and fix printed instruction name.
cpu struct.
(sim_hw_configure): Connect the capture input/output events.
* sim-main.h (_sim_cpu): New member hw_cpu.
(m68hc11cpu_set_oscillator): Declare.
(m68hc11cpu_clear_oscillator): Declare.
(m68hc11cpu_set_port): Declare.
* dv-m68hc11.c (m68hc11_options): New for oscillator commands.
(m68hc11cpu_ports): New input ports and output ports to reflect
the HC11 IOs.
(m68hc11_delete): Cleanup any running oscillator.
(attach_m68hc11_regs): Create the input oscillators.
(make_oscillator): New function.
(find_oscillator): New function.
(oscillator_handler): New function.
(reset_oscillators): New function.
(m68hc11cpu_port_event): Handle the new input ports.
(m68hc11cpu_set_oscillator): New function.
(m68hc11cpu_clear_oscillator): New function.
(get_frequency): New function.
(m68hc11_option_handler): New function.
(m68hc11cpu_set_port): New function.
(m68hc11cpu_io_write): Post the port output events.
* dv-m68hc11spi.c (set_bit_port): Use m68hc11cpu_set_port to set
the output port value.
* dv-m68hc11tim.c (m68hc11tim_port_event): Handle CAPTURE event
by latching the TCNT value in the register.
vector address according to cpu mode.
(interrupts_initialize): Move reset portion to the above.
(interrupt_names): New table to give a name to interrupts.
(idefs): Handle pulse accumulator interrupts.
(interrupts_info): Print the interrupt history.
(interrupt_option_handler): New function.
(interrupt_options): New table of options.
(interrupts_update_pending): Keep track of when interrupts are
raised and implement breakpoint-on-raise-interrupt.
(interrupts_process): Keep track of when interrupts are taken
and implement breakpoint-on-interrupt.
* interrupts.h (struct interrupt_history): Define.
(struct interrupt): Keep track of the interrupt history.
(interrupts_reset): Declare.
(interrupts_initialize): Update prototype.
* m68hc11_sim.c (cpu_reset): Reset interrupts.
(cpu_initialize): Cleanup.
* sim-main.h (status_UX, status_SX, status_KX, status_TS)
(status_PX, status_MX, status_CU0, status_CU1, status_CU2)
(status_CU3): New definitions.
* sim-main.h (ExceptionCause): Add new values for MIPS32
and MIPS64: MDMX, MCheck, CacheErr. Update comments
for DebugBreakPoint and NMIReset to note their status in
MIPS32 and MIPS64.
(SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
(SignalExceptionCacheErr): New exception macros.
* mips.igen (check_fpu): Enable check for coprocessor 1 usability.
* sim-main.h (COP_Usable): Define, but for now coprocessor 1
is always enabled.
(SignalExceptionCoProcessorUnusable): Take as argument the
unusable coprocessor number.
* mips.igen (check_fmt, check_fmt_p): New functions to check
whether specific floating point formats are usable.
(ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
(FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
(ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
Use the new functions.
(do_c_cond_fmt): Remove format checks...
(C.cond.fmta, C.cond.fmtb): And move them into all callers.
* mips.igen (loadstore_ea): New function to do effective
address calculations.
(do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
CACHE): Use loadstore_ea to do effective address computations.
* mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
add a comma) so that it more closely match the MIPS ISA
documentation opcode partitioning.
(PREF): Put useful names on opcode fields, and include
instruction-printing string.
* mips.igen (check_u64): New function which in the future will
check whether 64-bit instructions are usable and signal an
exception if not. Currently a no-op.
(DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
* mips.igen (check_fpu): New function which in the future will
check whether FPU instructions are usable and signal an exception
if not. Currently a no-op.
(ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
* mips.igen (do_load_left, do_load_right): Move to be immediately
following do_load.
(do_store_left, do_store_right): Move to be immediately following
do_store.
* mips.igen: Add some additional comments about supported
models, and about which instructions go where.
(BC1b, MFC0, MTC0, RFE): Sort supported models in the same
order as is used in the rest of the file.
* mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
indicating that ALU32_END or ALU64_END are there to check
for overflow.
(DADD): Likewise, but also remove previous comment about
overflow checking.
* mips.igen (ADDI): Print immediate value.
(BREAK): Print code.
(DADDIU, DSRAV, DSRLV): Print correct instruction name.
(SLL): Print "nop" specially, and don't run the code
that does the shift for the "nop" case.
* igen.c (main): Change -I to add include paths for :include:
files.
Implement -G as per sim/igen, with just gen-icache=N support.
Call load_insn_table() with the built include path.
* ld-insn.c (parse_include_entry): New. Load an :include: file.
(load_insn_table): New `includes' argument. Look for :include:
entries and call parse_include_entry() for them.
(main): Adjust load_insn_table() call.
* ld-insn.h (model_include_fields): New enum.
(load_insn_table): Update prototype.
* table.c (struct _open_table, struct _table): Rework
structures to handle included files.
(table_push): Move the guts of table_open() here.
* table.c (struct _open table, struct table): Make table object an
indirect ptr to the current table file.
(current_line, new_table_entry, next_line): Make file arg type
open_table.
(table_open): Use table_push.
(table_entry_read): Point variable file at current table, at eof, pop
last open table.
* misc.h (NZALLOC): New macro. From sim/igen.
* table.h, table.c (table_push): New function.
(tmp-gencode, gencode.o, gencode): Delete targets.
(simops.h): New file.
($(BUILT_SRC_FROM_IGEN)): Do not depend on simops.h.
* gencode.c: Delete file.
* hw_htab.c (htab_map_binary): Don't try to map the text section
when it is empty.
* emul_chirp.c (map_over_chirp_note): Default load-base to -1 not
CHIRP_LOAD_BASE.
(emul_chirp_create): Map in the interrupt table.
* lib/sim-defs.exp (run_sim_test): Include a description such as
"assembling" or "linking" that identifies the phase a test fails
in, for easier analysis of failures.
* interp.c (sim_resume): New function from sim-resume.c, install
the stepping event after having processed the pending ticks.
(has_stepped): Likewise.
(sim_info): Produce an output only if verbose or STATE_VERBOSE_P.
pending interrupts.
* interrupts.c (interrupts_process): Keep track of the last number
of masked insn cycles.
(interrupts_initialize): Clear last number of masked insn cycles.
(interrupts_info): Report them.
(interrupts_update_pending): Compute clear and set masks of
interrupts and clear the interrupt bits before setting them
(due to SCI interrupt sharing).
* interrupts.h (struct interrupts): New members last_mask_cycles
and xirq_last_mask_cycles.
2001-04-18 matthew green <mrg@redhat.com>
* armcopro.c (write_cp15_reg): Set CHANGEMODE if endianness changes.
(read_cp15_reg): Make non-static.
(XScale_cp15_LDC): Update for write_cp15_reg() change.
(XScale_cp15_MCR): Likewise.
(XScale_cp15_write_reg): Likewise.
(XScale_check_memacc): New function. Check for breakpoints being
activated by memory accesses. Does not support the Branch Target
Buffer.
(XScale_set_fsr_far): New function. Set FSR and FAR for XScale.
(XScale_debug_moe): New function. Set the debug Method Of Entry,
if configured.
(write_cp14_reg): Reset count counter if requested.
* armdefs.h (struct ARMul_State): New members `LastTime' and
`CP14R0_CCD' used for the timer/counters.
(ARMul_CP13_R0_FIQ, ARMul_CP13_R0_IRQ, ARMul_CP13_R8_PMUS,
ARMul_CP14_R0_ENABLE, ARMul_CP14_R0_CLKRST, ARMul_CP14_R0_CCD,
ARMul_CP14_R0_INTEN0, ARMul_CP14_R0_INTEN1, ARMul_CP14_R0_INTEN2,
ARMul_CP14_R0_FLAG0, ARMul_CP14_R0_FLAG1, ARMul_CP14_R0_FLAG2,
ARMul_CP14_R10_MOE_IB, ARMul_CP14_R10_MOE_DB, ARMul_CP14_R10_MOE_BT,
ARMul_CP15_R1_ENDIAN, ARMul_CP15_R1_ALIGN, ARMul_CP15_R5_X,
ARMul_CP15_R5_ST_ALIGN, ARMul_CP15_R5_IMPRE, ARMul_CP15_R5_MMU_EXCPT,
ARMul_CP15_DBCON_M, ARMul_CP15_DBCON_E1, ARMul_CP15_DBCON_E0): New
defines for XScale registers.
(XScale_check_memacc, XScale_set_fsr_far, XScale_debug_moe): Prototype.
(ARMul_Emulate32, ARMul_Emulate26): Clean up function definition.
(ARMul_Emulate32): Handle the clock counter and hardware instruction
breakpoints. Call XScale_set_fsr_far() for software breakpoints and
software interrupts.
(LoadMult): Call XScale_set_fsr_far() for data aborts.
(LoadSMult): Likewise.
(StoreMult): Likewise.
(StoreSMult): Likewise.
* armemu.h (write_cp15_reg): Update prototype.
* arminit.c (ARMul_NewState): Initialise CP14R0_CCD and LastTime.
(ARMul_Abort): If XScale, check for FIQ and IRQ being enabled in CP13
register 0.
* armvirt.c (GetWord): Call XScale_check_memacc().
(PutWord): Likewise.
PENDING_FILL. Use PENDING_SCHED directly to handle the pending
set of the FCSR.
* sim-main.h (COCIDX): Remove definition; this isn't supported by
PENDING_FILL, and you can get the intended effect gracefully by
calling PENDING_SCHED directly.
2001-03-16 Frank Ch. Eigler <fche@redhat.com>
Add support for mmap-based memory regions.
* sim-memopt.c (mmap_next_fd): New global.
(sim_memory_init): Reinitialize it.
(OPTION_MEMORY_MAPFILE, memory_option_handler): Support new
"--memory-mapfile FILE" option. Check for some errors.
(do_memopt_add): Conditionally do mmap instead of malloc for
backing store of simulated memory. Check for more errors.
(do_simopt_delete, sim_memory_uninstall): Corresponding cleanup.
* sim-memopt.h (munmap_length): New member of _sim_memopt.
* configure.in: Look for mmap/fstat related functions and headers.
* config.in, configure: Regenerated.
2001-02-09 Ben Elliston <bje@redhat.com>
* (profile_print_pc): Write header out in target byte order.
2001-02-09 Ben Elliston <bje@redhat.com>
* sim-profile.c (profile_pc_init): Correct bug in loop logic when
adjusting the pc shift value.
later inspection by the trap handler.
(count_argc): New function.
(prog_argv): Declare static.
(sim_write): Declare.
(trap): Implement argc, argnlen and argn system calls. Do not
abort on unknown system calls--simply return -1.
* syscall.h (SYS_argc, SYS_argnlen, SYS_argn): Define.
[common/ChangeLog]
2001-01-12 Chris Demetriou <cgd@sibyte.com>
* aclocal.m4 (SIM_AC_OPTION_SCACHE): Properly
handle the case where a numeric value is supplied.
[eg. m32r/ChangeLog]
2001-01-12 Frank Ch. Eigler <fche@redhat.com>
* configure: Regenerated with sim_scache fix.
* sim-fpu.h (sim_fpu_printn_fpu): Declare.
* sim-fpu.c (print_bits): Add digits parameter. Print only as many
trailing digits as specified (-1 to print all digits).
(sim_fpu_print_fpu): New wrapper around sim_fpu_printn_fpu.
(sim_fpu_printn_fpu): Rename from sim_fpu_print_fpu; update calls
to print_bits ().
* sim-endian.h: Don't have parameters on macro definitions which
are simply renaming functions, to permit use of XCONCAT2 in both
the macro name and the arguments in a use of such a definition.
In sim/ppc:
* sim-endian.h: Don't have parameters on macro definitions which
are simply renaming functions, to permit use of XCONCAT2 in both
the macro name and the arguments in a use of such a definition.
