8sa1-binutils-gdb

Author	SHA1	Message	Date
Paul Brook	1fbaefec00	2011-04-07 Paul Carroll<pcarroll@codesourcery.com> opcodes/ * arm-dis.c (print_insn): init vars moved into private_data structure. binutils/testsuite/ * binutils-all/arm/simple.s: Demo issue with objdump with multiple input files * binutils-all/arm/objdump.exp: added new ARM test case code	2011-04-08 11:42:19 +00:00
Mike Frysinger	67171547aa	opcodes: blackfin: ignore (M) on MAC0-only dsp mac funcs If the MAC1 part of the insn is disabled, then the (M) flag is ignored. Rather than include it in the decode, move the MM clearing to the MAC0 portion of the code. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2011-03-24 05:27:39 +00:00
Eric B. Weddington	8cc66334fa	/bfd: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * archures.c: Add AVR XMEGA architecture information. * cpu-avr.c (arch_info_struct): Likewise. * elf32-avr.c (bfd_elf_avr_final_write_processing): Likewise. (elf32_avr_object_p): Likewise. /gas: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * config/tc-avr.c (struct avr_opcodes_s): Add opcode field. (AVR_INSN): Change definition to match. (avr_opcodes): Likewise, change to match. (mcu_types): Add XMEGA architecture names and new XMEGA device names. (md_show_usage): Add XMEGA architecture names. (avr_operand): Add 'E' constraint for DES instruction of XMEGA devices. Add support for SPM Z+ instruction. * doc/c-avr.texi: Add documentation for XMEGA architectures and devices. /include/opcode: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * avr.h (AVR_ISA_SPMX,AVR_ISA_DES,AVR_ISA_M256,AVR_ISA_XMEGA): New instruction set flags. (AVR_INSN): Add new instructions for SPM Z+, DES for XMEGA. /ld: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * Makefile.am (ALL_EMULATION_SOURCES): Add AVR XMEGA architectures. (eavrxmega?.c): Likewise. * configure.tgt (targ_extra_emuls): Likewise. * emulparams/avrxmega1.sh: New file. * emulparams/avrxmega2.sh: Likewise. * emulparams/avrxmega3.sh: Likewise. * emulparams/avrxmega4.sh: Likewise. * emulparams/avrxmega5.sh: Likewise. * emulparams/avrxmega6.sh: Likewise. * emulparams/avrxmega7.sh: Likewise. * emultempl/avrelf.em (avr_elf_${EMULATION_NAME}_before_allocation): Add avrxmega6, avrxmega7 to list of architectures for no stubs. /opcodes: 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> * avr-dis.c (avr_operand): Add opcode_str parameter. Check for post-increment to support LPM Z+ instruction. Add support for 'E' constraint for DES instruction. (print_insn_avr): Adjust calls to avr_operand. Rename variable.	2011-03-22 18:10:48 +00:00
Richard Sandiford	34e77a920a	include/elf/ * arm.h (R_ARM_IRELATIVE): New relocation. bfd/ * reloc.c (BFD_RELOC_ARM_IRELATIVE): New relocation. * bfd-in2.h: Regenerate. * elf32-arm.c (elf32_arm_howto_table_2): Rename existing definition to elf32_arm_howto_table_3 and replace with a single R_ARM_IRELATIVE entry. (elf32_arm_howto_from_type): Update accordingly. (elf32_arm_reloc_map): Map BFD_RELOC_ARM_IRELATIVE to R_ARM_IRELATIVE. (elf32_arm_reloc_name_lookup): Handle elf32_arm_howto_table_3. (arm_plt_info): New structure, split out from elf32_arm_link_hash_entry with an extra noncall_refcount field. (arm_local_iplt_info): New structure. (elf_arm_obj_tdata): Add local_iplt. (elf32_arm_local_iplt): New accessor macro. (elf32_arm_link_hash_entry): Replace plt_thumb_refcount, plt_maybe_thumb_refcount and plt_got_offset with an arm_plt_info. Change tls_type to a bitfield and add is_iplt. (elf32_arm_link_hash_newfunc): Update accordingly. (elf32_arm_allocate_local_sym_info): New function. (elf32_arm_create_local_iplt): Likewise. (elf32_arm_get_plt_info): Likewise. (elf32_arm_plt_needs_thumb_stub_p): Likewise. (elf32_arm_get_local_dynreloc_list): Likewise. (create_ifunc_sections): Likewise. (elf32_arm_copy_indirect_symbol): Update after the changes to elf32_arm_link_hash_entry. Assert the is_iplt has not yet been set. (arm_type_of_stub): Add an st_type argument. Use elf32_arm_get_plt_info to get PLT information. Assert that all STT_GNU_IFUNC references are turned into PLT references. (arm_build_one_stub): Pass the symbol type to elf32_arm_final_link_relocate. (elf32_arm_size_stubs): Pass the symbol type to arm_type_of_stub. (elf32_arm_allocate_irelocs): New function. (elf32_arm_add_dynreloc): In static objects, use .rel.iplt for all R_ARM_IRELATIVE. (elf32_arm_allocate_plt_entry): New function. (elf32_arm_populate_plt_entry): Likewise. (elf32_arm_final_link_relocate): Add an st_type parameter. Set srelgot to null for static objects. Use separate variables to record which st_value and st_type should be used when generating a dynamic relocation. Use elf32_arm_get_plt_info to find the symbol's PLT information, setting has_iplt_entry, splt, plt_offset and gotplt_offset accordingly. Check whether STT_GNU_IFUNC symbols should resolve to an .iplt entry, and change the relocation target accordingly. Broaden assert to include .iplts. Don't set sreloc for static relocations. Assert that we only generate dynamic R_ARM_RELATIVE relocations for R_ARM_ABS32 and R_ARM_ABS32_NOI. Generate R_ARM_IRELATIVE relocations instead of R_ARM_RELATIVE relocations if the target is an STT_GNU_IFUNC symbol. Pass the symbol type to arm_type_of_stub. Conditionally resolve GOT references to the .igot.plt entry. (elf32_arm_relocate_section): Update the call to elf32_arm_final_link_relocate. (elf32_arm_gc_sweep_hook): Use elf32_arm_get_plt_info to get PLT information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call relocations in shared libraries and relocatable executables. Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list to get the list of dynamic relocations for a local symbol. (elf32_arm_check_relocs): Always create ifunc sections. Set isym at the same time as setting h. Use elf32_arm_allocate_local_sym_info to allocate local symbol information. Treat R_ARM_REL32 and R_ARM_REL32_NOI as call relocations in shared libraries and relocatable executables. Record PLT information for local STT_GNU_IFUNC functions as well as global functions. Count non-call PLT references. Use elf32_arm_get_local_dynreloc_list to get the list of dynamic relocations for a local symbol. (elf32_arm_adjust_dynamic_symbol): Handle STT_GNU_IFUNC symbols. Don't remove STT_GNU_IFUNC PLTs unless all references have been removed. Update after the changes to elf32_arm_link_hash_entry. (allocate_dynrelocs_for_symbol): Decide whether STT_GNU_IFUNC PLT entries should live in .plt or .iplt. Check whether the .igot.plt and .got entries can be combined. Use elf32_arm_allocate_plt_entry to allocate .plt and .(i)got.plt entries. Detect which .got entries will need R_ARM_IRELATIVE relocations and use elf32_arm_allocate_irelocs to allocate them. Likewise other non-.got dynamic relocations. (elf32_arm_size_dynamic_sections): Allocate .iplt, .igot.plt and dynamic relocations for local STT_GNU_IFUNC symbols. Check whether the .igot.plt and .got entries can be combined. Detect which .got entries will need R_ARM_IRELATIVE relocations and use elf32_arm_allocate_irelocs to allocate them. Use stashed section pointers intead of strcmp checks. Handle iplt and igotplt. (elf32_arm_finish_dynamic_symbol): Use elf32_arm_populate_plt_entry to fill in .plt, .got.plt and .rel(a).plt entries. Point STT_GNU_IFUNC symbols at an .iplt entry if non-call relocations resolve to it. (elf32_arm_output_plt_map_1): New function, split out from elf32_arm_output_plt_map. Handle .iplt entries. Use elf32_arm_plt_needs_thumb_stub_p. (elf32_arm_output_plt_map): Call it. (elf32_arm_output_arch_local_syms): Add mapping symbols for local .iplt entries. (elf32_arm_swap_symbol_in): Handle Thumb STT_GNU_IFUNC symbols. (elf32_arm_swap_symbol_out): Likewise. (elf32_arm_add_symbol_hook): New function. (elf_backend_add_symbol_hook): Define for all targets. opcodes/ * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code. gas/ * config/tc-arm.c (md_pcrel_from_section): Use S_FORCE_RELOC to determine whether a relocation is needed. (md_apply_fix, arm_apply_sym_value): Likewise. ld/testsuite/ * ld-arm/ifunc-1.s, ld-arm/ifunc-1.dd, ld-arm/ifunc-1.gd, ld-arm/ifunc-1.rd, ld-arm/ifunc-2.s, ld-arm/ifunc-2.dd, ld-arm/ifunc-2.gd, ld-arm/ifunc-2.rd, ld-arm/ifunc-3.s, ld-arm/ifunc-3.dd, ld-arm/ifunc-3.gd, ld-arm/ifunc-3.rd, ld-arm/ifunc-4.s, ld-arm/ifunc-4.dd, ld-arm/ifunc-4.gd, ld-arm/ifunc-4.rd, ld-arm/ifunc-5.s, ld-arm/ifunc-5.dd, ld-arm/ifunc-5.gd, ld-arm/ifunc-5.rd, ld-arm/ifunc-6.s, ld-arm/ifunc-6.dd, ld-arm/ifunc-6.gd, ld-arm/ifunc-6.rd, ld-arm/ifunc-7.s, ld-arm/ifunc-7.dd, ld-arm/ifunc-7.gd, ld-arm/ifunc-7.rd, ld-arm/ifunc-8.s, ld-arm/ifunc-8.dd, ld-arm/ifunc-8.gd, ld-arm/ifunc-8.rd, ld-arm/ifunc-9.s, ld-arm/ifunc-9.dd, ld-arm/ifunc-9.gd, ld-arm/ifunc-9.rd, ld-arm/ifunc-10.s, ld-arm/ifunc-10.dd, ld-arm/ifunc-10.gd, ld-arm/ifunc-10.rd, ld-arm/ifunc-11.s, ld-arm/ifunc-11.dd, ld-arm/ifunc-11.gd, ld-arm/ifunc-11.rd, ld-arm/ifunc-12.s, ld-arm/ifunc-12.dd, ld-arm/ifunc-12.gd, ld-arm/ifunc-12.rd, ld-arm/ifunc-13.s, ld-arm/ifunc-13.dd, ld-arm/ifunc-13.gd, ld-arm/ifunc-13.rd, ld-arm/ifunc-14.s, ld-arm/ifunc-14.dd, ld-arm/ifunc-14.gd, ld-arm/ifunc-14.rd, ld-arm/ifunc-15.s, ld-arm/ifunc-15.dd, ld-arm/ifunc-15.gd, ld-arm/ifunc-15.rd, ld-arm/ifunc-16.s, ld-arm/ifunc-16.dd, ld-arm/ifunc-16.gd, ld-arm/ifunc-16.rd, ld-arm/ifunc-dynamic.ld, ld-arm/ifunc-static.ld: New tests. * ld-arm/farcall-group.d, ld-arm/farcall-group-size2.d, ld-arm/farcall-mixed-lib-v4t.d, ld-arm/farcall-mixed-lib.d: Update for new stub hashes. * ld-arm/arm-elf.exp: Run them.	2011-03-14 16:04:16 +00:00
Richard Sandiford	35fc36a8d6	include/elf/ * internal.h (elf_internal_sym): Add st_target_internal. * arm.h (arm_st_branch_type): New enum. (ARM_SYM_BRANCH_TYPE): New macro. bfd/ * elf-bfd.h (elf_link_hash_entry): Add target_internal. * elf.c (swap_out_syms): Set st_target_internal for each Elf_Internal_Sym. * elfcode.h (elf_swap_symbol_in): Likewise. * elf32-i370.c (i370_elf_finish_dynamic_sections): Likewise. * elf32-sh-symbian.c (sh_symbian_relocate_section): Likewise. * elf64-sparc.c (elf64_sparc_output_arch_syms): Likewise. * elfxx-sparc.c (_bfd_sparc_elf_size_dynamic_sections): Likewise. * elflink.c (elf_link_output_extsym): Likewise. (bfd_elf_final_link): Likewise. (elf_link_add_object_symbols): Copy st_target_internal to the hash table if we see a definition. (_bfd_elf_copy_link_hash_symbol_type): Copy target_internal. * elf32-arm.c (elf32_arm_stub_hash_entry): Replace st_type with a branch_type field. (a8_erratum_fix, a8_erratum_reloc): Likewise. (arm_type_of_stub): Replace actual_st_type with an actual_branch_type parameter. (arm_build_one_stub): Use branch types rather than st_types to determine the type of branch. (cortex_a8_erratum_scan): Likewise. (elf32_arm_size_stubs): Likewise. (bfd_elf32_arm_process_before_allocation): Likewise. (allocate_dynrelocs_for_symbol): Likewise. (elf32_arm_finish_dynamic_sections): Likewise. (elf32_arm_final_link_relocate): Replace sym_flags parameter with a branch_type parameter. (elf32_arm_relocate_section): Update call accordingly. (elf32_arm_adjust_dynamic_symbol): Don't check STT_ARM_TFUNC. (elf32_arm_output_map_sym): Initialize st_target_internal. (elf32_arm_output_stub_sym): Likewise. (elf32_arm_symbol_processing): Delete. (elf32_arm_swap_symbol_in): Convert STT_ARM_TFUNCs into STT_FUNCs. Use st_target_internal to record the branch type. (elf32_arm_swap_symbol_out): Use st_target_internal to test for Thumb functions. (elf32_arm_is_function_type): Delete. (elf_backend_symbol_processing): Likewise. (elf_backend_is_function_type): Likewise. gas/ * config/tc-arm.c (arm_adjust_symtab): Set the branch type for Thumb symbols. ld/ * emultempl/armelf.em (gld${EMULATION_NAME}_finish): Check eh->target_internal. opcodes/ * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC. Use branch types instead. (print_insn): Likewise.	2011-03-14 15:55:04 +00:00
Maciej W. Rozycki	0067d8fc73	opcodes/ * mips-opc.c (mips_builtin_opcodes): Correct register use annotation of "alnv.ps". gas/testsuite/ * gas/mips/alnv_ps-swap.d: New test for ALNV.PS instruction branch swapping. * gas/mips/alnv_ps-swap.s: Source for the new test. * gas/mips/mips.exp: Run the new test.	2011-02-28 16:34:39 +00:00
Maciej W. Rozycki	3eebd5eb03	gas/ * config/tc-mips.c (macro): Handle M_PREF_AB. include/opcode/ * mips.h (M_PREF_AB): New enum value. opcodes/ * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.	2011-02-28 16:06:51 +00:00
Maciej W. Rozycki	89c0d58cff	Swap ChangeLog entries.	2011-02-28 16:03:38 +00:00
Mike Frysinger	500cccad3b	opcodes: blackfin: drop null/nul checks in OUTS Parts of the disassembler rely on the disasm info never being NULL (such as being able to read memory to disassemble in the first place). So drop useless null checks in the OUTS helper. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2011-02-22 20:52:31 +00:00
Mike Frysinger	f5caf9f434	opcodes: blackfin: use OUTS helper We have an OUTS helper to handle outf fprintf_func logic, so conver the few places not using it over. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2011-02-22 20:51:42 +00:00
Mike Frysinger	e5bc42655d	opcodes: blackfin: clean up saved_state Mark the state static, punt unused members, unify indexable register lookups, and abort when there is a register lookup failure. Otherwise we return NULL and the calling code assumes a valid pointer is returned. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2011-02-20 01:26:14 +00:00
Mike Frysinger	602427c4af	opcodes: blackfin: fix style Non-functional thrashing to the GNU style. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2011-02-14 17:12:05 +00:00
Mike Frysinger	298c1ec2a0	opcodes: blackfin: catch invalid loopsetup insns The LoopSetup insn is only valid when the reg field is 0-7, so don't go decoding it incorrectly when reg is 8-15. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2011-02-14 05:21:04 +00:00
Ralf Wildenhues	822ce8ee21	Remove freebsd1 from libtool.m4 macros and config.rpath. /: Import from Libtool and gnulib: 2011-01-27 Gerald Pfeifer <gerald@pfeifer.com> Prepare for supporting FreeBSD 10. * config.rpath: Remove handling of freebsd1* which soon would match FreeBSD 10.0. 2011-01-20 Gerald Pfeifer <gerald@pfeifer.com> (tiny change) Remove support for FreeBSD 1.x. * libtool.m4 (_LT_LINKER_SHLIBS) (_LT_SYS_DYNAMIC_LINKER): Remove handling of freebsd1* which soon would incorrectly match FreeBSD 10.0. bfd/: * configure: Regenerate. gas/: * configure: Regenerate. ld/: * configure: Regenerate. opcodes/: * configure: Regenerate. binutils/: * configure: Regenerate. gprof/: * configure: Regenerate.	2011-02-13 21:00:14 +00:00
Mike Frysinger	13c02f06ff	opcodes: blackfin: fix decoding of ABS The single cycle dual mac ABS insn was incorrectly decoding the mac1 part of the insn. Once we fix the decode, update the gas tests to have the correct output. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2011-02-13 18:55:22 +00:00
Mike Frysinger	4db6639409	opcodes: blackfin: fix decoding of dsp mult insns When assigning to a register half, the mac0 part of the mult insn was not decoding properly. It would always show a full dreg instead of the dreg low half. Once we fix the disassembler, we have to update a few of the gas tests as their previous expected output was incorrect. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2011-02-13 18:54:49 +00:00
Mike Frysinger	36f446111a	gas/opcodes: blackfin: punt BYTEOP2M insn support The BYTEOP2M insn was part of the initial Blackfin designs, but never made it into any actual silicon. So punt support for it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2011-02-13 18:53:16 +00:00
Mike Frysinger	9805c0a5b6	opcodes: blackfin: add missing space after PRNT insn Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2011-02-12 19:38:11 +00:00
Mike Frysinger	43a6aa65fe	opcodes: blackfin: drop "GP" register There never was a "GP" register, so punt it from the decode map. It's a hold over from a very old processor definition and never made it into actual silicon. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2011-02-12 19:37:32 +00:00
Mike Frysinger	26bb3ddd50	gas/opcodes: blackfin: move dsp mac func defines to common header The mmod field is decoded in a few places (gas/opcodes/sim), so move it to a common place to avoid duplication. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2011-02-12 19:36:31 +00:00
Mike Frysinger	69b8ea4abd	opcodes: blackfin: constify register names Constify the array itself since it need not be writable. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2011-02-11 19:03:27 +00:00
Michael Snyder	42d5f9c6ef	2011-02-09 Michael Snyder <msnyder@vmware.com> * i386-dis.c (OP_J): Parenthesize expression to prevent truncated addresses. (print_insn): Fix indentation off-by-one.	2011-02-09 18:43:41 +00:00
Nick Clifton	4be0c94123	Updated Danish translation.	2011-02-01 13:14:40 +00:00
Alan Modra	6b069ee70d	* ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.	2011-01-21 00:53:11 +00:00
H.J. Lu	e3949f17f3	Properly sign-extend byte. gas/testsuite/ 2011-01-18 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/intel.d: Updated. * gas/i386/opcode-intel.d: Likewise. * gas/i386/opcode-suffix.d: Likewise. * gas/i386/opcode.d: Likewise. opcodes/ 2011-01-18 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (sIbT): New. (b_T_mode): Likewise. (dis386): Replace sIb with sIbT on "pushT". (x86_64_table): Replace sIb with Ib on "aam" and "aad". (OP_sI): Handle b_T_mode. Properly sign-extend byte.	2011-01-18 17:08:13 +00:00
Jan Kratochvil	752573b292	opcodes/ * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.	2011-01-18 14:14:46 +00:00
Quentin Neill	2a2a0f38e7	Add support for TBM instructions. gas/ 2011-01-17 Quentin Neill <quentin.neill@amd.com> * config/tc-i386.c (cpu_arch): Add CPU_TBM_FLAGS. * doc/c-i386.texi (i386-TBM): New section. opcodes/ 2011-01-17 Quentin Neill <quentin.neill@amd.com> * i386-dis.c (REG_XOP_TBM_01): New. (REG_XOP_TBM_02): New. (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables. (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02 entries, and add bextr instruction. * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM. (cpu_flags): Add CpuTBM. * i386-opc.h (CpuTBM) New. (i386_cpu_flags): Add bit cputbm. * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk, blcs, blsfill, blsic, t1mskc, and tzmsk. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated gas/testsuite 2011-01-17 Quentin Neill <quentin.neill@amd.com> * gas/i386/tbm.s: New. * gas/i386/tbm.d: New. * gas/i386/tbm-intel.d: New. * gas/i386/x86-64-tbm.s: New. * gas/i386/x86-64-tbm.d: New. * gas/i386/x86-64-tbm-intel.d: New. * gas/i386/arch-10.d: Add tbm flag and TBM instruction pattern. * gas/i386/arch-10.s: Add a TBM instruction. * gas/i386/arch-10-1.l: Add TBM instruction pattern. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/x86-64-arch-2.d: Likewise.	2011-01-17 18:40:36 +00:00
DJ Delorie	90d6ff629e	* rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.	2011-01-12 07:06:29 +00:00
Mingjie Xing	c95354ed13	Take unadjusted offset for loongson3a specific instructions.	2011-01-11 07:22:09 +00:00
Nick Clifton	f74656046a	* po/da.po: Updated Danish translation.	2011-01-10 13:51:10 +00:00
Nathan Sidwell	639e30d297	gas/testsuite/ * gas/arm/blx-bad.s: New. * gas/arm/blx-bad.d: New. opcodes/ * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.	2011-01-06 14:30:43 +00:00
H.J. Lu	f12dc42220	Implement BMI instructions.	2011-01-05 00:16:57 +00:00
H.J. Lu	cb21baef77	Add VexGdq. 2011-01-04 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (VexGdq): New. (OP_VEX): Handle dq_mode.	2011-01-04 20:53:32 +00:00
H.J. Lu	4fb3aee212	Update copyright in comments to 2011.	2011-01-01 21:42:17 +00:00
H.J. Lu	0db46eb403	Update copyright to 2011. binutils/ 2011-01-01 H.J. Lu <hongjiu.lu@intel.com> * version.c (print_version): Update copyright to 2011. gas/ 2011-01-01 H.J. Lu <hongjiu.lu@intel.com> * gas.c (parse_args): Update copyright to 2011. gold/ 2011-01-01 H.J. Lu <hongjiu.lu@intel.com> * version.cc (print_version): Update copyright to 2011. ld/ 2011-01-01 H.J. Lu <hongjiu.lu@intel.com> * ldver.c (ldversion): Update copyright to 2011. opcodes/ 2011-01-01 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (process_copyright): Update copyright to 2011.	2011-01-01 20:55:48 +00:00
H.J. Lu	9e9e082043	Rotate binutils ChangeLogs.	2011-01-01 16:43:53 +00:00
Dave Anglin	3c853d9313	PR gas/11395 * config/tc-hppa.c (pa_ip): Revert last change. Add variable need_cond to determine whether a 64-bit condition is needed for 'A' and 'S' conditions. Default to 32-bit never condition for logical and unit instructions. Add error message for missing branch on bit condition. * hppa.h (pa_opcodes): Revert last change. Exchange 32 and 64-bit "bb" entries. * hppa-dis.c (compare_cond_64_names): Change never condition to ",*". (add_cond_64_names): Likewise. (logical_cond_64_names): Likewise. (unit_cond_64_names): Likewise.	2010-12-31 16:43:46 +00:00
H.J. Lu	351f65ca26	Add x86-64 ILP32 support. bfd/ 2010-12-30 H.J. Lu <hongjiu.lu@intel.com> * archures.c (bfd_mach_x64_32): New. (bfd_mach_x64_32_intel_syntax): Likewise. * bfd-in2.h: Regenerated. * config.bfd (targ64_selvecs): Add bfd_elf32_x86_64_vec for i[3-7]86--linux-. (targ_selvecs): Add bfd_elf32_x86_64_vec for x86_64--linux-. * configure.in: Support bfd_elf32_x86_64_vec. * configure: Regenerated. * cpu-i386.c (bfd_x64_32_arch_intel_syntax): New. (bfd_x64_32_arch): Likewise. * elf-bfd.h (elf_append_rela): New prototype. (elf_append_rel): Likewise. (elf64_r_info): Likewise. (elf32_r_info): Likewise. (elf64_r_sym): Likewise. (elf32_r_sym): Likewise. * elf64-x86-64.c (ABI_64_P): New. (elf_x86_64_info_to_howto): Replace ELF64_R_TYPE with ELF32_R_TYPE. Replace ELF64_ST_TYPE with ELF_ST_TYPE. (elf_x86_64_check_tls_transition):Likewise. (elf_x86_64_check_relocs): Likewise. (elf_x86_64_gc_mark_hook):Likewise. (elf_x86_64_gc_sweep_hook): Likewise. (elf_x86_64_relocate_section): Likewise. (elf_x86_64_reloc_type_class): Likewise. (ELF_DYNAMIC_INTERPRETER): Renamed to ... (ELF64_DYNAMIC_INTERPRETER): This. (ELF32_DYNAMIC_INTERPRETER): New. (elf_x86_64_link_hash_table): Add r_info, r_sym, swap_reloca_out, dynamic_interpreter and dynamic_interpreter_size. (elf_x86_64_get_local_sym_hash): Replace ELF64_R_SYM with htab->r_sym. Replace ELF64_R_INFO with htab->r_info. (elf_x86_64_get_local_sym_hash): Likewise. (elf_x86_64_check_tls_transition):Likewise. (elf_x86_64_check_relocs): Likewise. (elf_x86_64_gc_mark_hook):Likewise. (elf_x86_64_gc_sweep_hook): Likewise. (elf_x86_64_relocate_section): Likewise. (elf_x86_64_finish_dynamic_symbol): Likewise. (elf_x86_64_finish_local_dynamic_symbol): Likewise. (elf_x86_64_link_hash_table_create): Initialize r_info, r_sym, swap_reloca_out, dynamic_interpreter and dynamic_interpreter_size. (elf_x86_64_check_relocs): Check ABI_64_P when requesting for PIC. (elf_x86_64_relocate_section): Likewise. (elf64_x86_64_adjust_dynamic_symbol): Replace sizeof (Elf64_External_Rela) with bed->s->sizeof_rela. (elf64_x86_64_allocate_dynrelocs): Likewise. (elf64_x86_64_size_dynamic_sections): Likewise. (elf64_x86_64_finish_dynamic_symbol): Likewise. (elf64_x86_64_append_rela): Removed. (elf32_x86_64_elf_object_p): New. Add bfd_elf32_x86_64_vec. * elf64-x86-64.c (elf64_x86_64_xxx): Renamed to ... (elf_x86_64_xxx): This. * elflink.c (bfd_elf_final_link): Check ELF file class on error. (elf_append_rela): New. (elf_append_rel): Likewise. (elf64_r_info): Likewise. (elf32_r_info): Likewise. (elf64_r_sym): Likewise. (elf32_r_sym): Likewise. * targets.c (bfd_elf32_x86_64_vec): New. (_bfd_target_vector): Add bfd_elf32_x86_64_vec. gas/ 2010-12-30 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (x86_elf_abi): New. (i386_mach): Return bfd_mach_x64_32 for ILP32. (OPTION_N32): Likewise. (md_longopts): Add "n32" for ELF. (md_parse_option): Handle OPTION_N32. (md_show_usage): Add --n32. (i386_target_format): Update and check x86_elf_abi. * config/tc-i386.h (ELF_TARGET_FORMAT32): New. * doc/as.texinfo: Document --n32. * doc/c-i386.texi: Likewise. gas/testsuite/ 2010-12-30 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/ilp32/lns/ilp32.exp: New. * gas/i386/ilp32/lns/lns-common-1.d: Likewise. * gas/i386/ilp32/lns/lns-duplicate.d: Likewise. * gas/i386/ilp32/cfi/cfi-common-1.d: New. * gas/i386/ilp32/cfi/cfi-common-2.d: Likewise. * gas/i386/ilp32/cfi/cfi-common-3.d: Likewise. * gas/i386/ilp32/cfi/cfi-common-4.d: Likewise. * gas/i386/ilp32/cfi/cfi-common-5.d: Likewise. * gas/i386/ilp32/cfi/cfi-common-6.d: Likewise. * gas/i386/ilp32/cfi/cfi-common-7.d: Likewise. * gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise. * gas/i386/ilp32/cfi/ilp32.exp: Likewise. * gas/i386/ilp32/elf/ehopt0.d: Likewise. * gas/i386/ilp32/elf/equ-reloc.d: Likewise. * gas/i386/ilp32/elf/file.d: Likewise. * gas/i386/ilp32/elf/group0a.d: Likewise. * gas/i386/ilp32/elf/group0b.d: Likewise. * gas/i386/ilp32/elf/group1a.d: Likewise. * gas/i386/ilp32/elf/group1b.d: Likewise. * gas/i386/ilp32/elf/ifunc-1.d: Likewise. * gas/i386/ilp32/elf/ilp32.exp: Likewise. * gas/i386/ilp32/elf/redef.d: Likewise. * gas/i386/ilp32/elf/section0.d: Likewise. * gas/i386/ilp32/elf/section1.d: Likewise. * gas/i386/ilp32/elf/section3.d: Likewise. * gas/i386/ilp32/elf/section4.d: Likewise. * gas/i386/ilp32/elf/section6.d: Likewise. * gas/i386/ilp32/elf/section7.d: Likewise. * gas/i386/ilp32/elf/struct.d: Likewise. * gas/i386/ilp32/elf/symtab.d: Likewise. * gas/i386/ilp32/elf/symver.d: Likewise. * gas/i386/ilp32/ilp32.exp: New. * gas/i386/ilp32/immed64.d: Likewise. * gas/i386/ilp32/mixed-mode-reloc64.d: Likewise. * gas/i386/ilp32/reloc64.d: Likewise. * gas/i386/ilp32/rex.d: Likewise. * gas/i386/ilp32/rexw.d: Likewise. * gas/i386/ilp32/svme64.d: Likewise. * gas/i386/ilp32/x86-64-addr32.d: Likewise. * gas/i386/ilp32/x86-64-addr32-intel.d: Likewise. * gas/i386/ilp32/x86-64-aes.d: Likewise. * gas/i386/ilp32/x86-64-aes-intel.d: Likewise. * gas/i386/ilp32/x86-64-amdfam10.d: Likewise. * gas/i386/ilp32/x86-64-arch-1.d: Likewise. * gas/i386/ilp32/x86-64-arch-2.d: Likewise. * gas/i386/ilp32/x86-64-avx.d: Likewise. * gas/i386/ilp32/x86-64-avx-intel.d: Likewise. * gas/i386/ilp32/x86-64-avx-swap.d: Likewise. * gas/i386/ilp32/x86-64-avx-swap-intel.d: Likewise. * gas/i386/ilp32/x86-64-branch.d: Likewise. * gas/i386/ilp32/x86-64-cbw.d: Likewise. * gas/i386/ilp32/x86-64-cbw-intel.d: Likewise. * gas/i386/ilp32/x86-64-clmul.d: Likewise. * gas/i386/ilp32/x86-64-clmul-intel.d: Likewise. * gas/i386/ilp32/x86-64-crc32.d: Likewise. * gas/i386/ilp32/x86-64-crc32-intel.d: Likewise. * gas/i386/ilp32/x86-64-crx.d: Likewise. * gas/i386/ilp32/x86-64-crx-suffix.d: Likewise. * gas/i386/ilp32/x86-64.d: Likewise. * gas/i386/ilp32/x86-64-disp.d: Likewise. * gas/i386/ilp32/x86-64-disp-intel.d: Likewise. * gas/i386/ilp32/x86-64-drx.d: Likewise. * gas/i386/ilp32/x86-64-drx-suffix.d: Likewise. * gas/i386/ilp32/x86-64-ept.d: Likewise. * gas/i386/ilp32/x86-64-ept-intel.d: Likewise. * gas/i386/ilp32/x86-64-fma4.d: Likewise. * gas/i386/ilp32/x86-64-fma.d: Likewise. * gas/i386/ilp32/x86-64-fma-intel.d: Likewise. * gas/i386/ilp32/x86-64-gidt.d: Likewise. * gas/i386/ilp32/x86-64-ifunc.d: Likewise. * gas/i386/ilp32/x86-64-intel64.d: Likewise. * gas/i386/ilp32/x86-64-io.d: Likewise. * gas/i386/ilp32/x86-64-io-intel.d: Likewise. * gas/i386/ilp32/x86-64-io-suffix.d: Likewise. * gas/i386/ilp32/x86-64-localpic.d: Likewise. * gas/i386/ilp32/x86-64-mem.d: Likewise. * gas/i386/ilp32/x86-64-mem-intel.d: Likewise. * gas/i386/ilp32/x86-64-movbe.d: Likewise. * gas/i386/ilp32/x86-64-movbe-intel.d: Likewise. * gas/i386/ilp32/x86-64-nops-1-core2.d: Likewise. * gas/i386/ilp32/x86-64-nops-1.d: Likewise. * gas/i386/ilp32/x86-64-nops-1-k8.d: Likewise. * gas/i386/ilp32/x86-64-nops-1-nocona.d: Likewise. * gas/i386/ilp32/x86-64-nops-1-pentium.d: Likewise. * gas/i386/ilp32/x86-64-nops-2.d: Likewise. * gas/i386/ilp32/x86-64-nops-3.d: Likewise. * gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise. * gas/i386/ilp32/x86-64-nops-4.d: Likewise. * gas/i386/ilp32/x86-64-nops-4-k8.d: Likewise. * gas/i386/ilp32/x86-64-nops-5.d: Likewise. * gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise. * gas/i386/ilp32/x86-64-nops.d: Likewise. * gas/i386/ilp32/x86-64-opcode.d: Likewise. * gas/i386/ilp32/x86-64-opcode-inval.d: Likewise. * gas/i386/ilp32/x86-64-opcode-inval-intel.d: Likewise. * gas/i386/ilp32/x86-64-opts.d: Likewise. * gas/i386/ilp32/x86-64-opts-intel.d: Likewise. * gas/i386/ilp32/x86-64-pcrel.d: Likewise. * gas/i386/ilp32/x86-64-reg.d: Likewise. * gas/i386/ilp32/x86-64-reg-intel.d: Likewise. * gas/i386/ilp32/x86-64-rep.d: Likewise. * gas/i386/ilp32/x86-64-rep-suffix.d: Likewise. * gas/i386/ilp32/x86-64-rip.d: Likewise. * gas/i386/ilp32/x86-64-rip-intel.d: Likewise. * gas/i386/ilp32/x86-64-sib.d: Likewise. * gas/i386/ilp32/x86-64-sib-intel.d: Likewise. * gas/i386/ilp32/x86-64-simd.d: Likewise. * gas/i386/ilp32/x86-64-simd-intel.d: Likewise. * gas/i386/ilp32/x86-64-simd-suffix.d: Likewise. * gas/i386/ilp32/x86-64-sse2avx.d: Likewise. * gas/i386/ilp32/x86-64-sse2avx-opts.d: Likewise. * gas/i386/ilp32/x86-64-sse2avx-opts-intel.d: Likewise. * gas/i386/ilp32/x86-64-sse3.d: Likewise. * gas/i386/ilp32/x86-64-sse4_1.d: Likewise. * gas/i386/ilp32/x86-64-sse4_1-intel.d: Likewise. * gas/i386/ilp32/x86-64-sse4_2.d: Likewise. * gas/i386/ilp32/x86-64-sse4_2-intel.d: Likewise. * gas/i386/ilp32/x86-64-sse-check.d: Likewise. * gas/i386/ilp32/x86-64-sse-check-none.d: Likewise. * gas/i386/ilp32/x86-64-sse-check-warn.d: Likewise. * gas/i386/ilp32/x86-64-sse-noavx.d: Likewise. * gas/i386/ilp32/x86-64-ssse3.d: Likewise. * gas/i386/ilp32/x86-64-stack.d: Likewise. * gas/i386/ilp32/x86-64-stack-intel.d: Likewise. * gas/i386/ilp32/x86-64-stack-suffix.d: Likewise. * gas/i386/ilp32/x86-64-unwind.d: Likewise. * gas/i386/ilp32/x86-64-vmx.d: Likewise. * gas/i386/ilp32/x86-64-xsave.d: Likewise. * gas/i386/ilp32/x86-64-xsave-intel.d: Likewise. ld/ 2010-12-30 H.J. Lu <hongjiu.lu@intel.com> * emulparams/elf32_x86_64.sh: New. * configure.tgt (targ64_extra_emuls): Add elf32_x86_64 for i[3-7]86--linux-. (targ_extra_libpath): Likewise. (targ_extra_emuls): Add elf32_x86_64 for x86_64--linux-. (targ_extra_libpath): Likewise. * Makefile.am (ALL_64_EMULATION_SOURCES): Add eelf32_x86_64.c. (eelf32_x86_64.c): New. * Makefile.in: Regenerated. opcodes/ 2010-12-30 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (print_insn): Support bfd_mach_x64_32 and bfd_mach_x64_32_intel_syntax.	2010-12-31 00:33:36 +00:00
Richard Sandiford	9867540240	include/opcode/ 2010-12-14 Mingjie Xing <mingjie.xing@gmail.com> * mips.h (OP__OFFSET_A, OP__OFFSET_B, OP__OFFSET_C) (OP__RZ, OP__FZ, INSN2_M_FP_D, INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z) (INSN2_READ_GPR_Z, INSN2_READ_FPR_Z, INSN2_READ_GPR_D): Define. opcodes/ 2010-12-14 Mingjie Xing <mingjie.xing@gmail.com> mips-opc.c (WR_z, WR_Z, RD_z, RD_Z, RD_d): Define. (mips_builtin_opcodes): Add loongson3a specific instructions. * mips-dis.c (print_insn_args): Handle the new arguments +a\|b\|c\|z\|Z. gas/ 2010-12-14 Mingjie Xing <mingjie.xing@gmail.com> * config/tc-mips.c (insn_uses_reg): Handle the new flags INSN2_READ_FPR_Z, INSN2_READ_GPR_D and INSN2_READ_GPR_Z. (append_insn): Handle delay-slot filling for the new flags. (validate_mips_insn): Handle the new arguments +a\|b\|c\|z\|Z. (mips_ip): Handle the new arguments +a\|b\|c\|z\|Z. gas/testsuite/ 2010-12-14 Mingjie Xing <mingjie.xing@gmail.com> * gas/mips/loongson-3a-2.s, gas/mips/loongson-3a-2.d, gas/mips/loongson-3a-3.s, gas/mips/loongson-3a-3.d: New tests. * gas/mips/mips.exp: Run them.	2010-12-18 11:14:14 +00:00
Richard Sandiford	a471ec3a5c	opcodes/ 2010-12-03 Mingming Sun <mingm.sun@gmail.com> * mips-opc.c: (mips_builtin_opcodes): Add loongson3a mul/div and fixed point instructions. gas/testsuite/ 2010-12-03 Mingming Sun <mingm.sun@gmail.com> * gas/mips/loongson-3a.s, gas/mips/loongson-3a.d: New test. * gas/mips/mips.exp: Run it.	2010-12-11 10:48:55 +00:00
Mike Frysinger	8b9a522f57	bfd/binutils/gas/gprof/ld/libiberty/opcodes: add .gitignore This seems to cover a few random targets as well as --enable-targets=all. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2010-12-09 09:03:18 +00:00
Alan Modra	1de34e0afe	Update translations	2010-11-25 06:08:52 +00:00
Nick Clifton	fd50354116	bfd/ * archures.c (bfd_mach_mips_loongson_3a): Defined. * bfd-in2.h (bfd_mach_mips_loongson_3a): Defined. * cpu-mips.c (I_loongson_3a): New add. (arch_info_struct): Add loongson_3a. * elfxx-mips.c (_bfd_elf_mips_mach): Add loongson_3a. (mips_set_isa_flags): Add loongson_3a. (mips_mach_extensions): Add loongson_3a in MIPS64 extensions. binutils/ * readelf.c (get_machine_flags): Add loongson-3a. gas/ * config/tc-mips.c (mips_cpu_info_table): Add loongson3a in MIPS 64. * doc/c-mips.texi (MIPS cpu): Add loongson3a. include/ * elf/mips.h (E_MIPS_MACH_LS3A): Defined. * opcode/mips.h (INSN_LOONGSON_3A): Defined. (CPU_LOONGSON_3A): Defined. (OPCODE_IS_MEMBER): Add LOONGSON_3A. opcodes/ * mips-dis.c (mips_arch_choices): Add loongson3a. * mips-opc.c (IL3A): Defined as INSN_LOONGSON_3A. (mips_builtin_opcodes): Modify some instructions' membership from IL2F to IL2F\|IL3A, since these instructions are supported by Loongson_3A.	2010-11-11 10:23:39 +00:00
Nick Clifton	8e295ce05a	Updated translations.	2010-11-10 14:39:10 +00:00
Tristan Gingold	2ee0aedfb8	bfd/ 2010-11-05 Tristan Gingold <gingold@adacore.com> * po/bfd.pot: Regenerate binutils/ 2010-11-05 Tristan Gingold <gingold@adacore.com> * po/binutils.pot: Regenerate gas/ 2010-11-05 Tristan Gingold <gingold@adacore.com> * po/gas.pot: Regenerate * po/POTFILES.in: Regenerate gprof/ 2010-11-05 Tristan Gingold <gingold@adacore.com> * po/gprof.pot: Regenerate ld/ 2010-11-05 Tristan Gingold <gingold@adacore.com> * po/ld.pot: Regenerate * po/POTFILES.in: Regenerate opcodes/ 2010-11-05 Tristan Gingold <gingold@adacore.com> * po/opcodes.pot: Regenerate	2010-11-05 10:25:11 +00:00
Maciej W. Rozycki	af47889861	* mips-opc.c (mips_builtin_opcodes): Fix formatting of "ld".	2010-10-28 13:49:51 +00:00
Andreas Krebbel	be7a250d1a	2010-10-28 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * config/tc-s390.c (md_begin): Only add to hash table if cpu and mode mask fit. 2010-10-28 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-opc.txt: cfxr, cfdr and cfer z900 -> g5.	2010-10-28 07:37:45 +00:00
Chao-ying Fu	d958d1a369	2010-10-25 Chao-ying Fu <fu@mips.com> * mips-opc.c (madd, maddu, msub, msubu, mult, multu): Change D33 to D32.	2010-10-25 18:09:10 +00:00
Nathan Sidwell	c0621d88b0	bfd/ * elf32-tic6x.c: Add attribution. gas/ * config/tc-tic6x.c: Add attribution. opcodes/ * tic6x-dis.c: Add attribution.	2010-10-25 15:33:54 +00:00
Alan Modra	a43817dfc9	* Makefile.am (CLEANFILES): Add stamp-lm32. Sort. * Makefile.in: Regenerate.	2010-10-21 23:50:57 +00:00
Maciej W. Rozycki	704897fbef	opcodes/ * mips-opc.c (mips_builtin_opcodes): Move M_LD_OB and M_SD_OB macros before their corresponding MIPS III hardware instructions. gas/ * config/tc-mips.c (macro)[M_LD_OB, M_SD_OB]: Handle 64-bit ABIs. gas/testsuite/ * gas/mips/lineno.s: Convert to o32. * gas/mips/lineno.d: Adjust patterns accordingly. Force the o32 ABI.	2010-10-18 00:15:35 +00:00
H.J. Lu	da98bb4c74	Add CpuNop to CPU_GENERIC64_FLAGS. gas/testsuite/ 2010-10-16 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run x86-64-nops-1-g64. * gas/i386/x86-64-nops-1.d: Remove -mtune=generic64. * gas/i386/x86-64-nops-1-g64.d: New. opcodes/ 2010-10-16 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Add CpuNop to CPU_GENERIC64_FLAGS. * i386-init.h: Regenerated.	2010-10-16 21:53:16 +00:00
Mike Frysinger	e1791cb8b5	gas: blackfin: fix encoding of BYTEOP2M insn The BYTEOP2M parser incorrectly calls BYTEOP2P to generate the opcode. Once we've fixed that, it's easy to see that the disassembler also likes to decode this insn incorrectly. So fix that and then add some tests. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2010-10-15 20:44:46 +00:00
H.J. Lu	553d0a7447	Remove CheckRegSize from movq. 2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Remove CheckRegSize from movq. * i386-tbl.h: Regenerated.	2010-10-14 23:16:19 +00:00
H.J. Lu	cfc08d490e	Remove CheckRegSize from instructions with 0, 1 or fixed operands. 2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Remove CheckRegSize from instructions with 0, 1 or fixed operands. * i386-tbl.h: Regenerated.	2010-10-14 21:37:30 +00:00
H.J. Lu	56ffb74112	Add CheckRegSize to instructions which require register size check. gas/ 2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (match_template): Check checkregsize instead of w for register size check. gas/testsuite/ 2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run inval-reg. * gas/i386/inval-reg.l: New. * gas/i386/inval-reg.s: Likewise. opcodes/ 2010-10-14 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Add CheckRegSize. * i386-opc.h (CheckRegSize): New. (i386_opcode_modifier): Add checkregsize. * i386-opc.tbl: Add CheckRegSize to instructions which require register size check. * i386-tbl.h: Regenerated.	2010-10-14 18:45:10 +00:00
Andreas Schwab	1a2dab1fbb	binutils/: * binutils-all/m68k/objdump.exp: Add fnop test. * binutils-all/m68k/fnop.s: New file. opcodes/: * m68k-opc.c (m68k_opcodes): Move fnop before fbf.	2010-10-11 22:18:42 +00:00
Andreas Krebbel	a3ec2691d0	2010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-opc.c: Make the instruction masks for the load/store on condition instructions to cover the condition code mask as well. * s390-opc.txt: lgoc -> locg and stgoc -> stocg. 2010-10-11 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/zarch-z196.d: Adjust the load/store on condition instructions. * gas/s390/zarch-z196.s: Likewise.	2010-10-11 11:56:53 +00:00
Jan Kratochvil	d92fa646e7	opcodes/ * Makefile.am (libopcodes_a_SOURCES): New as empty. * Makefile.in: Regenerate.	2010-10-11 06:10:35 +00:00
Alan Modra	4469d2be4b	cgen/ * utils-cgen.scm (gen-attr-accessors): Rename bool attribute to bool_. * cpu/mep.opc (mep_cgen_insn_supported): Ditto. include/opcode/ * cgen.h (CGEN_ATTR, CGEN_ATTR_TYPE): Rename bool attribute to bool_. (CGEN_ATTR_BOOLS, CGEN_ATTR_CGEN_INSN_ALIAS_VALUE): Likewise. opcodes/ * fr30-desc.h: Regenerate. * frv-desc.h: Regenerate. * ip2k-desc.h: Regenerate. * iq2000-desc.h: Regenerate. * lm32-desc.h: Regenerate. * m32c-desc.h: Regenerate. * m32r-desc.h: Regenerate. * mep-desc.h: Regenerate. * mep-opc.c: Regenerate. * mt-desc.h: Regenerate. * openrisc-desc.h: Regenerate. * xc16x-desc.h: Regenerate. * xstormy16-desc.h: Regenerate.	2010-10-09 06:50:23 +00:00
Alan Modra	9ccb8af972	Fix build with -DDEBUG=7	2010-10-08 14:00:50 +00:00
Bernd Schmidt	5d4c71e127	gas/ * config/tc-tic6x.c (tic6x_try_encode): Correct encoding of fstg field in SPKERNEL instructions. opcodes/ * tic6x-dis.c (print_insn_tic6x): Correct decoding of fstg field in SPKERNEL instructions. gas/testsuite/ * gas/tic6x/insns-c674x-sploop.d: Add two more sploop/spkernel tests. * gas/tic6x/insns-c674x-sploop.s: Likewise.	2010-10-07 11:28:49 +00:00
H.J. Lu	9ce00134f4	Remove duplicated RMAL. 2010-10-02 H.J. Lu <hongjiu.lu@intel.com> PR binutils/12076 * i386-dis.c (RMAL): Remove duplicate.	2010-10-02 07:04:07 +00:00
Pierre Muller	e7390eec2e	* s390-mkopc.c (main): Exit with error 1 if sscanf fails to parse all 6 parameters.	2010-09-30 16:02:35 +00:00
Pierre Muller	d2ae9c847a	* s390-mkopc.c (main): Change description array size to 80. Add maximum length of 79 to description parsing.	2010-09-30 11:32:15 +00:00
Ralf Wildenhues	3cac54d216	Fix unportable shell quoting. /: Sync from GCC: PR bootstrap/44621 * configure.ac: Fix unportable shell quoting. * configure: Regenerate. config/: * po.m4 (AM_PO_SUBDIRS): Fix unportable shell quoting. bfd/: * configure: Regenerate. gas/: * configure: Regenerate. gold/: * configure: Regenerate. intl/: * configure: Regenerate. ld/: * configure: Regenerate. opcodes/: * configure: Regenerate. binutils/: * configure: Regenerate. gprof/: * configure: Regenerate.	2010-09-27 20:23:01 +00:00
Andreas Krebbel	d9aee5d7f7	2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-mkopc.c (enum s390_opcde_cpu_val): Add S390_OPCODE_Z196. (main): Recognize the new CPU string. * s390-opc.c: Add new instruction formats and masks. * s390-opc.txt: Add new z196 instructions. 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * opcode/s390.h: Add S390_OPCODE_Z196 to enum s390_opcode_cpu_val. 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * config/tc-s390.c: (md_parse_option): New option -march=z196. * doc/c-s390.texi: Document new option. 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/s390.exp: Run the zarch-z196 test. * gas/s390/zarch-z196.d: Add new instructions. * gas/s390/zarch-z196.s: Likewise. * gas/s390/zarch-z9-109.d: Likewise. * gas/s390/zarch-z9-109.s: Likewise.	2010-09-27 13:36:48 +00:00
Andreas Krebbel	02cbf7671a	2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-dis.c (print_insn_s390): Pick instruction with most specific mask. * s390-opc.c: Add unused bits to the insn mask. * s390-opc.txt: Reorder some instructions to prefer more recent versions. 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/esa-g5.d: Adjust serveral instructions. * gas/s390/esa-reloc.d: Likewise. * gas/s390/esa-z990.d: Likewise. * gas/s390/zarch-reloc.d: Likewise. * gas/s390/zarch-z10.d: Likewise. * gas/s390/zarch-z9-ec.d: Likewise. * gas/s390/zarch-z900.d: Likewise. 2010-09-27 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * ld-s390/tlsbin.dd: bcr 0,%r7 -> nopr %r7. * ld-s390/tlsbin_64.dd: Likewise. * ld-s390/tlspic.dd: Likewise. * ld-s390/tlspic_64.dd: Likewise.	2010-09-27 13:33:00 +00:00
Matthew Gretton-Dann	6844b2c2db	2010-09-27 Tejas Belagod <tejas.belagod@arm.com> * gas/config/tc-arm.c (do_neon_ldr_str): Deprecate ARM-mode PC-relative VSTR, issue an error in THUMB mode. * opcodes/arm_dis.c (print_insn_coprocessor): Apply off-by-alignment correction to unaligned PCs while printing comment. * gas/testsuite/gas/arm/vldr.s: New test for pc-relative VLDR disassembly comment. * gas/testsuite/gas/arm/vldr.d: Likewise. * gas/testsuite/gas/arm/vstr-bad.s: New test for PC-relative VSTR. * gas/testsuite/gas/arm/vstr-thumb-bad.l: Likewise. * gas/testsuite/gas/arm/vstr-thumb-bad.d: Likewise. * gas/testsuite/gas/arm/vstr-arm-bad.l: Likewise. * gas/testsuite/gas/arm/vstr-arm-bad.d: Likewise.	2010-09-27 09:47:05 +00:00
Matthew Gretton-Dann	90ec0d684e	* bfd/bfd-in2.h (BFD_RELOC_ARM_HVC): New enum value. * gas/config/tc-arm.c (arm_ext_virt): New variable. (arm_reg_type): Add REG_TYPE_RNB for banked registers. (reg_entry): Allow registers to be larger than a byte. (reg_alias): Fix type warning. (parse_operands): Parse banked registers when appropriate. (do_mrs): Add support for Virtualization Extensions. (do_hvc): New function. (do_t_mrs): Add support for Virtualization Extensions. (do_t_msr): Likewise. (do_t_hvc): New function. (SPLRBANK): New define. (reg_names): Add banked registers. (insns): Add support for Virtualization Extensions. (md_apply_fixup): Likewise. (arm_cpus): -mcpu=cortex-a15 implies the Virtualization Extensions. (arm_extensions): Add 'virt' extension. (aeabi_set_public_attributes): Add support for Virtualization Extensions. * gas/doc/c-arm.texi: Document 'virt' extension. * gas/testsuite/gas/arm/armv7-a+virt.d: New test. * gas/testsuite/gas/arm/armv7-a+virt.s: Likewise. * gas/testsuite/gas/arm/attr-march-all.d: Update for Virtualization Extensions. * gas/testsuite/gas/arm/attr-march-armv7-a+sec+virt.d: New test. * gas/testsuite/gas/arm/attr-march-armv7-a+virt.d: Likewise. * include/opcode/arm.h (ARM_EXT_VIRT): New define. (ARM_ARCH_V7A_IDIV_MP_SEC): Rename... (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): ...to this and include Virtualization Extensions. * opcodes/arm-dis.c (arm_opcodes): Add Virtualiztion Extensions support. (thumb32_opcodes): Likewise. (banked_regname): New function. (print_insn_arm): Add Virtualization Extensions support. (print_insn_thumb32): Likewise.	2010-09-23 15:52:19 +00:00
Matthew Gretton-Dann	eea54501f7	* gas/config/tc-arm.c (arm_ext_adiv): New variable. (do_div): New function. (insns): Accept UDIV and SDIV in ARM state. (arm_cpus): The cortex-a15 option has all current v7-A extensions. (arm_extensions): Add 'idiv' extension. (aeabi_set_public_attributes): Update Tag_DIV_use values for the Integer Divide extension. * gas/doc/c-arm.texi: Document the idiv extension. * gas/testsuite/gas/arm/armv7-a+idiv.d: New test. * gas/testsuite/gas/arm/armv7-a+idiv.s: Likewise. * gas/testsuite/gas/arm/attr-march-all.d: Update for Integer divide extension. * gas/testsuite/gas/arm/attr-march-armv7-a+idiv.d: New test. * include/opcode/arm.h (ARM_AEXT_ADIV): New define. (ARM_ARCH_V7A_IDIV_MP_SEC): Likewise. * opcodes/arm-dis.c (arm_opcodes): Support disassembly of UDIV and SDIV in ARM state.	2010-09-23 15:37:45 +00:00
Matthew Gretton-Dann	f4c65163c7	* gas/config/tc-arm.c (arm_ext_v6z): Remove. (arm_ext_sec): New variable. (do_t_smc): In Thumb state SMC requires v7-A. (insns): Make SMC depend on Security Extensions. (arm_cpus): All -mcpu=cortex-a* options have the Security Extensions. (arm_extensions): Add 'sec' extension. (cpu_arch_ver): Reorder. (aeabi_set_public_attributes): Emit Tag_Virtualization_use as appropriate. * gas/doc/c-arm.texi: Document Security Extensions. * gas/testsuite/gas/arm/attr-march-all.d: Update for Security Extensions.. * gas/testsuite/gas/arm/attr-march-armv6k+sec.d: New test. * gas/testsuite/gas/arm/attr-march-armv6z.d: Update for Security Extensions. * gas/testsuite/gas/arm/attr-march-armv6zk.d: Likewise. * gas/testsuite/gas/arm/attr-march-armv6zkt2.d: Likewise. * gas/testsuite/gas/arm/attr-march-armv6zt2.d: Likewise. * gas/testsuite/gas/arm/attr-march-armv7-a+sec.d: New test. * gas/testsuite/gas/arm/attr-mcpu.d: Update for Security Extensions. * gas/testsuite/gas/arm/thumb32.d: Likewise. * gas/testsuite/gas/arm/thumb32.s: Likewise. * include/opcode/arm.h (ARM_EXT_V6Z): Remove. (ARM_EXT_SEC): New define. (ARM_AEXT_V6Z): Use Security Extensions. (ARM_AEXT_V6ZK): Likeiwse. (ARM_AEXT_V6ZT2): Likewise. (ARM_AEXT_V6ZKT2): Likewise. (ARM_AEXT_V7_ARM): Base v7 does not have Security Extensions. (ARM_ARCH_V7A_SEC): New define. (ARM_ARCH_V7A_MP): Rename... (ARM_ARCH_V7A_MP_SEC): ...to this and add Security Extensions. * ld/testsuite/ld-arm/attr-merge-6.attr: Update for Security Extensions. * ld/testsuite/ld-arm/attr-merge-7.attr: Likewise. * opcodes/arm-dis.c (arm_opcodes): SMC implies Security Extensions. (thumb32_opcodes): Likewise.	2010-09-23 15:26:24 +00:00
Matthew Gretton-Dann	60e5ef9f19	* gas/config/tc-arm.c (arm_ext_mp): Add. (do_pld): Update comment. (insns): Add support for pldw. (arm_cpus): Update cortex-a5, cortex-a9, and cortex-a15 to support MP extension. (arm_extensions): Add 'mp' extension. (aeabi_set_public_attributes): Emit correct build attribute when MP extension is enabled. * gas/doc/c-arm.texi: Update for MP extensions. * gas/testsuite/gas/arm/arch7a-mp.d: Add. * gas/testsuite/gas/arm/arch7ar-mp.s: Likewise. * gas/testsuite/gas/arm/arch7r-mp.d: Likewise. * gas/testsuite/gas/arm/armv2-mp-bad.d: Likewise. * gas/testsuite/gas/arm/armv2-mp-bad.l: Likewise. * gas/testsuite/gas/arm/attr-march-all.d: Update for MP extension. * gas/testsuite/gas/arm/attr-march-armv7-a+mp.d: Add. * gas/testsuite/gas/arm/attr-march-armv7-r+mp.d: Likewise. * include/opcode/arm.h (ARM_EXT_MP): Add. (ARM_ARCH_V7A_MP): Likewise. * opcodes/arm-dis.c (arm_opcodes): Add support for pldw. (thumb32_opcodes): Likewise.	2010-09-23 15:18:19 +00:00
Mike Frysinger	7a360e83fc	opcodes: blackfin: fix decoding of 32bit addresses on 64bit systems The Blackfin ISA is very exact with regards to address truncation when under/over flowing its 32bit range. On a 32bit system, things work the same and so addresses are decoded properly. On a 64bit system though, the decoded addresses may include the bits that are supposed to have been truncated. So force a 32bit truncation after the address has been calculated. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2010-09-22 21:55:17 +00:00
Mike Frysinger	35fc57f38c	opcodes: blackfin: fix decoding of all register move insns Many register move insns were not being decoded properly, so rewrite the whole function to be a bit more manageable in terms of valid combinations. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2010-09-22 21:54:33 +00:00
Mike Frysinger	219b747a3b	opcodes: blackfin: fix decoding of many invalid insns The Blackfin disassembler was originally based on the premise of parsing valid opcodes all the time, so some of the opcode checking can be a bit fuzzy. This is exemplified in decoding of parallel insns where many times things are decoded as invalid when in reality, they may not be used in parallel combinations. So add parallel checking to most insn decoding routines so we see ILLEGAL and not just whatever insn happens to be close to a valid mnemonic, as well as some additional sub-opcode checks. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2010-09-22 21:53:46 +00:00
Mike Frysinger	775f1cf0c2	opcodes: blackfin: mark push/pop insns with a P6/P7 range as illegal The push/pop multiple insn has a 3 bit field for the P register range, but only values of 0...5 are valid (P0 - P5). There is no such P6 or P7 register, so mark these insns as illegal. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2010-09-22 21:53:14 +00:00
Mike Frysinger	0b7691fd6e	opcodes: blackfin: fix decoding of vector shift insn w/saturation The saturation bit was missed when decoding a vector shift insn leading to the output looking the same as the non-saturating insn. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2010-09-22 21:41:39 +00:00
Mike Frysinger	b2459327a6	opcodes: blackfin: decode all ASTAT bits All ASTAT bits work in the hardware even though they aren't part of the official Blackfin ISA. So decode every ASTAT field to make the output a bit nicer when working with hand generated opcodes. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2010-09-22 21:39:08 +00:00
Mike Frysinger	50e2162a22	opcodes: blackfin: decode insns with invalid register as illegal Sometimes the encoding in the opcode is a 4 bit field which defines a register number. However, register numbers are only 0-7, so make sure we call illegal for when the opcode register number is greater than 8. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2010-09-22 21:38:20 +00:00
Mike Frysinger	a01eda858f	gas: blackfin: fix DBG/DBGCMPLX insn encoding Some extended registers when given to the DBG/DBGCMPLX pseudo insns are not encoded properly. So fix them, fix the display of them when being disassembled, and add testcases. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2010-09-22 21:26:13 +00:00
Mike Frysinger	22215ae09b	opcodes/gas: blackfin: handle more ASTAT flags Support a few more ASTAT bits with the standard insns that operate on ASTAT bits directly. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2010-09-22 21:05:03 +00:00
Mike Frysinger	73a63ccf2f	opcodes/gas: blackfin: support OUTC debug insn The disassembler has partial (but incomplete/broken) support already for the pseudo debug insn OUTC, so let's fix it up and finish it. And now that the disassembler can handle it, make sure our assembler can output it too. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2010-09-22 20:59:00 +00:00
Mike Frysinger	59a82d2333	opcodes: blackfin: fix decoding of LSHIFT insns The Blackfin ISA does not have a "SHIFT" insn, it has either LSHIFT, ASHIFT, or BXORSHIFT. So be specific when disassembling. As fall out of this change, we need to update some assembler tests. Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2010-09-22 20:37:25 +00:00
Mike Frysinger	528c6277f7	opcodes: blackfin: constify formatting related structures No need for these local structures related to formatting of output to be writable, so constify the whole shebang. Signed-off-by: Mike Frysinger <vapier@gentoo.org>	2010-09-22 20:32:40 +00:00
Matthew Gretton-Dann	db472d6ff0	2010-09-17 Tejas Belagod <tejas.belagod@arm.com> * config/tc-arm.c (insns): Change MRC entry to accept APSR_RR instead of just RR. 2010-09-17 Tejas Belagod <tejas.belagod@arm.com> * gas/arm/copro.s: Add test for APSR_nzcv as a MRC operand. * gas/arm/copro.d: Change pc in MRC to disassemble as APSR_nzcv. Also add disassembly for test added in copro.s 2010-09-17 Tejas Belagod <tejas.belagod@arm.com> * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.	2010-09-17 10:13:41 +00:00
Maciej W. Rozycki	f6690563bb	opcodes/ * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire", "sync_mb", "sync_release", "sync_rmb" and "sync_wmb". gas/testsuite/ * gas/mips/mips32r2-sync.d: New test for MIPS32r2 "sync" instruction variants. * gas/mips/octeon@mips32r2-sync.d: Likewise, Octeon version. * gas/mips/mips32r2-sync.s: Source for the new test. * gas/mips/mips.exp: Run the new test.	2010-09-14 23:49:04 +00:00
Pierre Muller	8901a3cd7d	* src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for dlx_insn_type array.	2010-09-10 13:00:54 +00:00
H.J. Lu	d9e3625e37	Fix "pushw imm16" for x86-64 disassembler. gas/testsuite/ 2010-08-31 H.J. Lu <hongjiu.lu@intel.com> PR binutils/11960 * gas/i386/opcode-intel.d: Updated. * gas/i386/x86-64-opcode.d: Likewise. * gas/i386/x86-64-opcode.s: Add a "pushw imm16" test. opcodes/ 2010-08-31 H.J. Lu <hongjiu.lu@intel.com> PR binutils/11960 * i386-dis.c (sIv): New. (dis386): Replace Iq with sIv on "pushT". (reg_table): Replace T with {T\|} on callT, JcallT, jmpT and JjmpT. (x86_64_table): Replace {T\|}/{P\|} with P. (putop): Add 'w' to 'T'/'P' if needed for Intel syntax. (OP_sI): Update v_mode. Remove w_mode.	2010-08-31 21:56:57 +00:00
Nathan Froyd	f383de6633	opcodes/ * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate on E500 and E500MC.	2010-08-27 13:59:55 +00:00
H.J. Lu	1ab03f4b26	Replace Eb with Mb on prefetch and prefetchw. 2010-08-17 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and prefetchw.	2010-08-17 20:37:26 +00:00
H.J. Lu	2210942396	Don't generate multi-byte NOPs for i686. gas/ 2010-08-06 Quentin Neill <quentin.neill@amd.com> * config/tc-i386.c (arch_entry): Add negated bit to disambiguate flag names starting with "no". (cpu_arch): Add negated bit definitions. Add ".nop" CPU extension. (i386_align_code): Use new .cpunop bit to decide when to generate alignment using nops. (set_cpu_arch): Use negated bit instead to decide when to use cpu_flags or vs. cpu_flags_and_not. (md_parse_option): Likewise. gas/testsuite/ 2010-08-06 Quentin Neill <quentin.neill@amd.com> * gas/i386/arch-10-1.l: Add nopl instruction. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/arch-10.s: Likewise. * gas/i386/arch-10.d: Add nopl instruction, and +nopl extension flag to as flags. * gas/i386/nops-5-i686.d: Change alignment code generated for -mtune=i686. * gas/i386/nops-5.d: Change alignment code generated for .arch i686. * gas/i386/x86-64-nops-5-k8.d: Likewise. * gas/i386/x86-64-nops-5.d: Likewise. opcodes/ 2010-08-06 Quentin Neill <quentin.neill@amd.com> * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add to processor flags for PENTIUMPRO processors and later. * i386-opc.h (enum): Add CpuNop. (i386_cpu_flags): Add cpunop bit. * i386-opc.tbl: Change nop cpu_flags. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	2010-08-06 18:22:50 +00:00
H.J. Lu	b49dfb4a38	Fix typos in comments in i386-opc.h. 2010-08-06 Quentin Neill <quentin.neill@amd.com> * i386-opc.h (enum): Fix typos in comments.	2010-08-06 16:33:43 +00:00
Alan Modra	6ca4eb7789	* disassemble.c: Formatting. (disassemble_init_for_target <ARCH_m32c>): Comment on endian.	2010-08-06 03:59:49 +00:00
H.J. Lu	92d4d42efb	Add Cpu186 to ud1/ud2/ud2a/ud2b. 2010-08-05 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b. * i386-tbl.h: Regenerated.	2010-08-06 01:03:17 +00:00
H.J. Lu	b414985b9e	Add ud1 to x86. gas/testsuite/ 2010-08-05 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run arch-4. * gas/i386/arch-4.d: New. * gas/i386/arch-4.s: Likewise. * gas/i386/intel.d: Replace ud2a/ud2b with ud2/ud1. * gas/i386/opcode-intel.d: Likewise. * gas/i386/opcode-suffix.d: Likewise. * gas/i386/opcode.d: Likewise. opcodes/ 2010-08-05 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1. * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b. * i386-tbl.h: Regenerated.	2010-08-06 00:52:57 +00:00
DJ Delorie	f9c7014e9c	[include/opcode] * rx.h (RX_Operand_Type): Add TwoReg. (RX_Opcode_ID): Remove ediv and ediv2. [opcodes] * rx-decode.opc (SRR): New. (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov r0,r0) and NOP3 (max r0,r0) special cases. * rx-decode.c: Regenerate. [sim/rx] * rx.c (decode_cache_base): New. (id_names): Remove ediv and edivu. (optype_names): Add TwoReg. (maybe_get_mem_page): New. (rx_get_byte): Call it. (get_op): Add TwoReg support. (put_op): Likewise. (PD, PS, PS2, GD, GS, GS2, DSZ, SSZ, S2SZ, US1, US2, OM): "opcode" is a pointer now. (DO_RETURN): New. We use longjmp to return an exception result. (decode_opcode): Make opcode a pointer to the decode cache. Save decoded opcode information and re-use. Call DO_RETURN instead of return throughout. Remove ediv and edivu. * mem.c (ptdc): New. Adds decode cache. (rx_mem_ptr): Support it. (rx_mem_decode_cache): New. * mem.h (enum mem_ptr_action): add MPA_DECODE_CACHE. (rx_mem_decode_cache): Declare. * gdb-if.c (sim_resume): Add decode_opcode's setjmp logic here... * main.c (main): ...and here. Use a fast loop if neither trace nor disassemble is given. * cpu.h (RX_MAKE_STEPPED, RX_MAKE_HIT_BREAK, RX_MAKE_EXITED, RX_MAKE_STOPPED, RX_EXITED, RX_STOPPED): Adjust so that 0 is not a valid code for anything.	2010-07-29 18:41:28 +00:00
H.J. Lu	592a252b66	Add 0F to VEX opcode enums. 2010-07-28 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c: Add 0F to VEX opcode enums.	2010-07-28 21:54:34 +00:00
DJ Delorie	3cf79a015d	* rx-decode.opc (store_flags): Remove, replace with F_* macros. (rx_decode_opcode): Likewise. * rx-decode.c: Regenerate.	2010-07-28 00:36:46 +00:00
Nick Clifton	1cd986c585	Add support for v850E2 and v850E2V3	2010-07-23 14:52:54 +00:00
Richard Earnshaw	52e7f43db0	2010-07-08 Tejas Belagod <tejas.belagod@arm.com> gas/testsuite * gas/arm/barrier.s: New file. * gas/arm/barrier.d: New file. * gas/arm/barrier-thumb.s: New file. * gas/arm/barrier-thumb.d: New file. * gas/arm/barrier-bad.s: New file. * gas/arm/barrier-bad.d: New file. * gas/arm/barrier-bad.l: New file. * gas/arm/barrier-bad-thumb.s: New file. * gas/arm/barrier-bad-thumb.d: New file. * gas/arm/barrier-bad-thumb.l: New file. gas/config * tc-arm.c (OP_oBARRIER): Remove. (OP_oBARRIER_I15): Add. (po_barrier_or_imm): Add macro. (parse_operands): Improve OP_oBARRIER_I15 operand parsing. (do_barrier): Check correct immediate range. (do_t_barrier): Likewise. (barrier_opt_names): Add entries for more symbolic operands. (insns): Replace OP_oBARRIER with OP_oBARRIER_I15 for barriers. opcodes/ * arm-dis.c (print_insn_arm): Add cases for printing more symbolic operands. (print_insn_thumb32): Likewise.	2010-07-08 22:40:28 +00:00
Maciej W. Rozycki	c680e7f672	* mips-dis.c (print_insn_mips): Correct branch instruction type determination.	2010-07-06 00:06:04 +00:00
Maciej W. Rozycki	9a2c708887	gas/ * config/tc-mips.c (nops_for_insn_or_target): Replace MIPS16_INSN_BRANCH with MIPS16_INSN_UNCOND_BRANCH and MIPS16_INSN_COND_BRANCH. include/opcode/ * mips.h (MIPS16_INSN_UNCOND_BRANCH): New macro. (MIPS16_INSN_BRANCH): Rename to... (MIPS16_INSN_COND_BRANCH): ... this. opcodes/ * mips-dis.c (print_mips16_insn_arg): Remove branch instruction type and delay slot determination. (print_insn_mips16): Extend branch instruction type and delay slot determination to cover all instructions. * mips16-opc.c (BR): Remove macro. (UBR, CBR): New macros. (mips16_opcodes): Update branch annotation for "b", "beqz", "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc" and "jrc".	2010-07-06 00:02:46 +00:00
H.J. Lu	d7d9a9f820	Replace rdrnd with rdrand. gas/testsuite/ 2010-07-05 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * gas/i386/rdrnd.s: Replace rdrnd with rdrand. * gas/i386/rdrnd-intel.d: Likewise. * gas/i386/rdrnd.d: Likewise. * gas/i386/x86-64-rdrnd-intel.d: Likewise. * gas/i386/x86-64-rdrnd.d: Likewise. * gas/i386/x86-64-rdrnd.s: Likewise. opcodes/ 2010-07-05 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * i386-dis.c (mod_table): Replace rdrnd with rdrand. * i386-opc.tbl: Likewise. * i386-tbl.h: Regenerated.	2010-07-05 17:14:22 +00:00
H.J. Lu	77321f5360	Fix a typo in comments for CpuFSGSBase. 2010-07-05 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h (CpuFSGSBase): Fix a typo in comments.	2010-07-05 16:40:32 +00:00
Andreas Schwab	3a5530eaab	Update.	2010-07-03 08:29:51 +00:00
Andreas Schwab	7102e95e49	gas/: * config/tc-ppc.c (ppc_set_cpu): Cast PPC_OPCODE_xxx to ppc_cpu_t before inverting. binutils/: * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to ppc_cpu_t before inverting.	2010-07-03 08:27:23 +00:00
Alan Modra	bdc70b4a03	include/opcode/ * ppc.h (PPC_OPCODE_32, PPC_OPCODE_BOOKE64, PPC_OPCODE_CLASSIC): Delete. Renumber other PPC_OPCODE defines. gas/ * config/tc-ppc.c (ppc_set_cpu): Remove old opcode flags. (ppc_setup_opcodes): Likewise. Simplify opcode selection. opcodes/ * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags. * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete. (PPC64, MFDEC2): Update. (NON32, NO371): Define. (powerpc_opcode): Update to not use old opcode flags, and avoid -m601 duplicates.	2010-07-03 06:51:56 +00:00
DJ Delorie	21375995bd	* m32c.cpu (f-dsp-8-s24): Mask high byte after shifting it. * m32c-ibld.c: Regenerate.	2010-07-03 04:09:56 +00:00
Alan Modra	81a0b7e2ae	* ppc-opc.c (PWR2COM): Define. (PPCPWR2): Add PPC_OPCODE_COMMON. (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.", "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst", "rac" from -mcom.	2010-07-03 03:33:17 +00:00
H.J. Lu	a00eb5e843	Update ChangeLog entry.	2010-07-01 21:57:04 +00:00
H.J. Lu	c7b8aa3a72	Support AVX Programming Reference (June, 2010) gas/ 2010-07-01 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * config/tc-i386.c (cpu_arch): Add .xsaveopt, .fsgsbase, .rdrnd and .f16c. * doc/c-i386.texi: Document xsaveopt, fsgsbase, rdrnd and f16c. gas/testsuite/ 2010-07-01 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * gas/i386/arch-10.s: Add xsaveopt. * gas/i386/x86-64-arch-2.s: Likwise. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/f16c-intel.d: New. * gas/i386/f16c.d: Likewise. * gas/i386/f16c.s: Likewise. * gas/i386/fsgs-intel.d: Likewise. * gas/i386/fsgs.d: Likewise. * gas/i386/fsgs.s: Likewise. * gas/i386/rdrnd-intel.d: Likewise. * gas/i386/rdrnd.d: Likewise. * gas/i386/rdrnd.s: Likewise. * gas/i386/x86-64-f16c-intel.d: Likewise. * gas/i386/x86-64-f16c.d: Likewise. * gas/i386/x86-64-f16c.s: Likewise. * gas/i386/x86-64-fsgs-intel.d: Likewise. * gas/i386/x86-64-fsgs.d: Likewise. * gas/i386/x86-64-fsgs.s: Likewise. * gas/i386/x86-64-rdrnd-intel.d: Likewise. * gas/i386/x86-64-rdrnd.d: Likewise. * gas/i386/x86-64-rdrnd.s: Likewise. * gas/i386/i386.exp: Run f16c, f16c-intel, fsgs, fsgs-intel, rdrnd, rdrnd-intel, x86-64-f16c, x86-64-f16c-intel, x86-64-fsgs, x86-64-fsgs-intel, x86-64-rdrnd, x86-64-rdrnd-intel. * gas/i386/x86-64-xsave.s: Add tests for xsaveopt64. * gas/i386/x86-64-xsave-intel.d: Updated. * gas/i386/x86-64-xsave.d: Likewise. opcodes/ 2010-07-01 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (June, 2010) * i386-dis.c (PREFIX_0FAE_REG_0): New. (PREFIX_0FAE_REG_1): Likewise. (PREFIX_0FAE_REG_2): Likewise. (PREFIX_0FAE_REG_3): Likewise. (PREFIX_VEX_3813): Likewise. (PREFIX_VEX_3A1D): Likewise. (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1, PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and PREFIX_VEX_3A1D. (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D. (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1, PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd. * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS, CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS. (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C. * i386-opc.h (CpuXsaveopt): New. (CpuFSGSBase):Likewise. (CpuRdRnd): Likewise. (CpuF16C): Likewise. (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and cpuf16c. * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd, wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.	2010-07-01 21:55:02 +00:00
Alan Modra	09a8ad8d8f	* ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf and mtocrf on EFS.	2010-07-01 02:29:12 +00:00
Alan Modra	360cfc9c8b	remove maxq-coff port	2010-06-29 04:17:34 +00:00
Alan Modra	dc898d5e26	cgen/ * cpu/mep.opc (mep_examine_ivc2_insns): Delete set but unused var. opcodes/ * mep-dis.c: Regenerate.	2010-06-28 14:41:59 +00:00
Matthew Gretton-Dann	8e56076649	* gas/config/tc-arm.c (parse_neon_alignment): New function. (parse_address_main): Fix Neon load/store alignment parsing. * gas/testsuite/gas/arm/neon-ldst-align-bad.l: Update for Neon alignment syntax fix. * gas/testsuite/gas/arm/neon-ldst-align-bad.s: Likewise. * gas/testsuite/gas/arm/neon-ldst-es.d: Likewise. * gas/testsuite/gas/arm/neon-ldst-es.s: Likewise. * opcodes/arm-disc.c (parse_insn_neon): Fix Neon alignment syntax.	2010-06-28 09:10:25 +00:00
Alan Modra	c7e2358a88	fix set but unused variable warnings	2010-06-27 04:07:55 +00:00
Nick Clifton	6ffe3d995f	PR gas/11673 * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later. * gas/m68k/p11673.s: New test. * gas/m68k/all.exp: Run the new test.	2010-06-16 16:27:37 +00:00
Nick Clifton	09ec0d177a	2010-06-16 Vincent Rivire <vincent.riviere@freesbee.fr> PR binutils/11676 * m68k-dis.c (print_insn_arg): Prefix float constants with #0e. 2010-06-16 Nick Clifton <nickc@redhat.com> PR binutils/11676 * gas/m68k/pr11676.s: New test. * gas/m68k/pr11676.d: Expected disassembly. * gas/m68k/all.exp: Run the new test.	2010-06-16 15:12:51 +00:00
Alan Modra	e01d869a3b	gas/ * config/tc-ppc.c (md_assemble): Emit APUinfo section for PPC_OPCODE_E500. gas/testsuite/ * gas/ppc/e500.s: Add eieio, mbar and lwsync * gas/ppc/e500.d: Likewise. include/opcode/ * ppc.h (PPC_OPCODE_E500): Define. opcodes/ * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and e500x2. Add PPC_OPCODE_E500 to e500 and e500x2 * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which touch floating point regs and are enabled by COM, PPC or PPCCOM. Treat sync as msync on e500. Treat eieio as mbar 1 on e500. Treat lwsync as msync on e500.	2010-06-14 14:48:05 +00:00
Matthew Gretton-Dann	1f4e495053	* gas/testsuite/gas/arm/thumb-eabi.d: Add case for divided syntax encoding of movs. * gas/testsuite/gas/arm/thumb.d: Likewise. * gas/testsuite/gas/arm/thumb.s: Likewise. * gas/testsuite/gas/arm/thumb2_it.d: Update for change in lsls/movs disassembly. * gas/testsuite/gas/arm/thumb2_it_auto.d: Liekwise. * gas/testsuite/gas/arm/thumb32.d: Likewise. * ld/testsuite/ld-arm/arm-call.d: Handle change in lsls/movs disassembly. * ld/testsuite/ld-arm/farcall-thumb-arm-short.d: Likewise. * ld/testsuite/ld-arm/farcall-thumb-thumb-blx-pic-veneer.d: Likewise. * ld/testsuite/ld-arm/farcall-thumb-thumb-blx.d: Likewise. * ld/testsuite/ld-arm/farcall-thumb-thumb-m-pic-veneer.d: Likewise. * ld/testsuite/ld-arm/farcall-thumb-thumb-m.d: Likewise. * ld/testsuite/ld-arm/farcall-thumb-thumb-pic-veneer.d: Likewise. * ld/testsuite/ld-arm/farcall-thumb-thumb.d: Likewise. * ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad-noeabi.d: Likewise. * ld/testsuite/ld-arm/thumb2-bl-as-thumb1-bad.d: Likewise. * ld/testsuite/ld-arm/thumb2-bl-bad-noeabi.d: Likewise. * ld/testsuite/ld-arm/thumb2-bl-bad.d: Likewise. * opcodes/arm-dis.c (thumb-opcodes): Add disassembly for movs.	2010-06-07 10:43:52 +00:00
Matthew Gretton-Dann	9d82ec3801	* opcodes/arm-dis.c (print_insn_neon): Ensure disassembly of Neon constants is the same on 32-bit and 64-bit hosts.	2010-05-28 16:04:21 +00:00
Nick Clifton	c3a6ea62fc	Fix typo in ChangeLog entry.	2010-05-27 10:45:52 +00:00
Nick Clifton	d8b24b9569	* m68k-dis.c (print_insn_m68k): Emit undefined instructions as .short directives so that they can be reassembled.	2010-05-27 10:43:27 +00:00
Catherine Moore	9db8dccb17	2010-05-26 Catherine Moore <clm@codesourcery.com> David Ung <davidu@mips.com> * mips-opc.c: Change membership to I1 for instructions ssnop and ehb. 2010-05-26 Catherine Moore <clm@codesoucery.com> Maxim Kuvyrkov <maxim@codesourcery.com> * gas/mips/set-arch.d: Expect ehb.	2010-05-26 21:49:30 +00:00
H.J. Lu	dfc8cf43a1	Add SIB. 2010-05-26 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (sib): New. (get_sib): Likewise. (print_insn): Call get_sib. OP_E_memory): Use sib.	2010-05-26 16:08:23 +00:00
Catherine Moore	f79e2745b2	gas/ * config/tc-mips.c (is_opcode_valid): Remove expansionp. (macro_build): Change invocation of is_opcode_valid. (mips_ip): Likewise. gas/testsuite/ * gas/mips/mips-no-jalx.l: Delete. * gas/mips/mips-no-jalx.s: Delete. * gas/mips/mips-jalx-2.d: New. * gas/mips/mips-jalx-2.s: New. * gas/mips/mips.exp (mips-jalx-2): Run new test. (mips-no-jalx): Remove deleted test. include/ * opcode/mips.h (INSN_MIPS16): Remove. opcodes/ * mips-dis.c (mips_arch): Remove INSN_MIPS16. * mips-opc.c (I16): Remove. (mips_builtin_op): Reclassify jalx.	2010-05-26 12:59:56 +00:00
Alan Modra	51b5d4a8c5	* ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde, divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx.	2010-05-19 03:44:36 +00:00
Alan Modra	85d4ac0b3c	Correct wclr encoding.	2010-05-13 06:30:09 +00:00
Nick Clifton	4547cb569c	2010-05-10 Andrew Stubbs <ams@codesourcery.com> gas/ * config/tc-arm.c (aeabi_set_public_attributes): Set Tag_DIV_use. gas/testsuite/ * gas/arm/attr-cpu-directive.d: Add Tag_DIV_use. * gas/arm/attr-default.d: Likewise. * gas/arm/attr-march-armv1.d: Likewise. * gas/arm/attr-march-armv2.d: Likewise. * gas/arm/attr-march-armv2a.d: Likewise. * gas/arm/attr-march-armv2s.d: Likewise. * gas/arm/attr-march-armv3.d: Likewise. * gas/arm/attr-march-armv3m.d: Likewise. * gas/arm/attr-march-armv4.d: Likewise. * gas/arm/attr-march-armv4t.d: Likewise. * gas/arm/attr-march-armv4txm.d: Likewise. * gas/arm/attr-march-armv4xm.d: Likewise. * gas/arm/attr-march-armv5.d: Likewise. * gas/arm/attr-march-armv5t.d: Likewise. * gas/arm/attr-march-armv5te.d: Likewise. * gas/arm/attr-march-armv5tej.d: Likewise. * gas/arm/attr-march-armv5texp.d: Likewise. * gas/arm/attr-march-armv5txm.d: Likewise. * gas/arm/attr-march-armv6-m.d: Likewise. * gas/arm/attr-march-armv6.d: Likewise. * gas/arm/attr-march-armv6j.d: Likewise. * gas/arm/attr-march-armv6k.d: Likewise. * gas/arm/attr-march-armv6kt2.d: Likewise. * gas/arm/attr-march-armv6t2.d: Likewise. * gas/arm/attr-march-armv6z.d: Likewise. * gas/arm/attr-march-armv6zk.d: Likewise. * gas/arm/attr-march-armv6zkt2.d: Likewise. * gas/arm/attr-march-armv6zt2.d: Likewise. * gas/arm/attr-march-armv7-a.d: Likewise. * gas/arm/attr-march-armv7.d: Likewise. * gas/arm/attr-march-armv7a.d: Likewise. * gas/arm/attr-march-iwmmxt.d: Likewise. * gas/arm/attr-march-iwmmxt2.d: Likewise. * gas/arm/attr-march-marvell-f.d: Likewise. * gas/arm/attr-march-xscale.d: Likewise. * gas/arm/attr-mcpu.d: Likewise. * gas/arm/attr-mfpu-arm1020e.d: Likewise. * gas/arm/attr-mfpu-arm1020t.d: Likewise. * gas/arm/attr-mfpu-arm1136jf-s.d: Likewise. * gas/arm/attr-mfpu-arm1136jfs.d: Likewise. * gas/arm/attr-mfpu-arm7500fe.d: Likewise. * gas/arm/attr-mfpu-fpa.d: Likewise. * gas/arm/attr-mfpu-fpa10.d: Likewise. * gas/arm/attr-mfpu-fpa11.d: Likewise. * gas/arm/attr-mfpu-fpe.d: Likewise. * gas/arm/attr-mfpu-fpe2.d: Likewise. * gas/arm/attr-mfpu-fpe3.d: Likewise. * gas/arm/attr-mfpu-maverick.d: Likewise. * gas/arm/attr-mfpu-neon-fp16.d: Likewise. * gas/arm/attr-mfpu-neon.d: Likewise. * gas/arm/attr-mfpu-softfpa.d: Likewise. * gas/arm/attr-mfpu-softvfp+vfp.d: Likewise. * gas/arm/attr-mfpu-softvfp.d: Likewise. * gas/arm/attr-mfpu-vfp.d: Likewise. * gas/arm/attr-mfpu-vfp10-r0.d: Likewise. * gas/arm/attr-mfpu-vfp10.d: Likewise. * gas/arm/attr-mfpu-vfp3.d: Likewise. * gas/arm/attr-mfpu-vfp9.d: Likewise. * gas/arm/attr-mfpu-vfpv2.d: Likewise. * gas/arm/attr-mfpu-vfpv3-d16.d: Likewise. * gas/arm/attr-mfpu-vfpv3.d: Likewise. * gas/arm/attr-mfpu-vfpv4-d16.d: Likewise. * gas/arm/attr-mfpu-vfpv4.d: Likewise. * gas/arm/attr-mfpu-vfpxd.d: Likewise. * gas/arm/attr-order.d: Likewise. * gas/arm/attr-override-cpu-directive.d: Likewise. * gas/arm/attr-override-mcpu.d: Likewise. * gas/arm/eabi_attr_1.d: Likewise. ld/testsuite/ * ld-arm/attr-merge-2.attr: Add Tag_DIV_use. * ld-arm/attr-merge-2a.s: Likewise. * ld-arm/attr-merge-2b.s: Likewise. * ld-arm/attr-merge-3a.s: Likewise. * ld-arm/attr-merge-3b.s: Likewise. * ld-arm/attr-merge-4.attr: Likewise. * ld-arm/attr-merge-5.attr: Likewise. * ld-arm/attr-merge-6.attr: Likewise. * ld-arm/attr-merge-7.attr: Likewise. * ld-arm/attr-merge-arch-1.attr: Likewise. * ld-arm/attr-merge-arch-2.attr: Likewise. * ld-arm/attr-merge-unknown-2.d: Likewise. * ld-arm/attr-merge-unknown-2r.d: Likewise. * ld-arm/attr-merge-unknown-3.d: Likewise. * ld-arm/attr-merge-vfp-1.d: Likewise. * ld-arm/attr-merge-vfp-1r.d: Likewise. * ld-arm/attr-merge-vfp-2.d: Likewise. * ld-arm/attr-merge-vfp-2r.d: Likewise. * ld-arm/attr-merge-vfp-3.d: Likewise. * ld-arm/attr-merge-vfp-3r.d: Likewise. * ld-arm/attr-merge-vfp-4.d: Likewise. * ld-arm/attr-merge-vfp-4r.d: Likewise. * ld-arm/attr-merge-vfp-5.d: Likewise. * ld-arm/attr-merge-vfp-5r.d: Likewise. * ld-arm/attr-merge-wchar-00-nowarn.d: Likewise. * ld-arm/attr-merge-wchar-00.d: Likewise. * ld-arm/attr-merge-wchar-02-nowarn.d: Likewise. * ld-arm/attr-merge-wchar-02.d: Likewise. * ld-arm/attr-merge-wchar-04-nowarn.d: Likewise. * ld-arm/attr-merge-wchar-04.d: Likewise. * ld-arm/attr-merge-wchar-20-nowarn.d: Likewise. * ld-arm/attr-merge-wchar-20.d: Likewise. * ld-arm/attr-merge-wchar-22-nowarn.d: Likewise. * ld-arm/attr-merge-wchar-22.d: Likewise. * ld-arm/attr-merge-wchar-24-nowarn.d: Likewise. * ld-arm/attr-merge-wchar-40-nowarn.d: Likewise. * ld-arm/attr-merge-wchar-40.d: Likewise. * ld-arm/attr-merge-wchar-42-nowarn.d: Likewise. * ld-arm/attr-merge-wchar-44-nowarn.d: Likewise. * ld-arm/attr-merge-wchar-44.d: Likewise. * ld-arm/attr-merge.attr: Likewise. 2010-04-07 Jie Zhang <jie@codesourcery.com> gas/ * config/tc-arm.c (aeabi_set_public_attributes): Set Tag_ABI_HardFP_use to 1 if a single precision FPU is selected. gas/testsuite/ * gas/arm/attr-mfpu-vfpxd.d: New test. bfd/ * elf32-arm.c (elf32_arm_merge_eabi_attributes): Merge Tag_ABI_HardFP_use correctly. ld/testsuite/ * ld-arm/attr-merge-vfp-6.d: New test. * ld-arm/attr-merge-vfp-6r.d: New test. * ld-arm/attr-merge-vfpv3xd.s: New test. * ld-arm/arm-elf.exp: Add attr-merge-vfp-6 and attr-merge-vfp-6r. 2010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com> * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W format. (print_insn_thumb16): Add support for new %W format. * gas/arm/thumb32.d: Fix expected disassembly of ldmia instruction.	2010-05-11 17:36:33 +00:00
Tristan Gingold	6540b386f0	bfd/ 2010-05-07 Tristan Gingold <gingold@adacore.com> * Makefile.in: Regenerate with automake 1.11.1. * aclocal.m4: Ditto. bfd/doc/ 2010-05-07 Tristan Gingold <gingold@adacore.com> * Makefile.in: Regenerate with automake 1.11.1. binutils/ 2010-05-07 Tristan Gingold <gingold@adacore.com> * Makefile.in: Regenerate with automake 1.11.1. * aclocal.m4: Ditto. * doc/Makefile.in: Ditto. gas/ 2010-05-07 Tristan Gingold <gingold@adacore.com> * Makefile.in: Regenerate with automake 1.11.1. * aclocal.m4: Ditto. * doc/Makefile.in: Ditto. gprof/ 2010-05-07 Tristan Gingold <gingold@adacore.com> * Makefile.in: Regenerate with automake 1.11.1. * aclocal.m4: Ditto. ld/ 2010-05-07 Tristan Gingold <gingold@adacore.com> * Makefile.in: Regenerate with automake 1.11.1. * aclocal.m4: Ditto. opcodes/ 2010-05-07 Tristan Gingold <gingold@adacore.com> * Makefile.in: Regenerate with automake 1.11.1. * aclocal.m4: Ditto.	2010-05-07 12:28:50 +00:00
Nick Clifton	3e01a7fd46	Updated Spanish translations.	2010-05-05 15:28:26 +00:00
Nick Clifton	9c9c98a59d	Updated translation templates. Updated Bulgarian translation. Updated Finnish translations. Updated French translations. Updated Vietnamese translations.	2010-04-22 14:37:16 +00:00
H.J. Lu	9e3223abf4	Remove extra breack.	2010-04-16 21:37:08 +00:00
H.J. Lu	f07af43e36	Return bad_opcode on unknown bits in opcode. 2010-04-16 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown bits in opcode.	2010-04-16 21:35:24 +00:00
Nick Clifton	3d540e936b	bfd/ChangeLog 2010-04-09 Nick Clifton <nickc@redhat.com> * aoutx.h (aout_link_input_bfd): Remove unused variable sym_count. * elf-eh-frame.c (_bfd_elf_eh_frame_section_offset): Remove unused variables htab and hdr_info and mark info parameter as unused. * elf.c (prep_headers): Remove unused variable i_phdrp. (_bfd_elf_write_object_contents): Remove unused variable i_ehdrp. * elf32-i386.c (elf_i386_relocate_section): Mark variabled warned as unused. * peXXigen.c (pe_print_reloc): Remove unused variable datasize. * verilog.c (verilog_write_section): Remove unused variable address. binutils/ChangeLog 2010-04-09 Nick Clifton <nickc@redhat.com> * dwarf.c (process_debug_info): Remove unused variable cu_abbrev_offset_ptr. (display_debug_lines_decoded): Remove unused variable prev_line. * elfedit.c (process_archive): Remove unused variable file_name_size. * ieee.c (ieee_start_compilation_unit): Remove unused variable nindx. (ieee_set_type): Remove unused variables info, targetindx and baseindx. * objdump.c (disassmble_byte): Remove unused variable done_dot. * rddbg.c (read_section_stabs_debugging_info): Remove unused variable other. * readelf.c (dump_section_as_strings): Remove unused variable addr. (process_archive): Remove unused variable file_name_size. * stabs.c (parse_stab_string): Mark desc parameter as unused. Remove unused variable lineno. (parse_stab_struct_type): Remove unused variable orig. (stab_demangle_type): Remove unused variables constp, volatilep and hold. gas/ChangeLog 2010-04-09 Nick Clifton <nickc@redhat.com> * as.c (create_obj_attrs_section): Remove unused variable addr. * listing.c (listing_listing): Remove unused variable message. * read.c: Remove unnecessary register type qualifiers. (s_mri): Only define/use old_flag variable if MRI_MODE_CHANGE is defined. ld/ChangeLog 2010-04-09 Nick Clifton <nickc@redhat.com> * ldlang.c (wild_sort): Remove unused variable section_name. opcodes/ChangeLog 2010-04-09 Nick Clifton <nickc@redhat.com> * i386-dis.c (print_insn): Remove unused variable op. (OP_sI): Remove unused variable mask.	2010-04-09 14:40:18 +00:00
Alan Modra	397841b5ae	* configure: Regenerate.	2010-04-07 07:20:51 +00:00
Peter Bergner	cee62821d4	opcodes/ * ppc-opc.c (RBOPT): New define. ("dccci"): Enable for PPCA2. Make operands optional. ("iccci"): Likewise. Do not deprecate for PPC476. gas/testsuite/ * gas/ppc/476.d ("dccci", "dci", "iccci"): Add tests. * gas/ppc/476.s: Likewise. * gas/ppc/a2.d ("dccci", "dci", "iccci", "ici"): Add tests. * gas/ppc/a2.s: Likewise.	2010-04-06 16:04:34 +00:00
Nick Clifton	accf44633e	* cr16-opc.c (cr16_instruction): Fix typo in comment.	2010-04-06 15:41:43 +00:00
Joseph Myers	40b365969f	bfd: * Makefile.am (ALL_MACHINES): Add cpu-tic6x.lo. (ALL_MACHINES_CFILES): Add cpu-tic6x.c. (BFD32_BACKENDS): Add elf32-tic6x.lo. (BFD32_BACKENDS_CFILES): Add elf32-tic6x.c. * Makefile.in: Regenerate. * archures.c (bfd_arch_tic6x, bfd_tic6x_arch): New. (bfd_archures_list): Update. * config.bfd (tic6x--elf): New. configure.in (bfd_elf32_tic6x_be_vec, bfd_elf32_tic6x_le_vec): New. * configure: Regenerate. * cpu-tic6x.c, elf32-tic6x.c: New. * reloc.c (BFD_RELOC_C6000_PCR_S21, BFD_RELOC_C6000_PCR_S12, BFD_RELOC_C6000_PCR_S10, BFD_RELOC_C6000_PCR_S7, BFD_RELOC_C6000_ABS_S16, BFD_RELOC_C6000_ABS_L16, BFD_RELOC_C6000_ABS_H16, BFD_RELOC_C6000_SBR_U15_B, BFD_RELOC_C6000_SBR_U15_H, BFD_RELOC_C6000_SBR_U15_W, BFD_RELOC_C6000_SBR_S16, BFD_RELOC_C6000_SBR_L16_B, BFD_RELOC_C6000_SBR_L16_H, BFD_RELOC_C6000_SBR_L16_W, BFD_RELOC_C6000_SBR_H16_B, BFD_RELOC_C6000_SBR_H16_H, BFD_RELOC_C6000_SBR_H16_W, BFD_RELOC_C6000_SBR_GOT_U15_W, BFD_RELOC_C6000_SBR_GOT_L16_W, BFD_RELOC_C6000_SBR_GOT_H16_W, BFD_RELOC_C6000_DSBT_INDEX, BFD_RELOC_C6000_PREL31, BFD_RELOC_C6000_COPY, BFD_RELOC_C6000_ALIGN, BFD_RELOC_C6000_FPHEAD, BFD_RELOC_C6000_NOCMP): New. * targets.c (bfd_elf32_tic6x_be_vec, bfd_elf32_tic6x_le_vec): New. (_bfd_target_vector): Update. * bfd-in2.h, libbfd.h: Regenerate. binutils: * MAINTAINERS: Add self as TI C6X maintainer. * NEWS: Add news entry for TI C6X support. * readelf.c: Include elf/tic6x.h. (guess_is_rela): Handle EM_TI_C6000. (dump_relocations): Likewise. (get_tic6x_dynamic_type): New. (get_dynamic_type): Call it. (get_machine_flags): Handle EF_C6000_REL. (get_osabi_name): Handle machine-specific values only for relevant machines. Handle C6X values. (get_tic6x_segment_type): New. (get_segment_type): Call it. (get_tic6x_section_type_name): New. (get_section_type_name): Call it. (is_32bit_abs_reloc, is_16bit_abs_reloc, is_none_reloc): Handle EM_TI_C6000. gas: * Makefile.am (TARGET_CPU_CFILES): Add config/tc-tic6x.c. (TARGET_CPU_HFILES): Add config/tc-tic6x.h. * Makefile.in: Regenerate. * NEWS: Add news entry for TI C6X support. * app.c (do_scrub_chars): Handle "\|\|^" for TI C6X. Handle TC_PREDICATE_START_CHAR and TC_PREDICATE_END_CHAR. Keep spaces in operands if TC_KEEP_OPERAND_SPACES. * configure.tgt (tic6x--): New. * config/tc-ia64.h (TC_PREDICATE_START_CHAR, TC_PREDICATE_END_CHAR): Define. * config/tc-tic6x.c, config/tc-tic6x.h: New. * doc/Makefile.am (CPU_DOCS): Add c-tic6x.texi. * doc/Makefile.in: Regenerate. * doc/all.texi (TIC6X): Define. * doc/as.texinfo: Add TI C6X documentation. Include c-tic6x.texi. * doc/c-tic6x.texi: New. gas/testsuite: * gas/tic6x: New directory and testcases. include: * dis-asm.h (print_insn_tic6x): Declare. include/elf: * common.h (ELFOSABI_C6000_ELFABI, ELFOSABI_C6000_LINUX): Define. * tic6x.h: New. include/opcode: * tic6x-control-registers.h, tic6x-insn-formats.h, tic6x-opcode-table.h, tic6x.h: New. ld: * Makefile.am (ALL_EMULATIONS): Add eelf32_tic6x_be.o and eelf32_tic6x_le.o. (eelf32_tic6x_be.c, eelf32_tic6x_le.c): New. * NEWS: Add news entry for TI C6X support. * configure.tgt (tic6x--): New. * emulparams/elf32_tic6x_be.sh, emulparams/elf32_tic6x_le.sh: New. ld/testsuite: * ld-elf/flags1.d, ld-elf/merge.d: XFAIL for tic6x--. * ld-elf/sec-to-seg.exp: Set B_test_same_seg to 0 for tic6x--. * ld-tic6x: New directory and testcases. opcodes: * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c. * Makefile.in: Regenerate. * configure.in (bfd_tic6x_arch): New. * configure: Regenerate. * disassemble.c (ARCH_tic6x): Define if ARCH_all. (disassembler): Handle TI C6X. * tic6x-dis.c: New.	2010-03-25 21:12:36 +00:00
Mike Frysinger	1985c81cf5	Blackfin disassmbler: fix typo where M2.H was decoded as L2.H	2010-03-24 05:16:29 +00:00
Joseph Myers	f66187fdfe	* dis-buf.c (buffer_read_memory): Give error for reading just before the start of memory.	2010-03-23 15:59:45 +00:00
Sebastian Pop	ce7d077ec0	2010-03-22 Sebastian Pop <sebastian.pop@amd.com> Quentin Neill <quentin.neill@amd.com> opcodes/ * i386-dis.c (OP_LWP_I): Removed. (reg_table): Do not use OP_LWP_I, use Iq. (OP_LWPCB_E): Remove use of names16. (OP_LWP_E): Same. * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns should not set the Vex.length bit. * i386-tbl.h: Regenerated. gas/ * testsuite/gas/i386/x86-64-lwp.s: Remove use of 16bit LWP insns. * testsuite/gas/i386/lwp.s: Same. * testsuite/gas/i386/x86-64-lwp.d: Updated. * testsuite/gas/i386/lwp.d: Updated.	2010-03-23 02:56:24 +00:00
Alan Modra	63d0fa4e9e	* ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".	2010-02-25 01:00:13 +00:00
Nick Clifton	c060226ad0	PR binutils/6773 * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with <prefix>asx. Replace <prefix>subaddx with <prefix>sax. (thumb32_opcodes): Likewise. * gas/arm/arch7em.d: Replace expected disassembly of <prefix>addsubx with <prefix>asx. Also replace <prefix>subaddx with <prefix>sax. * gas/arm/archv6.d: Likewise. * gas/arm/thumb32.d: Likewise.	2010-02-24 15:11:44 +00:00
Nick Clifton	ab7875de80	Updated Vietnamese translation.	2010-02-15 10:09:39 +00:00
Doug Evans	fee1d3e815	* lm32-opinst.c: Regenerate.	2010-02-13 04:38:57 +00:00
Doug Evans	9468ae8905	* cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL. (print_address): Delete CGEN_PRINT_ADDRESS. * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c, * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c, * xc16x-dis.c, * xstormy16-dis.c: Regenerate.	2010-02-12 04:42:28 +00:00
Doug Evans	37ec92403b	* fr30-desc.c, * fr30-desc.h, * fr30-opc.c, * frv-desc.c, * frv-desc.h, * frv-opc.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c, * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c, * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c, * m32c-desc.c, * m32c-desc.h, * m32c-opc.c, * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c, * mep-desc.c, * mep-desc.h, * mep-opc.c, * mt-desc.c, * mt-desc.h, * mt-opc.c, * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c, * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c, * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.	2010-02-12 03:25:49 +00:00
H.J. Lu	c75ef631bd	Update copyright. gas/ 2010-02-11 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c: Update copyright. opcodes/ 2010-02-11 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c: Update copyright. * i386-gen.c: Likewise. * i386-opc.h: Likewise. * i386-opc.tbl: Likewise.	2010-02-11 13:41:19 +00:00
Sebastian Pop	a683cc34e4	2010-02-10 Quentin Neill <quentin.neill@amd.com> Sebastian Pop <sebastian.pop@amd.com> gas: * config/tc-i386.c (vec_imm4) New operand type. (fits_in_imm4): New. (VEX_check_operands): New. (check_reverse): Call VEX_check_operands. (build_modrm_byte): Reintroduce code for 5 operand insns. Fix whitespace. gas/testsuite: * gas/i386/x86-64-xop.d: Add vpermil2p[sd] tests. * gas/i386/x86-64-xop.s: Likewise. * gas/i386/xop.d: Likewise. * gas/i386/xop.s: Likewise. opcodes: * i386-dis.c (OP_EX_VexImmW): Reintroduced function to handle 5th imm8 operand. (PREFIX_VEX_3A48): Added. (PREFIX_VEX_3A49): Added. (VEX_W_3A48_P_2): Added. (VEX_W_3A49_P_2): Added. (prefix table): Added entries for PREFIX_VEX_3A48 and PREFIX_VEX_3A49. (vex table): Added entries for VEX_W_3A48_P_2 and and VEX_W_3A49_P_2. * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4 for Vec_Imm4 operands. * i386-opc.h (enum): Added Vec_Imm4. (i386_operand_type): Added vec_imm4. * i386-opc.tbl: Add entries for vpermilp[ds]. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.	2010-02-11 05:06:14 +00:00
Richard Sandiford	cdc51b0748	gas/ * config/tc-ppc.c (md_show_usage): Add -mpwr4, -mpwr5, -mpwr5x, -mpwr6 and -mpwr7. opcodes/ * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6" and "pwr7". Move "a2" into alphabetical order.	2010-02-10 19:59:07 +00:00
Alan Modra	ce3d2015b2	include/ * opcode/ppc.h (PPC_OPCODE_TITAN): Define. bfd/ * archures.c (bfd_mach_ppc_titan): Define. * bfd-in2.h: Regenerate. * cpu-powerpc.c (bfd_powerpc_archs): Add titan entry. opcodes/ * ppc-dis.c (ppc_opts): Add titan entry. * ppc-opc.c (TITAN, MULHW): Define. (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx). gas/ * config/tc-ppc.c (md_show_usage): Mention -mtitan. Don't use tabs. (ppc_mach): Handle titan. * doc/c-ppc.texi: Mention -mtitan. gas/testsuite/ * gas/ppc/titan.d, * gas/ppc/titan.s: New test. * gas/ppc/ppc.exp: Run it.	2010-02-08 01:59:38 +00:00
Sebastian Pop	68339fdf88	2010-02-03 Quentin Neill <quentin.neill@amd.com> gas/ * config/tc-i386.c (cpu_arch): Change amdfam15 to bdver1. (i386_align_code): Rename PROCESSOR_AMDFAM15 to PROCESSOR_BDVER1. * config/tc-i386.h (processor_type): Same. * doc/c-i386.texi: Change amdfam15 to bdver1. opcodes/ * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS to CPU_BDVER1_FLAGS * i386-init.h: Regenerated. testsuite/ * gas/i386/i386.exp: Rename amdfam15 test cases to bdver1. * gas/i386/x86-64-nops-1-amdfam15.d: Renamed test case to gas/i386/x86-64-nops-1-bdver1.d. * gas/i386/nops-1-amdfam15.d: Renamed test case to gas/i386/nops-1-bdver1.d.	2010-02-03 20:36:14 +00:00
Anthony Green	f3d55a94f3	Move NOP from 0x00 to 0x0f.	2010-02-03 12:47:06 +00:00
Daniel Jacobowitz	b0e28b39b7	gas/testsuite/ * gas/arm/dis-data.d: Update test name. Do not expect .word output. * gas/arm/dis-data2.d, gas/arm/dis-data2.s, gas/arm/dis-data3.d, gas/arm/dis-data3.s: New tests. opcodes/ * opcodes/arm-dis.c (struct arm_private_data): New. (print_insn_coprocessor, print_insn_arm): Update to use struct arm_private_data. (is_mapping_symbol, get_map_sym_type): New functions. (get_sym_code_type): Check the symbol's section. Do not check mapping symbols. (print_insn): Default to disassembling ARM mode code. Check for mapping symbols separately from other symbols. Use struct arm_private_data.	2010-01-29 16:47:55 +00:00
H.J. Lu	1c4809636b	Allow VL=1 on scalar FMA instructions. gas/testsuite/ 2010-01-28 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/fma-scalar-intel.d: New. * gas/i386/fma-scalar.d: Likewise. * gas/i386/fma-scalar.s: Likewise. * gas/i386/x86-64-fma-scalar-intel.d: Likewise. * gas/i386/x86-64-fma-scalar.d: Likewise. * gas/i386/x86-64-fma-scalar.s: Likewise. * gas/i386/i386.exp: Run fma-scalar, fma-scalar-intel, x86-64-fma-scalar and x86-64-fma-scalar-intel. opcodes/ 2010-01-28 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (EXVexWdqScalar): New. (vex_scalar_w_dq_mode): Likewise. (prefix_table): Update entries for PREFIX_VEX_3899, PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F, PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD, PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB, PREFIX_VEX_38BD and PREFIX_VEX_38BF. (intel_operand_size): Handle vex_scalar_w_dq_mode. (OP_EX): Likewise.	2010-01-28 15:33:23 +00:00
H.J. Lu	539f890d01	Allow VL=1 on AVX scalar instructions. gas/ 2010-01-27 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (avxscalar): New. (OPTION_MAVXSCALAR): Likewise. (build_vex_prefix): Select vector_length for scalar instructions based on avxscalar. (md_longopts): Add OPTION_MAVXSCALAR. (md_parse_option): Handle OPTION_MAVXSCALAR. (md_show_usage): Add -mavxscalar=. * doc/c-i386.texi: Document -mavxscalar=. gas/testsuite/ 2010-01-27 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/avx-scalar-intel.d: New. * gas/i386/avx-scalar.d: Likewise. * gas/i386/avx-scalar.s: Likewise. * gas/i386/x86-64-avx-scalar-intel.d: Likewise. * gas/i386/x86-64-avx-scalar.d: Likewise. * gas/i386/x86-64-avx-scalar.s: Likewise. * gas/i386/i386.exp: Run avx-scalar, avx-scalar-intel, x86-64-avx-scalar and x86-64-avx-scalar-intel. opcodes/ 2010-01-27 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (XMScalar): New. (EXdScalar): Likewise. (EXqScalar): Likewise. (EXqScalarS): Likewise. (VexScalar): Likewise. (EXdVexScalarS): Likewise. (EXqVexScalarS): Likewise. (XMVexScalar): Likewise. (scalar_mode): Likewise. (d_scalar_mode): Likewise. (d_scalar_swap_mode): Likewise. (q_scalar_mode): Likewise. (q_scalar_swap_mode): Likewise. (vex_scalar_mode): Likewise. (vex_len_table): Duplcate entries for VEX_LEN_10_P_1, VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1, VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0, VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3, VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3, VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1, VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1, VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2, VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1, VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2. (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3, VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2, VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3, VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3, VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3, VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3, VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3, VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3, VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2. (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode, q_scalar_swap_mode. (OP_XMM): Handle scalar_mode. (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode and q_scalar_swap_mode. (OP_VEX): Handle vex_scalar_mode.	2010-01-27 14:34:40 +00:00
H.J. Lu	208b4d786e	Remove trailing { Bad_Opcode }.	2010-01-24 23:22:43 +00:00
H.J. Lu	448b213a86	Remove trailing { Bad_Opcode } in vex_len_table. 2010-01-24 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.	2010-01-24 21:35:13 +00:00
H.J. Lu	47cf8fa043	Remove trailing { Bad_Opcode }. 2010-01-24 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.	2010-01-24 20:39:40 +00:00
H.J. Lu	592d1631a4	Remove trailing "(bad)" entries and replace { "(bad)", { XX } } with { Bad_Opcode }. 2010-01-24 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (Bad_Opcode): New. (bad_opcode): Likewise. (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }. (dis386_twobyte): Likewise. (reg_table): Likewise. (prefix_table): Likewise. (x86_64_table): Likewise. (vex_len_table): Likewise. (vex_w_table): Likewise. (mod_table): Likewise. (rm_table): Likewise. (float_reg): Likewise. (reg_table): Remove trailing "(bad)" entries. (prefix_table): Likewise. (x86_64_table): Likewise. (vex_len_table): Likewise. (vex_w_table): Likewise. (mod_table): Likewise. (rm_table): Likewise. (get_valid_dis386): Handle bytemode 0.	2010-01-24 18:24:23 +00:00
H.J. Lu	712366da0a	Replace "Vex" with "Vex=3" on AVX scalar instructions. 2010-01-23 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h (VEXScalar): New. * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar instructions. * i386-tbl.h: Regenerated.	2010-01-24 00:59:13 +00:00
H.J. Lu	706e820514	Correct month.	2010-01-21 17:32:32 +00:00
H.J. Lu	73bb672904	Add xsave64 and xrstor64. gas/testsuite/ 2010-02-21 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/x86-64-xsave.s: Add tests for xsave64 and xrstor64. * gas/i386/x86-64-xsave-intel.d: Updated. * gas/i386/x86-64-xsave.d: Likewise. opcodes/ 2010-02-21 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor. * i386-opc.tbl: Add xsave64 and xrstor64. * i386-tbl.h: Regenerated.	2010-01-21 17:30:14 +00:00
Nick Clifton	99ea83aac3	PR 11170 * arm-dis.c (print_arm_address): Do not ignore negative bit in PC based post-indexed addressing.	2010-01-20 10:54:03 +00:00
Sebastian Pop	a6461c0251	2010-01-15 Sebastian Pop <sebastian.pop@amd.com> gas/ * config/tc-i386.c (md_assemble): Before accessing the IMM field check that it's not an XOP insn. gas/testsuite/ * gas/i386/x86-64-xop.d: Add missing patterns. * gas/i386/x86-64-xop.s: Same. * gas/i386/xop.d: Same. * gas/i386/xop.s: Same. opcodes/ * i386-opc.tbl: Support all the possible aliases for VPCOM* insns. * i386-tbl.h: Regenerated.	2010-01-15 21:24:13 +00:00
H.J. Lu	a2a7d12cfc	Replace VEX.DNS with VEX.NDS in comments. 2010-01-14 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in comments.	2010-01-14 19:35:36 +00:00
H.J. Lu	b9733481ab	Add names_mm, names_xmm and names_ymm. 2010-01-14 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (names_mm): New. (intel_names_mm): Likewise. (att_names_mm): Likewise. (names_xmm): Likewise. (intel_names_xmm): Likewise. (att_names_xmm): Likewise. (names_ymm): Likewise. (intel_names_ymm): Likewise. (att_names_ymm): Likewise. (print_insn): Set names_mm, names_xmm and names_ymm. (OP_MMX): Use names_mm, names_xmm and names_ymm. (OP_XMM): Likewise. (OP_EM): Likewise. (OP_EMC): Likewise. (OP_MXC): Likewise. (OP_EX): Likewise. (XMM_Fixup): Likewise. (OP_VEX): Likewise. (OP_EX_VexReg): Likewise. (OP_Vex_2src): Likewise. (OP_Vex_2src_1): Likewise. (OP_Vex_2src_2): Likewise. (OP_REG_VexI4): Likewise.	2010-01-14 17:29:18 +00:00
H.J. Lu	5e6718e49c	Update comments 2010-01-13 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (print_insn): Update comments.	2010-01-13 16:06:12 +00:00
H.J. Lu	d869730db3	Remove rex_original 2010-01-12 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (rex_original): Removed. (ckprefix): Remove rex_original. (print_insn): Update comments.	2010-01-13 04:03:20 +00:00
Ralf Wildenhues	3725885a65	Sync Libtool from GCC. /: * libtool.m4: Sync from git Libtool. * ltmain.sh: Likewise. * ltoptions.m4: Likewise. * ltversion.m4: Likewise. * lt~obsolete.m4: Likewise. sim/iq2000/: * configure: Regenerate. sim/d10v/: * configure: Regenerate. sim/m32r/: * configure: Regenerate. sim/frv/: * configure: Regenerate. sim/: * avr/configure: Regenerate. * cris/configure: Regenerate. * microblaze/configure: Regenerate. sim/h8300/: * configure: Regenerate. sim/mn10300/: * configure: Regenerate. sim/erc32/: * configure: Regenerate. sim/arm/: * configure: Regenerate. sim/m68hc11/: * configure: Regenerate. sim/lm32/: * configure: Regenerate. sim/sh64/: * configure: Regenerate. sim/v850/: * configure: Regenerate. sim/cr16/: * configure: Regenerate. sim/moxie/: * configure: Regenerate. sim/m32c/: * configure: Regenerate. sim/mips/: * configure: Regenerate. sim/mcore/: * configure: Regenerate. sim/sh/: * configure: Regenerate. gprof/: * Makefile.in: Regenerate. * configure: Regenerate. opcodes/: * Makefile.in: Regenerate. * configure: Regenerate. gas/: * Makefile.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. ld/: * configure: Regenerate. gdb/testsuite/: * gdb.cell/configure: Regenerate. binutils/: * Makefile.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. bfd/: * Makefile.in: Regenerate. * configure: Regenerate. bfd/doc/: * Makefile.in: Regenerate.	2010-01-09 21:11:44 +00:00
Doug Evans	b7cd1872af	* cgen-ibld.in (insert_normal, extract_normal): Minor cleanup. * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.	2010-01-07 18:05:45 +00:00
Sebastian Pop	69dd98654a	2010-01-06 Quentin Neill <quentin.neill@amd.com> gas/ * config/tc-i386.c (cpu_arch): Add amdfam15. (i386_align_code): Add PROCESSOR_AMDFAM15 cases. * config/tc-i386.h (processor_type): Add PROCESSOR_AMDFAM15. * doc/c-i386.texi: Add amdfam15. opcodes/ * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS. * i386-init.h: Regenerated. testsuite/ * gas/i386/i386.exp: Add new amdfam15 test cases. * gas/i386/nops-1-amdfam15.d: New.	2010-01-06 22:52:47 +00:00
Nick Clifton	e3e535bc58	* arm-dis.c (print_insn): Fixed search for next symbol and data dumping condition, and the initial mapping symbol state. * gas/arm/dis-data.d: New test case. * gas/arm/dis-data.s: New file.	2010-01-06 15:02:45 +00:00
Doug Evans	fe8afbc48f	cpu/ * m32c.cpu (f-dsp-32-u24): Fix mode of extract handler. (f-dsp-40-u20, f-dsp-40-u24): Ditto. opcodes/ * cgen-ibld.in: #include "cgen/basic-modes.h". * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.	2010-01-06 05:30:19 +00:00
Nick Clifton	2edcd24424	PR 11123 * arm-dis.c (print_insn_coprocessor): Initialise value.	2010-01-04 10:18:32 +00:00
Alan Modra	0dc9305793	bfd/ * archures.c: Add bfd_mach_ppc_e500mc64. * bfd-in2.h: Regenerate. * cpu-powerpc.c (bfd_powerpc_archs): Add entry for bfd_mach_ppc_e500mc64. gas/ * config/tc-ppc.c (md_show_usage): Document -me500mc64. opcodes/ * ppc-dis.c (ppc_opts): Add entry for "e500mc64".	2010-01-04 02:32:56 +00:00
Doug Evans	05994f45db	* cgen-asm.in: Update copyright year. * cgen-dis.in: Update copyright year. * cgen-ibld.in: Update copyright year. * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c, * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c, * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h, * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c, * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c, * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c, * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c, * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h, * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h, * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c, * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c, * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c, * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h, * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c, * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c, * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c, * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c, * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c, * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c, * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.	2010-01-02 18:50:59 +00:00
H.J. Lu	43ecc30f09	Move 2009 binutils ChangeLog to ChangeLog-2009.	2010-01-01 18:06:10 +00:00
H.J. Lu	2426c15ff8	Replace VexNDS, VexNDD and VexLWP with VexVVVV. gas/ 2009-12-19 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_operands): Check vexvvvv instead of vexnds and vexndd. (build_modrm_byte): Check vexvvvv instead of vexnds, vexndd and vexlwp. opcodes/ 2009-12-19 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove VexNDS, VexNDD and VexLWP. Add VexVVVV. * i386-opc.h (VexNDS): Removed. (VexNDD): Likewise. (VexLWP): Likewise. (VEXXDS): New. (VEXNDD): Likewise. (VEXLWP): Likewise. (VexVVVV): Likewise. (i386_opcode_modifier): Remove vexnds, vexndd and vexlwp. Add vexvvvv. * i386-opc.tbl: Replace VexNDS with VexVVVV=1, VexNDD with VexVVVV=2 and VexLWP with VexVVVV=3. * i386-tbl.h: Regenerated.	2009-12-19 18:36:27 +00:00
H.J. Lu	94ff3a50d8	Move Imm1 before Imm8. 2009-12-18 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (operand_types): Move Imm1 before Imm8.	2009-12-18 21:07:58 +00:00
Nick Clifton	ff4a8d2b93	PR binutils/10924 * config/tc-arm.c (do_ldstv4): Do not allow r15 as the destination register. (do_mrs): Likewise. (do_mul): Likewise. * arm-dis.c: Add support for %<>ru and %<>rU formats to enforce unique register numbers. Extend support for %<>R format to thumb32 and coprocessor instructions. * gas/arm/unpredictable.s: Add more unpredictable instructions. * gas/arm/unpredictable.d: Add expected disassemblies.	2009-12-17 09:52:18 +00:00
H.J. Lu	2eb952a4d9	Remove ByteOkIntel. gas/ 2009-12-16 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_suffix): Set i.suffix to 0 in Intel syntax if size is ignored and b/l/w suffixes are illegal. (check_byte_reg): Remove byteokintel check. opcodes/ 2009-12-16 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove ByteOkIntel. * i386-opc.h (ByteOkIntel): Removed. (i386_opcode_modifier): Remove byteokintel. * i386-opc.tbl: Remove ByteOkIntel. * i386-tbl.h: Regenerated.	2009-12-16 20:08:32 +00:00
H.J. Lu	7f399153c6	Replace Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A with VexOpcode. gas/ 2009-12-16 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_vex_prefix): Replace vex0f, vex0f38, vex0f3a, xop08, xop09 and xop0a with vexopcode. opcodes/ 2009-12-16 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove Vex0F, Vex0F38, Vex0F3A, XOP08, XOP09 and XOP0A. Add VexOpcode. * i386-opc.h (Vex0F): Removed. (Vex0F38): Likewise. (Vex0F3A): Likewise. (VexOpcode): New. (VEX0F): Likewise. (VEX0F38): Likewise. (VEX0F3A): Likewise. (XOP08): Defined as a macro. (XOP09): Likewise. (XOP0A): Likewise. (i386_opcode_modifier): Remove vex0f, vex0f38, vex0f3a, xop08, xop09 and xop0a. Add vexopcode. * i386-opc.tbl: Replace Vex0F with VexOpcode=0, Vex0F38 with VexOpcode=1, Vex0F3A with VexOpcode=2, XOP08 with VexOpcode=3, XOP09 with VexOpcode=4 and XOP0A with VexOpcode=5. * i386-tbl.h: Regenerated.	2009-12-16 15:43:16 +00:00
H.J. Lu	25ac7f26dd	Fix a typo in ChangeLog.	2009-12-16 05:31:40 +00:00
H.J. Lu	8c43a48b28	Replace VEX2SOURCES with XOP2SOURCES. gas/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_modrm_byte): Check XOP2SOURCES instead VEX2SOURCES. opcodes/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h (VEX2SOURCES): Renamed to ... (XOP2SOURCES): This.	2009-12-16 05:18:11 +00:00
H.J. Lu	8cd7925b45	Replace Vex2Sources and Vex3Sources with VexSources. gas/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_operands): Check vexsources instead of vex3sources. (build_modrm_byte): Check vexsources instead of vex2sources and vex3sources. opcodes/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove Vex3Sources and Vex2Sources. Add VexSources. * i386-opc.h ()Vex2Sources: Removed. (Vex3Sources): Likewise. (VEX2SOURCES): New. (VEX3SOURCES): Likewise. (VexSources): Likewise. (i386_opcode_modifier): Remove vex2sources and vex3sources. Add vexsources. * i386-opc.tbl: Replace Vex2Sources with VexSources=1 and Vex3Sourceswith VexSources=2. * i386-tbl.h: Regenerated.	2009-12-16 04:00:35 +00:00
H.J. Lu	1ef99a7be9	Remove VexW0 and VexW1. Add VexW. gas/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_vex_prefix): Replace vexw0/vexw1 with vexw. (build_modrm_byte): Likewise. opcodes/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove VexW0 and VexW1. Add VexW. * i386-opc.h (VexW0): Removed. (VexW1): Likewise. (VEXW0): New. (VEXW1): Likewise. (VexW): Likewise. (i386_opcode_modifier): Remove vexw0 and vexw1. Add vexw. * i386-opc.tbl: Replace VexW0 with VexW=1 and VexW1 with Vex=2. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	2009-12-16 02:10:45 +00:00
H.J. Lu	bcf2684fb0	Add VEX_W_3818_P_2_M_0. 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (VEX_W_3818_P_2_M_0): New. (vex_w_table): Add VEX_W_3818_P_2_M_0. (mod_table): Use VEX_W_3818_P_2_M_0.	2009-12-15 23:33:51 +00:00
H.J. Lu	a179a9fdaa	Reformat vex_w_table. 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (vex_w_table): Reformat.	2009-12-15 22:20:50 +00:00
H.J. Lu	53aa04a0be	Add VEX_W_382X_P_2_M_0. 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (VEX_W_382X_P_2_M_0): New. (vex_w_table): Add VEX_W_382X_P_2_M_0. (mod_table): Use VEX_W_382X_P_2_M_0.	2009-12-15 22:13:05 +00:00
H.J. Lu	efdb52b70e	Reformat vex_w_table. 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (vex_w_table): Reformat.	2009-12-15 21:37:51 +00:00
H.J. Lu	9e30b8e093	Add USE_VEX_W_TABLE, VEX_W_TABLE and VEX_W_XXX. 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (USE_VEX_W_TABLE): New. (VEX_W_TABLE): Likewise. (VEX_W_XXX): Likewise. (vex_w_table): Likewise. (prefix_table): Use VEX_W_XXX. (vex_table): Likewise. (vex_len_table): Likewise. (mod_table): Likewise. (get_valid_dis386): Handle USE_VEX_W_TABLE. * i386-opc.tbl: Add VexW0 to AVX instructions where the VEX.W bit isn't used. * i386-tbl.h: Regenerated.	2009-12-15 18:56:09 +00:00
H.J. Lu	e3c58833bf	Define VEX128 and VEX256. gas/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_vex_prefix): Use VEX256. opcodes/ 2009-12-15 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h (VEX128): New. (VEX256): Likewise.	2009-12-15 16:36:59 +00:00
H.J. Lu	4c807e7262	Reformat vex_len_table. 2009-12-14 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (vex_len_table): Reformat.	2009-12-15 01:42:57 +00:00
H.J. Lu	976f1fde11	Rename MOD_VEX_51 to MOD_VEX_50. 2009-12-14 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (MOD_VEX_51): Renamed to ... (MOD_VEX_50): This. (vex_table): Updated. (mod_table): Likewise.	2009-12-14 20:22:16 +00:00
Nick Clifton	ab8e2090b6	PR binutils/10924 * arm-dis.c (arm_opcodes): Specify %R in cases where using r15 results in unpredictable behaviour. (print_insn_arm): Handle %R. * gas/arm/unpredictable.s: New test case - checks the disassembly of instructions with unpredictable behaviour. * gas/arm/unpredictable.d: New file - expected disassembly.	2009-12-14 16:38:23 +00:00
H.J. Lu	759a05ce24	Set vex.w to 0 for VEX C5 prefix. 2009-12-11 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (get_valid_dis386): Set vex.w to 0 for VEX C5 prefix. (print_insn): Don't set vex.w here.	2009-12-12 01:17:41 +00:00
H.J. Lu	5639ff8726	2009-12-11 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (print_insn): Set vex.w to 0.	2009-12-12 00:13:11 +00:00
Sebastian Pop	02e647f941	2009-12-11 Quentin Neill <quentin.neill@amd.com> gas/testsuite/ * gas/i386/fma4.d: Add test cases. * gas/i386/fma4.s: Add test cases. * gas/i386/x86-64-fma4.d: Add test cases. * gas/i386/x86-64-fma4.s: Add test cases. opcodes/ * i386-dis.c (get_vex_imm8): Extend logic to apply in all cases, to avoid fetching ahead for the immediate bytes when OP_E_memory has already been called. Fix indentation.	2009-12-11 20:38:51 +00:00
Nick Clifton	91d6fa6a03	Add -Wshadow to the gcc command line options used when compiling the binutils. Fix up all warnings generated by the addition of this switch.	2009-12-11 13:42:17 +00:00
Nick Clifton	07a28fab11	PR 10924 * arm-dis.c (print_insn_arm): Mark insns that use the PC in post-indexed addressing as unpredictable.	2009-12-09 08:38:04 +00:00
H.J. Lu	eacc9c891d	Support fxsave64 and fxrstor64. gas/testsuite/ 2009-12-03 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run x86-64-fxsave and x86-64-fxsave-intel. * gas/i386/rex.d: Updated for fxsave64. * gas/i386/x86-64-fxsave-intel.d: New. * gas/i386/x86-64-fxsave.d: Likewise. * gas/i386/x86-64-fxsave.s: Likewise. opcodes/ 2009-12-03 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (FXSAVE_Fixup): New. (FXSAVE): Likewise. (mod_table): Use FXSAVE on fxsave and fxrstor. * i386-opc.tbl: Add fxsave64 and fxrstor64. * i386-tbl.h: Regenerated.	2009-12-04 07:51:41 +00:00
Nick Clifton	03ee1b7f8e	PR gas/11013 * arm-dis.c (thumb32_opc): Adjust disassembly of QADD, QDADD, QSUB and QDSUB. * gas/arm/arch7em.d: Update expected disassembly. * gas/arm/thumb32.d: Likewise. * config/tc-arm.c (do_t_simd2): New function. (insns): Use do_t_simd2 for QADD, QDADD, QSUB and QDSUB.	2009-12-02 20:26:30 +00:00
Nick Clifton	ee9fd255b7	PR gas/11030 * m68k-opc.c (m68k_opcodes): Allow the STLDSR instruction on the Coldfire ISA A+.	2009-11-30 14:45:30 +00:00
Sebastian Pop	ccc5981b93	2009-11-17 Quentin Neill <quentin.neill@amd.com> Sebastian Pop <sebastian.pop@amd.com> gas/testsuite/ * gas/i386/x86-64-fma4.d: Add new patterns. * gas/i386/x86-64-fma4.s: Same. * gas/i386/x86-64-xop.d: Adjusted. opcodes/ * i386-dis.c (get_vex_imm8): Increase bytes_before_imm when decoding the second source operand from the immediate byte. (OP_EX_VexW): Pass an extra integer to identify the second and third source arguments.	2009-11-25 15:15:30 +00:00
H.J. Lu	18d0c96eb9	Allow lock on cmpxch16b. gas/testsuite/ 2009-11-19 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/lock-1.s: Add cmpxchg16b test. * gas/i386/lock-1-intel.d: Updated. * gas/i386/lock-1.d: Likewise. opcodes/ 2009-11-19 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add IsLockable to cmpxch16b. * i386-tbl.h: Regenerated.	2009-11-19 15:26:42 +00:00
Nick Clifton	945ee43039	PR binutils/10924 * gas/arm/arch4t-eabi.d: Restore previous expected dissambly of instructions using Immediate Offset addressing with an offset of zero. * gas/arm/arch4t.d: Likewise. * gas/arm/arm7t.d: Likewise. * gas/arm/xscale.d: Likewise. * gas/arm/wince-inst.d: Remove 'p' suffix from cmp, cmn, teq and tst instructions. PR binutils/10924 * arm-dis.c (print_insn_arm): Do not print an offset of zero when decoding Immediaate Offset addressing.	2009-11-19 14:07:11 +00:00
Sebastian Pop	41effecb2d	2009-11-18 Sebastian Pop <sebastian.pop@amd.com> opcodes/ PR binutils/10973 * i386-dis.c (get_vex_imm8): Do not increment codep. Avoid incrementing bytes_before_imm when OP_E_memory has already forwarded the codep pointer. (OP_EX_VexW): Increment codep to skip mod/rm byte. gas/testsuite/ * gas/i386/x86-64-xop.d: Update patterns.	2009-11-19 07:08:39 +00:00
Sebastian Pop	f0ae4a24b0	2009-11-18 Sebastian Pop <sebastian.pop@amd.com> gas/ * config/tc-i386.c (cpu_arch): Remove cvt16. (md_show_usage): Same. * doc/c-i386.texi: Same. gas/testsuite/ * gas/i386/cvt16.d: Removed. * gas/i386/cvt16.s: Removed. * gas/i386/x86-64-cvt16.d: Removed. * gas/i386/x86-64-cvt16.s: Removed. * gas/i386/i386.exp: Remove cvt16 and x86-64-cvt16 tests. opcodes/ * i386-dis.c (VEX_LEN_XOP_08_A0): Removed. (VEX_LEN_XOP_08_A1): Removed. (xop_table): Remove entries for VEX_LEN_XOP_08_A0 and VEX_LEN_XOP_08_A1. (vex_len_table): Same. * i386-gen.c (CPU_CVT16_FLAGS): Removed. (cpu_flags): Remove field for CpuCVT16. * i386-opc.h (CpuCVT16): Removed. (i386_cpu_flags): Remove bitfield cpucvt16. (i386-opc.tbl): Remove CVT16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.	2009-11-18 20:28:59 +00:00
Sebastian Pop	5dd85c9970	2009-11-17 Sebastian Pop <sebastian.pop@amd.com> Quentin Neill <quentin.neill@amd.com> gas/ * config/tc-i386.c (cpu_arch): Added .xop and .cvt16. (build_vex_prefix): Handle xop08. (md_assemble): Don't special case the constant 3 for insns using MODRM. (build_modrm_byte): Handle vex2sources. (md_show_usage): Add xop and cvt16. * doc/c-i386.texi: Document fma4, xop, and cvt16. gas/testsuite/ * gas/i386/i386.exp: Run xop and cvt16 in 32-bit mode. Run x86-64-xop and x86-64-cvt16 in 64-bit mode. * gas/i386/lwp.d: Update name of the testcase. * gas/i386/x86-64-xop.d: New. * gas/i386/x86-64-xop.s: New. * gas/i386/xop.d: New. * gas/i386/xop.s: New. * gas/i386/cvt16.d: New. * gas/i386/cvt16.s: New. opcodes/ * i386-dis.c (OP_Vex_2src_1): New. (OP_Vex_2src_2): New. (Vex_2src_1): New. (Vex_2src_2): New. (XOP_08): Added. (VEX_LEN_XOP_08_A0): Added. (VEX_LEN_XOP_08_A1): Added. (VEX_LEN_XOP_09_80): Added. (VEX_LEN_XOP_09_81): Added. (xop_table): Added an entry for XOP_08. Handle xop instructions. (vex_len_table): Added entries for VEX_LEN_XOP_08_A0, VEX_LEN_XOP_08_A1, VEX_LEN_XOP_09_80, VEX_LEN_XOP_09_81. (get_valid_dis386): Handle XOP_08. (OP_Vex_2src): New. * i386-gen.c (cpu_flag_init): Add CPU_XOP_FLAGS and CPU_CVT16_FLAGS. (cpu_flags): Add CpuXOP and CpuCVT16. (opcode_modifiers): Add XOP08, Vex2Sources. * i386-opc.h (CpuXOP): Added. (CpuCVT16): Added. (i386_cpu_flags): Add cpuxop and cpucvt16. (XOP08): Added. (Vex2Sources): Added. (i386_opcode_modifier): Add xop08, vex2sources. * i386-opc.tbl: Add entries for XOP and CVT16 instructions. * i386-init.h: Regenerated. * i386-tbl.h: Regenerated.	2009-11-18 04:04:17 +00:00
Nick Clifton	aefd8a406c	* gas/arm/vfma1.d: Only run on ELF based targets. PR binutils/10924 * gas/arm/arch4t-eabi.d: Update expected disassembly. * gas/arm/arch4t.d: Likewise. * gas/arm/archv6t2.d: Likewise. * gas/arm/arm7t.d: Likewise. * gas/arm/inst.d: Likewise. * gas/arm/xscale.d: Likewise. PR binutils/10924 * arm-dis.c (arm_opcodes): Add patterns to match undefined LDRB instruction variants. Add pattern for MRS variant that was being confused with CMP. (arm_decode_shift): Place error message in a comment. (print_insn_arm): Note that writing back to the PC is unpredictable. Only print 'p' variants of cmp/cmn/teq/tst instructions if decoding for pre-V6 architectures.	2009-11-17 17:20:26 +00:00
Ramana Radhakrishnan	0bb027fd62	2009-11-17 Edward Nevill <edward.nevill@arm.com> * arm-dis.c (print_insn_thumb32): Handle undefined instruction.	2009-11-17 10:43:09 +00:00
Doug Evans	c7e770a030	opcodes/ * Makefile.am (stamp-xc16x): Use ../cpu/xc16x.cpu instead of ../cgen/cpu. * Makefile.in: Regenerate. cgen/ * cpu/xc16x.cpu: Delete, use copy in ../cpu. * cpu/xc16x.opc: Ditto.	2009-11-14 20:04:58 +00:00
H.J. Lu	8b3f93e7a1	2009-11-13 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_E_extended): Removed.	2009-11-14 07:22:05 +00:00
H.J. Lu	2a70cca486	Check rex_ignored. gas/testsuite/ 2009-11-13 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/rex.s: Add a test for VEX insn. * gas/i386/rex.d: Updated. opcodes/ 2009-11-13 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (print_insn): Check rex_ignored.	2009-11-13 23:13:48 +00:00
H.J. Lu	f16cd0d502	Rewrite prefix processing. gas/testsuite/ 2009-11-13 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run long-1, long-1-intel, x86-64-long-1, and x86-64-long-1-intel. * gas/i386/long-1-intel.d: New. * gas/i386/long-1.d: Likewise. * gas/i386/long-1.s: Likewise. * gas/i386/x86-64-long-1-intel.d: Likewise. * gas/i386/x86-64-long-1.d: Likewise. * gas/i386/x86-64-long-1.s: Likewise. * gas/i386/jump16.d: Updated for prefix processing. * gas/i386/naked.d: Likewise. * gas/i386/nops-1-core2.d: Likewise. * gas/i386/nops-1-i686.d: Likewise. * gas/i386/nops-3-i686.d: Likewise. * gas/i386/nops-4-i686.d: Likewise. * gas/i386/nops-5-i686.d: Likewise. * gas/i386/nops-5.d: Likewise. * gas/i386/prefix.d: Likewise. * gas/i386/rep.d: Likewise. * gas/i386/string-ok.d: Likewise. * gas/i386/x86-64-addr32-intel.d: Likewise. * gas/i386/x86-64-addr32.d: Likewise. * gas/i386/x86-64-cbw-intel.d: Likewise. * gas/i386/x86-64-cbw.d: Likewise. * gas/i386/x86-64-io-intel.d: Likewise. * gas/i386/x86-64-io-suffix.d: Likewise. * gas/i386/x86-64-io.d: Likewise. * gas/i386/x86-64-lwp.d: Likewise. * gas/i386/x86-64-nops-1-core2.d: Likewise. * gas/i386/x86-64-nops-1-nocona.d: Likewise. * gas/i386/x86-64-nops-1.d: Likewise. * gas/i386/x86-64-nops-2.d: Likewise. * gas/i386/x86-64-nops-3.d: Likewise. * gas/i386/x86-64-nops-4-core2.d: Likewise. * gas/i386/x86-64-nops-4.d: Likewise. * gas/i386/x86-64-nops-5-k8.d: Likewise. * gas/i386/x86-64-nops-5.d: Likewise. * gas/i386/x86-64-rep.d: Likewise. * gas/i386/x86-64-stack-intel.d: Likewise. * gas/i386/x86-64-stack-suffix.d: Likewise. * gas/i386/x86-64-stack.d: Likewise. ld/testsuite/ 2009-11-13 H.J. Lu <hongjiu.lu@intel.com> * ld-x86-64/tlsbin.dd: Updated for prefix processing. * ld-x86-64/tlsgdesc.dd: Likewise. * ld-x86-64/tlsld1.dd: Likewise. * ld-x86-64/tlspic.dd: Likewise. opcodes/ 2009-11-13 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (ckprefix): Updated to return 0 if number of prefixes > 14 and record the last position for each prefix. (lock_prefix): Removed. (data_prefix): Likewise. (addr_prefix): Likewise. (repz_prefix): Likewise. (repnz_prefix): Likewise. (last_lock_prefix): New. (last_repz_prefix): Likewise. (last_repnz_prefix): Likewise. (last_data_prefix): Likewise. (last_addr_prefix): Likewise. (last_rex_prefix): Likewise. (last_seg_prefix): Likewise. (MAX_CODE_LENGTH): Likewise. (ADDR16_PREFIX): Likewise. (ADDR32_PREFIX): Likewise. (DATA16_PREFIX): Likewise. (DATA32_PREFIX): Likewise. (REP_PREFIX): Likewise. (seg_prefix): Likewise. (all_prefixes): Change size to MAX_CODE_LENGTH - 1. (prefix_name): Handle ADDR16_PREFIX, ADDR32_PREFIX, DATA16_PREFIX, DATA32_PREFIX and REP_PREFIX. (get_valid_dis386): Updated. (OP_C): Likewise. (OP_Monitor): Likewise. (REP_Fixup): Likewise. (print_insn): Display all prefixes. (putop): Set PREFIX_DATA on used_prefixes only if it is used. (intel_operand_size): Likewise. (OP_E_register): Likewise. (OP_G): Likewise. (OP_REG): Likewise. (OP_IMREG): Likewise. (OP_I): Likewise. (OP_I64): Likewise. (OP_sI): Likewise. (CRC32_Fixup): Likewise. (MOVBE_Fixup): Likewise. (OP_E_memory): Set REFIX_DATA on used_prefixes when it is used in 16bit mode. (OP_J): Set REX_W used if it is used. Set PREFIX_DATA on used_prefixes only if it is used.	2009-11-13 20:42:10 +00:00
H.J. Lu	20efc68957	2009-11-12 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Remove IsLockable from add, adc, and, dec, inc, or, sbb, sub, xor and xchg with register only operands. * i386-tbl.h: Regenerated.	2009-11-12 19:15:18 +00:00
H.J. Lu	c32fa91d70	gas/ 2009-11-12 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (LOCKREP_PREFIX): Removed. (REP_PREFIX): New. (LOCK_PREFIX): Likewise. (PREFIX_GROUP): Likewise. (REX_PREFIX): Updated. (MAX_PREFIXES): Likewise. (add_prefix): Updated. Return enum PREFIX_GROUP. (md_assemble): Check for lock without a lockable instruction. (parse_insn): Updated. (output_insn): Likewise. gas/testsuite/ 2009-11-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run lock-1, lock-1-intel, lockbad-1, x86-64-lock-1, x86-64-lock-1-intel and x86-64-lockbad-1. * gas/i386/lock-1-intel.d: New. * gas/i386/lock-1.d: Likewise. * gas/i386/lock-1.s: Likewise. * gas/i386/lockbad-1.l: Likewise. * gas/i386/lockbad-1.s: Likewise. * gas/i386/x86-64-lock-1-intel.d: Likewise. * gas/i386/x86-64-lock-1.d: Likewise. * gas/i386/x86-64-lock-1.s: Likewise. * gas/i386/x86-64-lockbad-1.l: Likewise. * gas/i386/x86-64-lockbad-1.s: Likewise. opcodes/ 2009-11-12 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Add IsLockable. * i386-opc.h (IsLockable): New. (i386_opcode_modifier): Add islockable. * i386-opc.tbl: Add IsLockable to add, adc, and, btc, btr, bts, cmpxchg, cmpxch8b, dec, inc, neg, not, or, sbb, sub, xor, xadd and xchg. * i386-tbl.h: Regenerated.	2009-11-12 18:57:14 +00:00
Daniel Jacobowitz	79862e4574	gas/testsuite/ * gas/arm/copro.d, gas/arm/fp-save.d, gas/arm/float.d, gas/arm/fpa-mem.d: Update for removed generic coprocessor instructions and expanded PC-relative offsets. opcodes/ * arm-dis.c (coprocessor_opcodes): Use %A instead of %C. Remove generic coprocessor instructions for FPA loads and stores. (print_insn_coprocessor): Remove %C support. Display address for PC-relative offsets in %A.	2009-11-12 14:49:45 +00:00
H.J. Lu	f310f33d50	gas/testsuite/ 2009-11-11 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/prefix.d: Swap order of ADDR and REP prefixes. * gas/i386/rep.d: Likewise. * gas/i386/x86-64-rep.d: Likewise. opcodes/ 2009-11-11 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (all_prefixes): New. (ckprefix): Set all_prefixes. (print_insn): Print all_prefixes instead of lock_prefix, repz_prefix, repnz_prefix, addr_prefix and data_prefix.	2009-11-12 02:13:06 +00:00
Nick Clifton	c1e2689731	PR binutils/10924 * arm-dis.c (UNPREDICTABLE_INSTRUCTION): New macro. (print_insn_arm): Extend %s format control code to check for unpredictable addressing modes. Add support for %S format control code which suppresses this check. (W_BIT, I_BIT, U_BIT, P_BIT): New macros. (WRITEBACK_BIT_SET, IMMEDIATE_BIT_SET, NEGATIVE_BIT_SET, PRE_BIT_SET): New macros. (print_insn_coprocessor): Use the new macros instead of magic constants. (print_arm_address): Likewise. (pirnt_insn_arm): Likewise. (print_insn_thumb32): Likewise.	2009-11-11 09:44:45 +00:00
Nick Clifton	41327c9d6d	Updated Indonesian translation.	2009-11-11 09:36:08 +00:00
Maxim Kuvyrkov	0d999f3337	* config/m68k-parse.h (enum m68k_register): Add ACR[4-7], RGPIOBAR. * config/tc-m68k.c (mcf5206_ctrl): Fix whitespace. (mcf52223_ctrl): Remove non-existent registers. (mcf54418): Define. (mcf54455): Remove MBAR. (m68k_cpus): Add lines for MCF5441x family. (m68k_ip, init_table): Handle RGPIOBAR, ACR[4-7]. * m68k-dis.c (print_insn_arg): Handle RGPIOBAR, ACR[4-7] and MBAR[01].	2009-11-10 18:05:24 +00:00
Sebastian Pop	c48244a521	2009-11-06 Sebastian Pop <sebastian.pop@amd.com> * opcodes/i386-dis.c (reg_table): Add XOP_8F_TABLE (XOP_09) to reg_table[REG_8F][1]: for XOP instructions, ModRM.reg first points to B.mm in the RXB.mmmmm byte, and so when B is set, we still should use the xop_table. (get_valid_dis386): Removed unused condition (from cut/n/paste) for XOP instructions. * gas/testsuite/gas/i386/x86-64-lwp.s: Updated to also contain patterns with r[8-15] registers. * gas/testsuite/gas/i386/x86-64-lwp.d: Same.	2009-11-06 23:17:26 +00:00
Sebastian Pop	f88c9eb030	2009-11-05 Sebastian Pop <sebastian.pop@amd.com> Quentin Neill <quentin.neill@amd.com> * gas/config/tc-i386.c (cpu_arch): Add CPU_LWP_FLAGS. (build_vex_prefix): Handle xop09 and xop0a. (build_modrm_byte): Handle vexlwp. (md_show_usage): Add lwp. * gas/doc/c-i386.texi (i386-LWP): New section. * gas/testsuite/gas/i386/i386.exp: Run x86-64-lwp in 64-bit mode, run lwp in 32-bit mode. * gas/testsuite/gas/i386/x86-64-lwp.d: New. * gas/testsuite/gas/i386/x86-64-lwp.s: New. * gas/testsuite/gas/i386/lwp.d: New. * gas/testsuite/gas/i386/lwp.s: New. * opcodes/i386-dis.c (OP_LWPCB_E): New. (OP_LWP_E): New. (OP_LWP_I): New. (USE_XOP_8F_TABLE): New. (XOP_8F_TABLE): New. (REG_XOP_LWPCB): New. (REG_XOP_LWP): New. (XOP_09): New. (XOP_0A): New. (reg_table): Redirect REG_8F to XOP_8F_TABLE. Add entries for REG_XOP_LWPCB and REG_XOP_LWP. (xop_table): New. (get_valid_dis386): Handle USE_XOP_8F_TABLE. Use the offsets VEX_0F, VEX_0F38, and VEX_0F3A instead of their values to access to the vex_table. (OP_LWPCB_E): New. (OP_LWP_E): New. (OP_LWP_I): New. * opcodes/i386-gen.c (cpu_flag_init): Add CPU_LWP_FLAGS, CpuLWP. (cpu_flags): Add CpuLWP. (opcode_modifiers): Add VexLWP, XOP09, and XOP0A. * opcodes/i386-opc.h (CpuLWP): New. (i386_cpu_flags): Add bit cpulwp. (VexLWP): New. (XOP09): New. (XOP0A): New. (i386_opcode_modifier): Add vexlwp, xop09, and xop0a. * opcodes/i386-opc.tbl (llwpcb): Added. (lwpval): Added. (lwpins): Added.	2009-11-05 23:40:05 +00:00
DJ Delorie	946ef19679	[opcodes] * rx-decode.opc (rx_decode_opcode) (mvtipl): Add. (mvtcp, mvfcp, opecp): Remove. * rx-decode.c: Regenerate. * rx-dis.c (cpen): Remove. [gas] * config/rx-parse.y (MVTIPL): Update bit pattern. (cpen): Remove. [include/opcode] * rx.h (rx_decode_opcode) (mvtipl): Add. (mvtcp, mvfcp, opecp): Remove.	2009-11-05 02:31:40 +00:00
DJ Delorie	0d734b5d06	[opcodes] * rx-decode.opc (rx_decode_opcode) (mvtipl): Add. (mvtcp, mvfcp, opecp): Remove. * rx-decode.c: Regenerate. * rx-dis.c (cpen): Remove. [gas] * config/rx-parse.y (MVTIPL): Update bit pattern. (cpen): Remove. [include/opcode] * rx.h (rx_decode_opcode) (mvtipl): Add. (mvtcp, mvfcp, opecp): Remove.	2009-11-05 00:38:45 +00:00
Doug Evans	d51b88d344	* m32c-desc.c: Regenerate. * mep-desc.c: Regenerate.	2009-11-04 06:18:27 +00:00
Paul Brook	62f3b8c867	2009-11-02 Paul Brook <paul@codesourcery.com> ld/testsuite/ * ld-arm/arm-elf.exp: Add new attr-merge-vfp tests. * ld-arm/attr-merge-vfp-1.d: New test. * ld-arm/attr-merge-vfp-1r.d: New test. * ld-arm/attr-merge-vfp-2.d: New test. * ld-arm/attr-merge-vfp-2r.d: New test. * ld-arm/attr-merge-vfp-3.d: New test. * ld-arm/attr-merge-vfp-3r.d: New test. * ld-arm/attr-merge-vfp-4.d: New test. * ld-arm/attr-merge-vfp-4r.d: New test. * ld-arm/attr-merge-vfp-5.d: New test. * ld-arm/attr-merge-vfp-5r.d: New test. * ld-arm/attr-merge-vfp-2.s: New test. * ld-arm/attr-merge-vfp-3.s: New test. * ld-arm/attr-merge-vfp-3-d16.s: New test. * ld-arm/attr-merge-vfp-4.s: New test. * ld-arm/attr-merge-vfp-4-d16.s: New test. gas/ * doc/c-arm.texi: Document new -mfpu options. * config/tc-arm.c (fpu_vfp_ext_v3xd, fpu_vfp_fp16, fpu_neon_ext_fma, fpu_vfp_ext_fma): New. (NEON_ENC_TAB): Add vfma, vfms, vfnma and vfnms. (do_vfp_nsyn_fma_fms, do_neon_fmac): New functions. (insns): Move double precision load/store. Split out double precision VFPv3 instrucitons. Add VFPv4 instructions. (arm_fpus): Add VFPv3-FP16, VFPv3xD and VFPv4 variants. (aeabi_set_public_attributes): Set VFPv4 variants gas/testsuite/ * gas/arm/attr-mfpu-vfpv4.d: New test. * gas/arm/attr-mfpu-vfpv4-d16.d: New test. * gas/arm/neon-fma-cov.d: New test. * gas/arm/neon-fma-cov.s: New test. * gas/arm/vfp-fma-inc.s: New test. * gas/arm/vfp-fma-arm.d: New test. * gas/arm/vfp-fma-arm.s: New test. * gas/arm/vfp-fma-thumb.d: New test. * gas/arm/vfp-fma-thumb.s: New test. * gas/arm/vfma1.d: New test. * gas/arm/vfma1.s: New test. * gas/arm/vfpv3xd.d: New test. * gas/arm/vfpv3xd.s: New test. include/opcode/ * arm.h (FPU_VFP_EXT_V3xD, FPU_VFP_EXT_FP16, FPU_NEON_EXT_FMA, FPU_VFP_EXT_FMA, FPU_VFP_V3xD, FPU_VFP_V4D16, FPU_VFP_V4): Define. (FPU_ARCH_VFP_V3D16_FP16, FPU_ARCH_VFP_V3_FP16, FPU_ARCH_VFP_V3xD, FPU_ARCH_VFP_V3xD_FP16, FPU_ARCH_VFP_V4, FPU_ARCH_VFP_V4D16, FPU_ARCH_NEON_VFP_V4): Define. binutils/ * readelf.c (arm_attr_tag_VFP_arch): Add VFPv4 and VFPv4-D16. bfd/ * elf32-arm.c (elf32_arm_merge_eabi_attributes): Handle VFPv4 attributes. opcodes/ * arm-dis.c (coprocessor_opcodes): Update to use new feature flags. Add VFPv4 instructions.	2009-11-02 13:44:05 +00:00
H.J. Lu	206c2556c2	gas/ 2009-10-29 Sebastian Pop <sebastian.pop@amd.com> * config/tc-i386.c (build_modrm_byte): Do not swap REG and NDS operands for FMA4. gas/testsuite/ 2009-10-29 Sebastian Pop <sebastian.pop@amd.com> * gas/i386/fma4.d: Updated patterns. * gas/i386/x86-64-fma4.d: Same. opcodes/ 2009-10-29 Sebastian Pop <sebastian.pop@amd.com> * i386-dis.c (OP_VEX_FMA): Removed. (VexFMA): Removed. (Vex128FMA): Removed. (prefix_table): First source operand of FMA4 insns is decoded with Vex not with VexFMA. (OP_EX_VexW): Second source operand is decoded with get_vex_imm8 when vex.w is set. Third source operand is decoded with get_vex_imm8 when vex.w is cleared. (OP_VEX_FMA): Removed.	2009-10-29 22:22:59 +00:00
Alan Modra	a2b2318d99	* Makefile.am (HFILES): Remove cgen-ops.h and cgen-types.h.	2009-10-27 01:49:26 +00:00
Doug Evans	ac1e9eca70	cpu/ * m32c.opc (opc.h): cgen-types.h -> cgen/basic-modes.h. cgen-ops.h -> cgen/basic-ops.h. include/opcode/ * cgen-bitset.h: Delete, moved to ../cgen/bitset.h. * cgen.h: Update. Improve multi-inclusion macro name. include/cgen/ * basic-modes.h: New file. Moved here from opcodes/cgen-types.h. * basic-ops.h: New file. Moved here from opcodes/cgen-ops.h. * bitset.h: New file. Moved here from ../opcode/cgen-bitset.h. Update license to GPL v3. opcodes/ * cgen-ops.h: Delete, moved to ../include/cgen/basic-ops.h. * cgen-types.h: Delete, moved to ../include/cgen/basic-modes.h. * cgen-bitset.c: Update. * fr30-desc.h: Regenerate. * frv-desc.h: Regenerate. * ip2k-desc.h: Regenerate. * iq2000-desc.h: Regenerate. * lm32-desc.h: Regenerate. * m32c-desc.h: Regenerate. * m32c-opc.h: Regenerate. * m32r-desc.h: Regenerate. * mep-desc.h: Regenerate. * mt-desc.h: Regenerate. * openrisc-desc.h: Regenerate. * xc16x-desc.h: Regenerate. * xstormy16-desc.h: Regenerate.	2009-10-24 00:17:08 +00:00
DJ Delorie	f282425ecd	* rx-decode.opc (decode_opcode): Fix flags for MUL, SUNTIL, and SWHILE. * rx-decode.c: Regenerated.	2009-10-23 01:11:53 +00:00
H.J. Lu	4b06377fcc	gas/ 2009-10-20 H.J. Lu <hongjiu.lu@intel.com> PR gas/10775 * doc/c-i386.texi: Mention movabs. gas/testsuite/ 2009-10-20 H.J. Lu <hongjiu.lu@intel.com> PR gas/10775 * gas/i386/immed64.d: Updated. * gas/i386/l1om.d: Likewise. * gas/i386/x86-64-disp-intel.d: Likewise. * gas/i386/x86-64-disp.d: Likewise. * gas/i386/x86_64.d: Likewise. opcodes/ 2009-10-20 H.J. Lu <hongjiu.lu@intel.com> PR gas/10775 * i386-dis.c: Document LB, LS and LV macros. (dis386): Use mov%LB, mov%LS and mov%LV on mov instruction with the 64-bit displacement or immediate operand. (putop): Handle LB, LS and LV macros.	2009-10-20 22:18:19 +00:00
Doug Evans	cedb97b6d0	* lm32-opinst.c: Regenerate. * m32c-desc.c: Regenerate. * m32r-opinst.c: Regenerate. * openrisc-ibld.c: Regenerate. * xc16x-desc.c: Regenerate. * xc16x-desc.h: Regenerate.	2009-10-19 05:09:44 +00:00
Doug Evans	d1119f7a8c	* Makefile.am (CGEN_CPUS): Add iq2000, lm32. (FR30_DEPS, FRV_DEPS, IQ2000_DEPS): Move so all cgen _DEPS are sorted alphabetically. (stamp-fr30, stamp-frv, stamp-iq2000, stamp-xc16x): Move so all cgen stamp- rules are sorted alphabetically. * Makefile.in: Regenerate.	2009-10-17 17:38:09 +00:00
H.J. Lu	52a6c1fedd	2009-10-16 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h: Use enum instead of nested macros.	2009-10-16 15:50:52 +00:00
H.J. Lu	3873ba1230	2009-10-16 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c: Simplify enums.	2009-10-16 14:47:08 +00:00
H.J. Lu	51e7da1b40	2009-10-15 H.J. Lu <hongjiu.lu@intel.com> Ineiev <ineiev@gmail.com> PR binutils/10767 * i386-dis.c: Use enum instead of nested macros.	2009-10-15 22:50:09 +00:00
H.J. Lu	c39846ed0a	2009-10-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (MAX_BYTEMODE): Removed.	2009-10-15 22:26:55 +00:00
Alan Modra	6a327e170e	PR 969 * m68k-opc.c (m68k_opcodes): Correct mask for macl and msacl.	2009-10-14 11:30:20 +00:00
H.J. Lu	55b126d49c	2009-10-13 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (print_insn): Always clear need_vex, need_vex_reg and vex_w_done.	2009-10-13 18:44:19 +00:00
Michael Eager	ef29941507	* opcodes/microblaze-dis.c: Add include for microblaze-dis.h, eliminate local extern decls. * opcodes/microblaze-dis.h: New.	2009-10-07 15:40:17 +00:00
Nick Clifton	245caaea22	Updated Finnish translation	2009-10-06 15:44:40 +00:00
Nick Clifton	49293ef70b	* opc2c.c: Include "libiberty.h" and <errno.h>. (orig_filename): Constify. (dump_lines): Fix line number directive. (main): Set orig_filename to basename of input file. Use xstrerror. * Makefile.am (rx-dis.lo): Remove explicit dependencies. ($(srcdir)/rx-decode.c): Use @MAINT@. Use $(EXEEXT_FOR_BUILD) instead of $(EXEEXT). (opc2c$(EXEEXT_FOR_BUILD)): Renamed from opc2c$(EXEEXT) and use $(LINK_FOR_BUILD). Link with libiberty. (MOSTLYCLEANFILES): Add opc2c$(EXEEXT_FOR_BUILD). (MAINTAINERCLEANFILES): Add $(srcdir)/rx-decode.c. * Makefile.in: Regenerated. * rx-decode.c: Regenerated.	2009-10-05 13:14:55 +00:00
H.J. Lu	caeec88ad4	Revert the last change.	2009-10-03 17:00:16 +00:00
H.J. Lu	ac845c8691	2009-10-03 H.J. Lu <hongjiu.lu@intel.com> * Makefile.am ($(srcdir)/rx-decode.c): Add @MAINT@. (rx-dis.lo): Remove a space. (pc2c$(EXEEXT)): Remove a space. Use $(LINK_FOR_BUILD) instead of gcc. (MAINTAINERCLEANFILES): Add $(srcdir)/rx-decode.c. * Makefile.in: Regenerated.	2009-10-03 14:36:34 +00:00
Alan Modra	8977d4b219	* arm-dis.c (print_insn): Check symtab_size not *symtab.	2009-10-03 00:39:53 +00:00
H.J. Lu	f98fa53424	2009-10-02 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Drop Disp64 on jump and loop instructions. * i386-tbl.h: Regenerated.	2009-10-02 19:03:40 +00:00
Alan Modra	e0c483d688	typo fix	2009-10-02 15:35:01 +00:00
Peter Bergner	9fe54b1ca1	gas/ * config/tc-ppc.c (md_show_usage): Document -m476. * doc/c-ppc.texi (PowerPC-Opts): Document -m476. gas/testsuite/ * gas/ppc/476.s: New test. * gas/ppc/476.d: Likewise. * gas/ppc/ppc.exp: Run the 476 test. include/opcode/ * ppc.h (PPC_OPCODE_476): Define. opcodes/ * ppc-dis.c (ppc_opts): Add "476" entry. * ppc-opc.c (PPC476): Define. (powerpc_opcodes): Update mnemonics where required for 476.	2009-10-02 14:42:42 +00:00
Peter Bergner	634b50f2a6	gas/ * config/tc-ppc.c (md_show_usage): Rename "ppca2" to "a2". * doc/c-ppc.texi (PowerPC-Opts): Likewise. gas/testsuite/ * gas/ppc/a2.d: Rename "ppca2" to "a2". include/opcode/ * ppc.h (PPC_OPCODE_A2): Rename from PPC_OPCODE_PPCA2. opcodes/ * ppc-opc.c (PPCA2): Use renamed mask PPC_OPCODE_A2. * ppc-dis.c (ppc_opts): Likewise. Rename "ppca2" to "a2".	2009-10-01 19:24:48 +00:00
M R Swami Reddy	4ded9dda7c	2009-10-01 M R Swami Reddy <MR.Swami.Reddy@nsc.com> * crx-dis.c (match_opcode): Truncate mcode to 32-bit.	2009-10-01 08:19:55 +00:00
Nick Clifton	c7927a3c0e	bfd * Makefile.am (ALL_MACHINES): Add cpu-rx.lo. (ALL_MACHINES_CFILES): Add cpu-rx.c. (BFD32_BACKENDS): Add elf32-rx.lo. (BFD32_BACKENDS_CFILES): Add elf32-rx.c. * archures.c (bfd_architecture): Add bfd_arch_rx and bfd_mach_rx. Export bfd_rx_arch. (bfd_archures_list): Add bfd_rx_arch. * config.bfd: Add entry for rx--elf. configure.in: Add entries for bfd_elf32_rx_le_vec and bfd_elf32_rx_be_vec. * reloc.c: Add RX relocations. * targets.c: Add RX target vectors. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * libbfd.h: Regenerate. * cpu-rx.c: New file. * elf32-rx.c: New file. binutils * readelf.c: Add support for RX target. * MAINTAINERS: Add DJ and NickC as maintainers for RX. gas * Makefile.am: Add RX target. * configure.in: Likewise. * configure.tgt: Likewise. * read.c (do_repeat_with_expander): New function. * read.h: Provide a prototype for do_repeat_with_expander. * doc/Makefile.am: Add RX target documentation. * doc/all.texi: Likewise. * doc/as.texinfo: Likewise. * Makefile.in: Regenerate. * NEWS: Mention support for RX architecture. * configure: Regenerate. * doc/Makefile.in: Regenerate. * config/rx-defs.h: New file. * config/rx-parse.y: New file. * config/tc-rx.h: New file. * config/tc-rx.c: New file. * doc/c-rx.texi: New file. gas/testsuite * gas/rx: New directory. * gas/rx/: New set of test cases. gas/elf/section2.e-rx: New expected output file. * gas/all/gas.exp: Add support for RX target. * gas/elf/elf.exp: Likewise. * gas/lns/lns.exp: Likewise. * gas/macros/macros.exp: Likewise. include * dis-asm.h: Add prototype for print_insn_rx. include/elf * rx.h: New file. include/opcode * rx.h: New file. ld * Makefile.am: Add rules to build RX emulation. * configure.tgt: Likewise. * NEWS: Mention support for RX architecture. * Makefile.in: Regenerate. * emulparams/elf32rx.sh: New file. * emultempl/rxelf.em: New file. opcodes * Makefile.am: Add RX files. * configure.in: Add support for RX target. * disassemble.c: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * opc2c.c: New file. * rx-decode.c: New file. * rx-decode.opc: New file. * rx-dis.c: New file.	2009-09-29 14:17:19 +00:00
Peter Bergner	8765b55692	opcodes/ * ppc-opc.c (powerpc_opcodes): Remove support for the the "lxsdux", "lxvd2ux", "lxvw4ux", "stxsdux", "stxvd2ux" and "stxvw4ux" opcodes. gas/testsuite/ * gas/ppc/vsx.s ("lxsdux", "lxvd2ux", "lxvw4ux", "stxsdux", "stxvd2ux", "stxvw4ux"): Remove tests. * gas/ppc/vsx.d: Likewise. * gas/ppc/power7.s: Likewise. * gas/ppc/power7.d: Likewise.	2009-09-29 13:19:10 +00:00
Michael Eager	fe2d172ccb	2009-09-25 Michael Eager <eager@eagercon.com> * microblaze-dis.c (get_insn_microblaze, microblaze_get_target_address, microblaze_decode_insn): Add declarations. (get_delay_slots_microblaze): Remove.	2009-09-25 19:59:51 +00:00
Nick Clifton	21d799b5c4	Update soruces to make alpha, arc and arm targets compile cleanly with -Wc++-compat: * config/tc-alpha.c: Add casts. (extended_bfd_reloc_code_real_type): New type. Used to avoid enumeration conversion warnings. (struct alpha_fixup, void assemble_insn, assemble_insn) (assemble_tokens): Use new type. * ecoff.c: Add casts. (mark_stabs): Use enumeration names. * config/obj-elf.c: Add cast * config/tc-arc.c: Add casts. * config/obj-aout.h (text_section,data_section,bss_section): Make extern. * config/obj-elf.c: Add cast. * config/tc-arm.c: Add casts. (X, TxCE, TxCE, TxC3, TxC3w, TxCM_, TxCM, TUE, TUF, CE, CL, cCE) (cCL, C3E, xCM_, nUF, nCE_tag): Change input format to avoid the need for keywords as arguments. * ecoff.c: Add casts. * ecofflink.c: Add casts. * elf64-alpha.c: Add casts. (struct alpha_elf_got_entry, struct alpha_elf_reloc_entry): Move to top level. (SKIP_HOWTO): Use enum name. * elf32-arm.c: Add casts. (elf32_arm_vxworks_bed): Update code to avoid multiple declarations. (struct map_stub): Move to top level. * arc-dis.c Fix casts. * arc-ext.c: Add casts. * arm-dis.c (enum opcode_sentinel_enum): Gave name to anonymous enum. * emultempl/armelf.em: Add casts.	2009-09-25 19:13:27 +00:00
H.J. Lu	2bf05e5730	gas/ 2009-09-24 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_vex_prefix): Check vex == 2 instead of vex256. opcodes/ 2009-09-24 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove Vex256. (set_bitfield): Handle XXX=V. * i386-opc.h (Vex): Update comments. (Vex256): Removed. (VexNDS): Updated. (i386_opcode_modifier): Change vex to 2 bits. Remove vex256. * i386-opc.tbl: Replace "Vex\|Vex256" with Vex=2. * i386-tbl.h: Regenerated.	2009-09-24 16:37:09 +00:00
Nick Clifton	8a00d39205	Updated French and Vietnamese translations.	2009-09-23 10:09:19 +00:00
Ben Elliston	e0d602ecff	gas/ * config/tc-ppc.c (md_show_usage): Document -mpcca2. * doc/c-ppc.texi (PowerPC-Opts): Document -mppca2. gas/testsuite/ * gas/ppc/a2.s: New. * gas/ppc/a2.d: Likewise. * gas/ppc/ppc.exp: Run the a2 dump test. include/opcode/ * ppc.h (PPC_OPCODE_PPCA2): New. opcodes/ * ppc-dis.c (ppc_opts): Add "ppca2" entry. * ppc-opc.c (powerpc_opcodes): Add eratilx, eratsx, eratsx., eratre, wchkall, eratwe, ldawx., mdfcrx., mfdcr. mtdcrx., icswx, icswx., mtdcr., dci, wclrone, wclrall, wclr, erativax, tlbsrx., ici mnemonics. (ERAT_T): New operand. (XWC_MASK): New mask. (XOPL2): New macro. (PPCA2): Define.	2009-09-21 10:29:07 +00:00
Nick Clifton	ca58b19f00	Updated Spanish and Vietnamese translations	2009-09-18 07:54:47 +00:00
H.J. Lu	0520304376	2009-09-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_E_memory): Don't print '-' in Intel mode if disp == -disp.	2009-09-15 17:53:40 +00:00
Nick Clifton	df58f7b0bf	Updated German, Dutch and Finnish translations.	2009-09-14 12:24:29 +00:00
Nick Clifton	1e9cc1c27b	* po/bfd.pot: Updated by the Translation project. * po/binutils.pot: Updated by the Translation project. * po/gold.pot: Updated by the Translation project. * po/gold.pot: Updated by the Translation project. * po/gprof.pot: Updated by the Translation project. * po/sv.po: Updated Swedish translation. * po/ld.pot: Updated by the Translation project. * po/fi.po: Updated Finnish translation. * po/ld.pot: Updated by the Translation project. * po/fi.po: Updated Finnish translation. Updated sources to compile cleanly with -Wc++-compat: * basic_blocks.c: Add casts. * cg_dfn.c: Add cast. * corefile.c: Add casts. * gmon_io.c: Add casts. * hist.c: Add cast. * source.c: Add cast. * sym_ids.c (struct match): Moved to top level. Updated soruces in ld/* to compile cleanly with -Wc++-compat: * ld.h (enum endian_enum,enum symbolic_enum,enum dynamic_list_enum): Move to top level. * ldcref.c: Add casts. * ldctor.c: Add casts. * ldexp.c * ldexp.h (enum node_tree_enum,enum phase_enum): Move to top level. * ldlang.c: Add casts. (lang_insert_orphan): Use enum name instead of integer. * ldlang.h (enum statement_enum): Move to top level. * ldmain.c: Add casts. * ldwrite.c: Add casts. * lexsup.c: Add casts. (enum control_enum): Move to top level. * mri.c: Add casts. (mri_draw_tree): Use enum name instead of integer. Updated sources to compile cleanly with -Wc++-compat: * basic_blocks.c: Add casts. * cg_dfn.c: Add cast. * corefile.c: Add casts. * gmon_io.c: Add casts. * hist.c: Add cast. * source.c: Add cast. * sym_ids.c (struct match): Moved to top level. * as.c (main): Call dwarf2_init. * config/obj-elf.c (struct group_list): New field. (build_group_lists): Use hash lookup. (free_section_idx): New function. (elf_frob_file): Adjust. * dwarf2dbg.c (all_segs_hash, last_seg_ptr): New variables. (get_line_subseg): Adjust. (dwarf2_init): New function. * dwarf2dbg.h (dwarf2_init): New declaration.	2009-09-11 15:27:38 +00:00
Andreas Krebbel	c8676ae452	2009-09-10 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-dis.c (print_insn_s390): Avoid 'long long'.	2009-09-10 09:04:06 +00:00
Andreas Krebbel	7330f9c3a4	2009-09-10 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-dis.c (s390_extract_operand): Remove the shift for pcrel operands. (print_insn_s390): Signextend and shift pcrel operands before printing.	2009-09-10 08:47:20 +00:00
H.J. Lu	9daa0d29f5	2009-09-09 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (vex_len_table): Change VEX_LEN_AE_R_X_M0 to VEX_LEN_AE_R_X_M_0 in comments.	2009-09-09 17:25:31 +00:00
DJ Delorie	495c5f871e	* cpu/mep.opc (mep_cgen_insn_supported_asm): Change the test to a preprocessor macro, not an enum.	2009-09-08 23:51:11 +00:00
Andreas Schwab	84c7196942	* z8kgen.c (struct op): Replace unused flavor with id. (opt): Remove extra xorb entry. (func): Use id field as fallback. (sub): Return new string, caller changed. (internal): Allocate end marker. Assign unique id before sorting. (gas): Likewise. Fix loop end condition. * z8k-opc.h: Regenerate.	2009-09-08 09:47:52 +00:00
Alan Modra	bdc7fcfe59	* ppc-opc.c (powerpc_macros <extrdi>): Allow n+b of 64.	2009-09-08 09:00:47 +00:00
Alan Modra	815c0482cb	* z8kgen.c (func): Fix thinko last patch.	2009-09-07 13:01:35 +00:00
Alan Modra	eae14d64d1	* z8kgen.c (func): Stabilize qsort of identically named entries. * z8k-opc.h: Regenerate.	2009-09-07 12:11:20 +00:00
Tristan Gingold	23f938f12a	bfd 2009-09-07 Tristan Gingold <gingold@adacore.com> * po/SRC-POTFILES.in: Regenerate. * po/bfd.pot: Regenerate. binutils 2009-09-07 Tristan Gingold <gingold@adacore.com> * po/binutils.pot: Regenerate. gas 2009-09-07 Tristan Gingold <gingold@adacore.com> * po/POTFILES.in: Regenerate. * po/gas.pot: Regenerate. gprof 2009-09-07 Tristan Gingold <gingold@adacore.com> * po/gprof.pot: Regenerate. ld 2009-09-07 Tristan Gingold <gingold@adacore.com> * po/ld.pot: Regenerate. opcodes 2009-09-07 Tristan Gingold <gingold@adacore.com> * po/opcodes.pot: Regenerate.	2009-09-07 11:29:56 +00:00
Alan Modra	2eee559322	* configure.in (BUILD_LIBS, BUILD_LIB_DEPS): Define and subst. * configure: Regenerate. * Makefile.am (LIBIBERTY, BUILD_LIBIBERTY, BUILD_LIBINTL): Delete. (BUILD_LIBS, BUILD_LIB_DEPS): Define. Use.. (i386-gen, ia64-gen, z8kgen): ..here. * Makefile.in: Regenerate.	2009-09-07 10:54:25 +00:00
Tristan Gingold	ae794f602d	2009-09-07 Tristan Gingold <gingold@adacore.com> * z8k-opc.h: Regenerate.	2009-09-07 08:14:09 +00:00
Nick Clifton	96d56e9f91	* bfd/coff-arm.c (coff_arm_relocate_section) (record_thumb_to_arm_glue, bfd_arm_process_before_allocation): Change member name class to symbol_class. * bfd/coff-i960.c (coff_i960_relocate_section) Rename variable class to class_val. Change member name class to symbol_class. * bfd/coff-rs6000.c (_bfd_xcoff_swap_aux_in) (_bfd_xcoff_swap_aux_out): Rename arguments class to in_class. * bfd/coff-stgo32.c (adjust_aux_in_post) (adjust_aux_out_pre, adjust_aux_out_post): Rename arguments class to in_class. * bfd/coff64-rs6000.c (_bfd_xcoff64_swap_aux_in) (_bfd_xcoff64_swap_aux_out): Rename arguments class to in_class. * bfd/coffcode.h (coff_pointerize_aux_hook): Rename variable class to n_sclass. * bfd/coffgen.c (coff_write_symbol, coff_pointerize_aux): Rename variables named class to n_sclass. (coff_write_symbols): Rename variable class to sym_class. (bfd_coff_set_symbol_class): Rename argument class to symbol_class. * bfd/cofflink.c (_bfd_coff_link_hash_newfunc) (coff_link_add_symbols, _bfd_coff_link_input_bfd) (_bfd_coff_write_global_sym, _bfd_coff_generic_relocate_section): Update code to use renamed members. * bfd/coffswap.h (coff_swap_aux_in, coff_swap_aux_out): Rename argument class to in_class. * bfd/libcoff-in.h (struct coff_link_hash_entry, struct coff_debug_merge_type) Renamed members class to symbol_class and type_class. * bfd/libcoff.h Regenerated. * bfd/peXXigen.c: (_bfd_XXi_swap_aux_in, _bfd_XXi_swap_aux_out): Rename argument class to in_class. * bfd/pef.c (bfd_pef_parse_imported_symbol): Update code to use renamed members. * bfd/pef.h (struct bfd_pef_imported_symbol): Changed name of member class to symbol_class. * binutils/ieee.c (ieee_read_cxx_misc, ieee_read_cxx_class) (ieee_read_reference): Rename variables named class to cxxclass. * gas/config/tc-arc.c (struct syntax_classes): Rename member class to s_class. (arc_extinst): Rename variable class to s_class. Update code to use renamed members. * gas/config/tc-mips.c (insn_uses_reg): Rename argument class to regclass. * gas/config/tc-ppc.c (ppc_csect, ppc_change_csect, ppc_function) (ppc_tc, ppc_is_toc_sym, ppc_symbol_new_hook, ppc_frob_label) (ppc_fix_adjustable, md_apply_fix): Update code to use renamed members. * gas/config/tc-ppc.h (struct ppc_tc_sy): Change name of member from class to symbol_class. (OBJ_COPY_SYMBOL_ATTRIBUTES): Update code to use renamed members. * gas/config/tc-score.c (s3_adjust_paritybit): Rename argument class to i_class. * gas/config/tc-score7.c (s7_adjust_paritybit): Rename argument class to i_class. * gprof/corefile.c (core_create_function_syms): Rename variable class to cxxclass. * include/coff/ti.h (GET_LNSZ_SIZE, PUT_LNSZ_SIZE): Updated name of class variable to in_class to match changes in function that use this macro. * include/opcode/ia64.h (struct ia64_operand): Renamed member class to op_class * ld/emultempl/elf32.em (gld${EMULATION_NAME}_load_symbols) (gld${EMULATION_NAME}_try_needed): Rename variable class to link_class * opcodes/ia64-dis.c (print_insn_ia64): Update code to use renamed member. * opcodes/m88k-dis.c (m88kdis): Rename variable class to in_class. * opcodes/tic80-opc.c (tic80_symbol_to_value) (tic80_value_to_symbol): Rename argument class to symbol_class.	2009-09-05 07:56:26 +00:00
Jie Zhang	66a6900a09	gas/ * config/bfin-parse.y (asm_1): Implement HLT instruction. Fix comments for DBGA, DBGAH and DBGAL. * config/tc-bfin.c (bfin_gen_pseudodbg_assert): Change according to the new encoding of DBGA, DBGAH, and DBGAL. include/ * opcode/bfin.h (PseudoDbg_Assert): Add bits_grp and mask_grp. (PseudoDbg_Assert_grp_bits, PseudoDbg_Assert_grp_mask): Define. (PseudoDbg_Assert_dbgop_bits, PseudoDbg_Assert_dbgop_mask, PseudoDbg_Assert_dontcare_bits, PseudoDbg_Assert_dontcare_mask): Adjust accordingly. (init_PseudoDbg_Assert): Add PseudoDbg_Assert_grp_bits and PseudoDbg_Assert_grp_mask. opcodes/ * bfin-dis.c (decode_pseudodbg_assert_0): Change according to the new encoding of DBGA, DBGAH, and DBGAL. (_print_insn_bfin): Likewise.	2009-09-04 04:29:42 +00:00
Jie Zhang	ad15c38ee6	gas/ * config/bfin-parse.y: Remove trailing whitespace. (ccstat): Indent. * config/tc-bfin.c (struct bfin_reg_entry): Remove. (bfin_reg_info[]): Remove. opcodes/ * bfin-dis.c (_print_insn_bfin): Don't declare. (print_insn_bfin): Don't declare. (dregs_pair): Remove. (ignore_bits): Remove. (ccstat): Remove.	2009-09-03 17:42:53 +00:00
Jie Zhang	c958a8a8fb	gas/ * config/bfin-defs.h (IS_GENREG): Define. (IS_DAGREG): Define. (IS_SYSREG): Define. * config/bfin-parse.y (asm_1): Check illegal register move instructions. gas/testsuite/ * gas/bfin/expected_move_errors.s, gas/bfin/expected_move_errors.l: Add "LC1 = I0;". * gas/bfin/move.s, gas/bfin/move.d: Remove "CYCLES = A0.W". opcodes/ * bfin-dis.c (IS_DREG): Define. (IS_PREG): Define. (IS_AREG): Define. (IS_GENREG): Define. (IS_DAGREG): Define. (IS_SYSREG): Define. (decode_REGMV_0): Check illegal register move instructions.	2009-09-03 16:17:36 +00:00
Dave Korn	3df5879c31	* Makefile.am (BUILD_LIBINTL): New variable. (i386-gen$(EXEEXT_FOR_BUILD)): Use it. (ia64-gen$(EXEEXT_FOR_BUILD)): And here. (z8kgen$(EXEEXT_FOR_BUILD)): And here. * Makefile.in: Regenerate.	2009-09-03 04:47:46 +00:00
Alan Modra	aa820537ea	update copyright dates	2009-09-02 07:25:43 +00:00
DJ Delorie	0531605226	[cgen] * cpu/mep.opc (parse_signed16_range): Mark as potentially unused. (parse_unsigned16_range): Likewise. (mep_cgen_insn_supported_asm): Make BSR12 check dependent on VLIW isa. [opcodes] * mep-asm.c: Regenerate. * mep-desc.c: Regenerate. * mep-opc.c: Regenerate.	2009-09-02 02:10:36 +00:00
Tristan Gingold	e06ae0d430	2009-09-01 Tristan Gingold <gingold@adacore.com> * makefile.vms: Ported to Itanium VMS. Remove useless targets and dependencies. Remove unused FORMAT variable. * configure.com: New file to create build.com DCL script for Itanium VMS or Alpha VMS.	2009-09-01 13:16:53 +00:00
Nick Clifton	d3ce72d070	Updated sources to avoid using the identifier name "new", which is a keyword in c++. * bfd/aoutx.h (NAME (aout, make_empty_symbol)): Rename variable new to new_symbol. * bfd/coffgen.c (coff_make_empty_symbol) (coff_bfd_make_debug_symbol): Rename variable new to new_symbol. * bfd/cpu-ia64-opc.c (ext_reg, ins_imms_scaled): Rename variable new to new_insn. * bfd/doc/chew.c (newentry, add_intrinsic): Rename variable new to new_d. * bfd/ecoff.c (_bfd_ecoff_make_empty_symbol): Rename variable new to new_symbol. * bfd/elf32-m68k.c (elf_m68k_get_got_entry_type): Rename argument new to new_reloc. * bfd/hash.c (bfd_hash_lookup): Rename variable new to new_string. * bfd/ieee.c (ieee_make_empty_symbol): Rename variable new to new_symbol. * bfd/linker.c (bfd_new_link_order): Rename variable new to new_lo. * bfd/mach-o.c (bfd_mach_o_sizeof_headers): Rename variable new to symbol. * bfd/oasys.c (oasys_make_empty_symbol): Rename variable new to new_symbol_type. * bfd/pdp11.c (NAME (aout, make_empty_symbol)): Rename variable new to new_symbol_type. * bfd/plugin.c (bfd_plugin_make_empty_symbol): Rename variable new to new_symbol. * bfd/rs6000-core.c (CoreHdr, VmInfo): Rename union member new to new_dump. (read_hdr, rs6000coff_core_p) (rs6000coff_core_file_matches_executable_p) (rs6000coff_core_file_failing_command) (rs6000coff_core_file_failing_signal): Updated function to use new union member name. * bfd/som.c (som_make_empty_symbol): Rename variable new to new_symbol_type. * bfd/syms.c (_bfd_generic_make_empty_symbol): Rename variable new to new_symbol. * bfd/tekhex.c (first_phase, tekhex_make_empty_symbol): Rename variable new to new_symbol. * binutils/nlmconv.c (main): Rename variable new to new_name. * gas/config/tc-arm.c (insert_reg_alias): Rename variable new to new_reg. * gas/config/tc-dlx.c (parse_operand): Rename variable new to new_pos. * gas/config/tc-ia64.c (ia64_gen_real_reloc_type): Rename variable new to newr. * gas/config/tc-mcore.c (parse_exp, parse_imm): Rename variable new to new_pointer. * gas/config/tc-microblaze.c (parse_exp, parse_imm, check_got): Change name from new to new_pointer. * gas/config/tc-or32.c (parse_operand): Rename variable new to new_pointer. * gas/config/tc-pdp11.c (md_assemble): Rename variable new to new_pointer. * gas/config/tc-pj.c (alias): Change argument new to new_name. * gas/config/tc-score.c (s3_build_score_ops_hsh): Rename variable new to new_opcode. (s3_build_dependency_insn_hsh) Rename variable new to new_i2n. (s3_convert): Rename variables old and new to r_old and r_new. * gas/config/tc-score7.c (s7_build_score_ops_hsh): Rename variable new to new_opcode. (s7_build_dependency_insn_hsh): Rename variable new to new_i2d. (s7_b32_relax_to_b16, s7_convert_frag): Rename variables old and new to r_old and r_new. * gas/config/tc-sh.c (parse_exp): Rename variable new to new_pointer. * gas/config/tc-sh64.c (shmedia_parse_exp): Rename variable new to new_pointer. * gas/config/tc-tic4x.c (tic4x_operand_parse): Rename variable new to new_pointer. * gas/config/tc-z8k.c (parse_exp): Rename variable new to new_pointer. * gas/listing.c (listing_newline): Rename variable new to new_i. * ld/ldexp.c (exp_intop, exp_bigintop, exp_relop, exp_binop) (exp_trinop, exp_unop, exp_nameop, exp_assop): Rename variable new to new_e. * ld/ldfile.c (ldfile_add_library_path): Rename variable new to new_dirs. (ldfile_add_arch): Rename variable new to new_arch. * ld/ldlang.c (new_statement, lang_final, lang_add_wild) (lang_target, lang_add_fill, lang_add_data, lang_add_assignment) (lang_add_insert): Rename variable new to new_stmt. (new_afile): Added missing cast. (lang_memory_region_lookup): Rename variable new to new_region. (init_os): Rename variable new to new_userdata. (lang_add_section): Rename variable new to new_section. (ldlang_add_undef): Rename variable new to new_undef. (realsymbol): Rename variable new to new_name. * opcodes/z8kgen.c (internal, gas): Rename variable new to new_op. Updated sources to avoid using the identifier name "template", which is a keyword in c++. * bfd/elf32-arm.c (struct stub_def): Rename member template to template_sequence. (arm_build_one_stub, find_stub_size_and_template, arm_size_one_stub, arm_map_one_stub): Rename variable template to template_sequence. * bfd/elfxx-ia64.c (elfNN_ia64_relax_br, elfNN_ia64_relax_brl): Rename variable template to template_val. * gas/config/tc-arm.c (struct asm_cond, struct asm_psr, struct asm_barrier_opt): Change member template to template_name. (md_begin): Update code to reflect new member names. * gas/config/tc-i386.c (struct templates, struct _i386_insn) (match_template, cpu_flags_match, match_reg_size, match_mem_size) (operand_size_match, md_begin, i386_print_statistics, pi) (build_vex_prefix, md_assemble, parse_insn, optimize_imm) (optimize_disp): Updated code to use new names. (parse_insn): Added casts. * gas/config/tc-ia64.c (dot_template, emit_one_bundle): Updated code to use new names. * gas/config/tc-score.c (struct s3_asm_opcode): Renamed member template to template_name. (s3_parse_16_32_inst, s3_parse_48_inst, s3_do_macro_ldst_label, s3_build_score_ops_hsh): Update code to use new names. * gas/config/tc-score7.c (struct s7_asm_opcode): Renamed member template to template_name. (s7_parse_16_32_inst, s7_do_macro_ldst_label, s7_build_score_ops_hsh): Update code to use new names. * gas/config/tc-tic30.c (md_begin, struct tic30_insn) (md_assemble): Update code to use new names. * gas/config/tc-tic54x.c (struct _tic54x_insn, md_begin) (optimize_insn, tic54x_parse_insn, next_line_shows_parallel): Update code to use new names. * include/opcode/tic30.h (template): Rename type template to insn_template. Updated code to use new name. * include/opcode/tic54x.h (template): Rename type template to insn_template. * opcodes/cris-dis.c (bytes_to_skip): Update code to use new name. * opcodes/i386-dis.c (putop): Update code to use new name. * opcodes/i386-gen.c (process_i386_opcodes): Update code to use new name. * opcodes/i386-opc.h (struct template): Rename struct template to insn_template. Update code accordingly. * opcodes/i386-tbl.h (i386_optab): Update type to use new name. * opcodes/ia64-dis.c (print_insn_ia64): Rename variable template to template_val. * opcodes/tic30-dis.c (struct instruction, get_tic30_instruction): Update code to use new name. * opcodes/tic54x-dis.c (has_lkaddr, get_insn_size) (print_parallel_instruction, print_insn_tic54x, tic54x_get_insn): Update code to use new name. * opcodes/tic54x-opc.c (tic54x_unknown_opcode, tic54x_optab): Update type to new name.	2009-08-29 22:11:02 +00:00
H.J. Lu	791f39718a	binutils/ 2009-08-28 H.J. Lu <hongjiu.lu@intel.com> * Makefile.am (sysinfo$(EXEEXT_FOR_BUILD)): Replace CFLAGS/LDFLAGS with CFLAGS_FOR_BUILD/LDFLAGS_FOR_BUILD. (syslex.o): Likewise. (sysinfo.o): Likewise. (bin2c$(EXEEXT_FOR_BUILD)): Likewise. * Makefile.in: Regenerated. opcodes/ 2009-08-28 H.J. Lu <hongjiu.lu@intel.com> * Makefile.am (COMPILE_FOR_BUILD): Remove BUILD_CPPFLAGS. Replace BUILD_CFLAGS with CFLAGS_FOR_BUILD. (LINK_FOR_BUILD): Replace BUILD_CFLAGS/BUILD_LDFLAGS with CFLAGS_FOR_BUILD/LDFLAGS_FOR_BUILD. * Makefile.in: Regenerated.	2009-08-29 00:41:25 +00:00
Ralf Wildenhues	573e8a1cd2	Do not create $(bfdlibdir) and $(bfdincludedir) if !INSTALL_LIBBFD. opcodes/: * Makefile.am (bfdlibdir, bfdincludedir): Move definition ... [INSTALL_LIBBFD]: ... here, ... [INSTALL_LIBBFD]: ... and empty overrides here. [!INSTALL_LIBBFD]: (rpath_bfdlibdir): New variable. [!INSTALL_LIBBFD] (libbfd_la_LDFLAGS): Use it. * Makefile.in: Regenerate. * configure: Regenerate. bfd/: * acinclude.m4 (AM_INSTALL_LIBBFD): Call AM_SUBST_NOTMAKE for bfdlibdir and bfdincludedir. * Makefile.am (bfdlibdir, bfdincludedir): Move definition ... [INSTALL_LIBBFD]: ... here, ... [INSTALL_LIBBFD]: ... and empty overrides here. [!INSTALL_LIBBFD]: (rpath_bfdlibdir): New variable. [!INSTALL_LIBBFD] (libbfd_la_LDFLAGS): Use it. * Makefile.in: Regenerate. * configure: Regenerate. bfd/doc/: * Makefile.in: Regenerate.	2009-08-27 05:24:43 +00:00
Nick Clifton	f7922329bf	* m68k-dis.c (print_insn_arg): Add movecr register names for coldfire v4e families.	2009-08-26 13:16:29 +00:00
Ralf Wildenhues	ff13a42d5c	Build cleanups in opcodes: cross-compilation and generators. opcodes/: * Makefile.am (SUBDIRS): Build '.' before 'po'. (COMPILE_FOR_BUILD, LINK_FOR_BUILD, BUILD_LIBIBERTY) (MOSTLYCLEANFILES, MAINTAINERCLEANFILES): New variables. (i386-gen$(EXEEXT_FOR_BUILD)): Renamed from i386-gen, rewrite using BUILD variables, depend upon $(BUILD_LIBIBERTY). (i386-gen.o): New rule. ($(srcdir)/i386-init.h): Adjust. (i386-opc.lo): Depend on $(srcdir)/i386-tbl.h. (ia64-gen$(EXEEXT_FOR_BUILD)): Rename from ia64-gen, adjust likewise. (ia64-gen.o): New rule. (ia64_asmtab_deps): New variable. ($(srcdir)/ia64-asmtab.c): Use it; adjust likewise. (ia64-opc.lo): Depend on $(srcdir)/ia64-asmtab.c. (s390-mkopc$(EXEEXT_FOR_BUILD)): Rename from s390-mkopc, adjust likewise. (s390-opc.tab): Adjust. (z8kgen$(EXEEXT_FOR_BUILD), z8kgen.o, $(srcdir)/z8k-opc.h): New rules. (z8k-dis.lo): Depend on $(srcdir)/z8k-opc.h. Makefile.in: Regenerate. * z8kgen.c (gas): Avoid '/' in comment. z8k-opc.h (func): Regenerate.	2009-08-25 03:13:44 +00:00
Ralf Wildenhues	6f01793dbb	More build fixes in opcodes opcodes/: * Makefile.am (TARGET_LIBOPCODES_CFILES): New variable, taken from $(CFILES), sorted, with dis-buf.c, dis-init.c, disassemble.c, i386-gen.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-f.c, ia64-opc-i.c, ia64-opc-m.c, ia64-opc-d.c, ia64-gen.c, ia64-asmtab.c removed, and msp430-dis.c added. (LIBOPCODES_CFILES): New variable, adding to TARGET_LIBOPCODES_CFILES also non-target library sources. (CFILES): Factorize based on $(LIBOPCODES_CFILES), adding generator files. (ALL_MACHINES): Factorize based on $(TARGET_LIBOPCODES_CFILES). (EXTRA_libopcodes_la_SOURCES): Use $(LIBOPCODES_CFILES). * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate.	2009-08-24 19:05:01 +00:00
Ralf Wildenhues	14ec8efdb1	Cleanups in binutils makefiles. ld/: * Makefile.am (bin_PROGRAMS): Renamed from ... (noinst_PROGRAMS): ... this. (transform): Override, including the renaming of ld-new to ld. (install-exec-local): Installation of ld in $(bindir) not needed here any more. (AM_CPPFLAGS): Renamed from ... (INCLUDES): ... this. (MAINTAINERCLEANFILES): Add ld.1. * Makefile.in: Regenerate. gold/: * Makefile.am (AM_CPPFLAGS): Renamed from ... (INCLUDES): ... this. * testsuite/Makefile.am (AUTOMAKE_OPTIONS): Add -Wno-portability. (AM_CPPFLAGS): Renamed from ... (INCLUDE): ... this. * Makefile.in, testsuite/Makefile.in: Regenerate. bfd/: * Makefile.am (libbfd_la_LDFLAGS): Initialize early, to allow appending. [INSTALL_LIBBFD] (bfdlib_LTLIBRARIES, bfdinclude_HEADERS): Set only in this condition. [!INSTALL_LIBBFD] (noinst_LTLIBRARIES, libbfd_la_LDFLAGS): New, to build but not install libbfd.la in this condition. (install-bfdlibLTLIBRARIES, uninstall-bfdlibLTLIBRARIES) (install_libbfd, install_libbfd): Remove. * Makefile.in: Regenerate. binutils/: * Makefile.am (AM_CPPFLAGS): Renamed from ... (INCLUDES): ... this. (bin2c$(EXEEXT_FOR_BUILD): Adjust rule. (installcheck-local): Renamed from ... (installcheck): ... this. * Makefile.in: Regenerate. gas/: * Makefile.am (YFLAGS): Remove, not needed any more. (AM_CPPFLAGS): Renamed from ... (INCLUDES): ... this. * Makefile.in: Regenerate. gprof/: * Makefile.am (AM_CPPFLAGS): Renamed from ... (INCLUDES): ... this. * Makefile.in: Regenerate. opcodes/: * Makefile.am (libopcodes_la_LDFLAGS): Initialize early. [INSTALL_LIBBFD] (bfdlib_LTLIBRARIES): Set only in this condition. [INSTALL_LIBBFD] (bfdinclude_DATA): New. [!INSTALL_LIBBFD] (noinst_LTLIBRARIES): New. [!INSTALL_LIBBFD] (libopcodes_la_LDFLAGS): Ensure libopcodes.la is built shared even if it is not to be installed. (install-bfdlibLTLIBRARIES,uninstall-bfdlibLTLIBRARIES) (install_libopcodes, uninstall_libopcodes): Remove. (AM_CPPFLAGS): Renamed from ... (INCLUDES): ... this. * Makefile.in: Regenerate.	2009-08-22 19:02:57 +00:00
Ralf Wildenhues	758227f0c5	dependency tracking in opcodes opcodes/: * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.9 and cygnus, add 1.11, foreign, no-dist. (MKDEP, m32c_opc_h): Remove variables. (disassemble.lo): Rewrite using automake-style dependency tracking rules; only list the dependency upon the primary source file, but no included headers. (m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo, m32c-opc.lo) (i386-gen.o, ia64-gen.o): Remove dependency statements. (EXTRA_libopcodes_la_SOURCES): New variable, list $(CFILES) to ensure all dependency fragments are included in the Makefile. (s390-opc.lo): Depend on s390-opc.tab. (DEP, DEP1, dep.sed, dep, dep-in, dep-am): Remove rules. (mkdep section): Remove. * Makefile.in: Regenerate. * po/POTFILES.in: Regenerate.	2009-08-22 18:44:58 +00:00
Ralf Wildenhues	af542c2e31	Cleanups after the update to Autoconf 2.64, Automake 1.11. /: * README-maintainer-mode: Point directly to upstream locations for autoconf, automake, libtool, gettext, instead of copies on sources.redhat.com. Document required versions. * configure.ac: Do not substitute datarootdir, htmldir, pdfdir, docdir. Do not process --with-datarootdir, --with-htmldir, --with-pdfdir, --with-docdir. * configure: Regenerate. gdb/: * CONTRIBUTE: Bump documented Autoconf version. * configure.ac: Do not substitute datarootdir, htmldir, pdfdir, docdir. Do not process --with-datarootdir, --with-htmldir, --with-pdfdir, --with-docdir. * configure: Regenerate. gdb/doc/: * gdbint.texinfo (Releasing GDB): Point to README-maintainer-mode file for required autoconf version. * configure.ac: Do not substitute datarootdir, htmldir, pdfdir, docdir. Do not process --with-datarootdir, --with-htmldir, --with-pdfdir, --with-docdir. * configure: Regenerate. gprof/: * Makefile.am (pdf__strip_dir, install-pdf, install-pdf-am) (install-pdf-recursive, html__strip_dir, install-html) (install-html-am, install-html-recursive): Remove. * Makefile.in: Regenerate. opcodes/: * Makefile.am (install-pdf, install-html): Remove. * Makefile.in: Regenerate. gas/: * Makefile.am (install-pdf, install-pdf-recursive, install-html) (install-html-recursive): Remove. * Makefile.in: Regenerate. * doc/Makefile.am (pdf__strip_dir, install-pdf, install-pdf-am) (html__strip_dir, install-html, install-html-am): Remove. * doc/Makefile.in: Regenerate. ld/: * Makefile.am (pdf__strip_dir, install-pdf, install-pdf-am) (install-pdf-recursive, html__strip_dir, install-html) (install-html-am, install-html-recursive): Remove. * Makefile.in: Regenerate. binutils/: * Makefile.am (install-pdf, install-pdf-recursive, install-html) (install-html-recursive): Remove. * Makefile.in: Regenerate. * doc/Makefile.am (pdf__strip_dir, install-pdf, install-pdf-am) (html__strip_dir, install-html, install-html-am): Remove. * doc/Makefile.in: Regenerate. bfd/: * Makefile.am (datarootdir, docdir, htmldor, pdfdir) (install-pdf, install-pdf-recursive, install-html) (install-html-recursive): Remove. * Makefile.in: Regenerate. bfd/doc/: * Makefile.am (pdf__strip_dir, install-pdf, install-pdf-am) (html__strip_dir, install-html, install-html-am): Remove. * Makefile.in: Regenerate.	2009-08-22 17:08:11 +00:00
Ralf Wildenhues	81ecdfbb4d	Regenerate tree using Autoconf 2.64 and Automake 1.11. config/: * override.m4 (_GCC_AUTOCONF_VERSION): Bump to 2.64. /: * configure: Regenerate. etc/: * configure: Regenerate. sim/common/: * config.in: Regenerate. * configure: Likewise. sim/iq2000/: * config.in: Regenerate. * configure: Likewise. sim/d10v/: * config.in: Regenerate. * configure: Likewise. sim/igen/: * config.in: Regenerate. * configure: Likewise. sim/m32r/: * config.in: Regenerate. * configure: Likewise. sim/frv/: * config.in: Regenerate. * configure: Likewise. sim/: * avr/config.in: Regenerate. * avr/configure: Likewise. * configure: Likewise. * cris/config.in: Likewise. * cris/configure: Likewise. sim/h8300/: * config.in: Regenerate. * configure: Likewise. sim/mn10300/: * config.in: Regenerate. * configure: Likewise. sim/ppc/: * config.in: Regenerate. * configure: Likewise. sim/erc32/: * config.in: Regenerate. * configure: Likewise. sim/arm/: * config.in: Regenerate. * configure: Likewise. sim/m68hc11/: * config.in: Regenerate. * configure: Likewise. sim/lm32/: * config.in: Regenerate. * configure: Likewise. sim/sh64/: * config.in: Regenerate. * configure: Likewise. sim/v850/: * config.in: Regenerate. * configure: Likewise. sim/cr16/: * config.in: Regenerate. * configure: Likewise. sim/moxie/: * config.in: Regenerate. * configure: Likewise. sim/m32c/: * config.in: Regenerate. * configure: Likewise. sim/mips/: * config.in: Regenerate. * configure: Likewise. sim/mcore/: * config.in: Regenerate. * configure: Likewise. sim/testsuite/d10v-elf/: * configure: Regenerate. sim/testsuite/: * configure: Regenerate. sim/testsuite/frv-elf/: * configure: Regenerate. sim/testsuite/m32r-elf/: * configure: Regenerate. sim/testsuite/mips64el-elf/: * configure: Regenerate. sim/sh/: * config.in: Regenerate. * configure: Likewise. gold/: * Makefile.in: Regenerate. * aclocal.m4: Likewise. * config.in: Likewise. * configure: Likewise. * testsuite/Makefile.in: Likewise. gprof/: * Makefile.in: Regenerate. * aclocal.m4: Likewise. * configure: Likewise. * gconfig.in: Likewise. opcodes/: * Makefile.in: Regenerate. * aclocal.m4: Likewise. * config.in: Likewise. * configure: Likewise. gas/: * Makefile.in: Regenerate. * aclocal.m4: Likewise. * config.in: Likewise. * configure: Likewise. * doc/Makefile.in: Likewise. ld/: * Makefile.in: Regenerate. * aclocal.m4: Likewise. * config.in: Likewise. * configure: Likewise. gdb/: * aclocal.m4: Regenerate. * config.in: Likewise. * configure: Likewise. * gnulib/Makefile.in: Likewise. gdb/doc/: * configure: Regenerate. gdb/gdbserver/: * aclocal.m4: Regenerate. * config.in: Likewise. * configure: Likewise. gdb/testsuite/: * configure: Regenerate. * gdb.hp/configure: Likewise. * gdb.hp/gdb.aCC/configure: Likewise. * gdb.hp/gdb.base-hp/configure: Likewise. * gdb.hp/gdb.compat/configure: Likewise. * gdb.hp/gdb.defects/configure: Likewise. * gdb.hp/gdb.objdbg/configure: Likewise. * gdb.stabs/configure: Likewise. binutils/: * Makefile.in: Regenerate. * aclocal.m4: Likewise. * config.in: Likewise. * configure: Likewise. * doc/Makefile.in: Likewise. bfd/: * Makefile.in: Regenerate. * aclocal.m4: Likewise. * config.in: Likewise. * configure: Likewise. bfd/doc/: * Makefile.in: Regenerate. readline/: * configure: Regenerate. readline/examples/rlfe/: * configure: Regenerate.	2009-08-22 16:56:56 +00:00
Nick Clifton	7ba29e2a41	Add support for Xilinx MicroBlaze processor. * bfd/Makefile.am: Add cpu-microblaze.{lo,c}, elf32-microblaze.{lo,c}. * bfd/Makefile.in: Same. * bfd/archures.c: Add bfd_arch_microblaze. * bfd/bfd-in2.h: Regenerate. * bfd/config.bfd: Add microblaze target. * bfd/configure: Add bfd_elf32_microblaze_vec target. * bfd/configure.in: Same. * bfd/cpu-microblaze.c: New. * bfd/elf32-microblaze.c: New. * bfd/libbfd-in.h: Add prototype _bfd_dwarf2_fixup_section_debug_loc(). * bfd/libbfd.h: Regenerate. * bfd/reloc.c: Add MICROBLAZE relocations. * bfd/section.c: Add struct relax_table and relax_count to section. * bfd/targets.c: Add bfd_elf32_microblaze_vec. * binutils/MAINTAINERS: Add self as maintainer. * binutils/readelf.c: Include elf/microblaze.h, add EM_MICROBLAZE & EM_MICROBLAZE_OLD to guess_is_rela(), dump_relocations(), get_machine_name(). * config.sub: Add microblaze target. * configure: Same. * configure.ac: Same. * gas/Makefile.am: add microblaze to CPU_TYPES, config/tc-microblaze.c to TARGET_CPU_CFILES, config/tc-microblaze.h to TARGET_CPU_HFILES, add DEP_microblaze_elf target. * gas/Makefile.in: Same. * gas/config/tc-microblaze.c: Add MicroBlaze assembler. * gas/config/tc-microblaze.h: Add header for tc-microblaze.c. * gas/configure: Add microblaze target. * gas/configure.in: Same. * gas/configure.tgt: Same. * gas/doc/Makefile.am: Add c-microblaze.texi to CPU_DOCS. * gas/doc/Makefile.in: Same. * gas/doc/all.texi: Set MICROBLAZE. * gas/doc/as.texinfo: Add MicroBlaze doc links. * gas/doc/c-microblaze.texi: New MicroBlaze docs. * include/dis-asm.h: Decl print_insn_microblaze(). * include/elf/common.h: Define EM_MICROBLAZE & EM_MICROBLAZE_OLD. * include/elf/microblaze.h: New reloc definitions. * ld/Makefile.am: Add eelf32mb_linux.o, eelf32microblaze.o to ALL_EMULATIONS, targets. * ld/Makefile.in: Same. * ld/configure.tgt: Add microblaze-linux, microblaze* targets. * ld/emulparams/elf32mb_linux.sh: New. * ld/emulparams/elf32microblaze.sh. New. * ld/scripttempl/elfmicroblaze.sc: New. * opcodes/Makefile.am: Add microblaze-opc.h to HFILES, microblaze-dis.c to CFILES, microblaze-dis.lo to ALL_MACHINES, targets. * opcodes/Makefile.in: Same. * opcodes/configure: Add bfd_microblaze_arch target. * opcodes/configure.in: Same. * opcodes/disassemble.c: Define ARCH_microblaze, return print_insn_microblaze(). * opcodes/microblaze-dis.c: New MicroBlaze disassembler. * opcodes/microblaze-opc.h: New MicroBlaze opcode definitions. * opcodes/microblaze-opcm.h: New MicroBlaze opcode types.	2009-08-06 17:38:04 +00:00
H.J. Lu	8a9036a406	bfd/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * archures.c (bfd_architecture): Add bfd_arch_l1om. (bfd_l1om_arch): New. (bfd_archures_list): Add &bfd_l1om_arch. * bfd-in2.h: Regenerated. * config.bfd (targ64_selvecs): Add bfd_elf64_l1om_vec if bfd_elf64_x86_64_vec is supported. Add bfd_elf64_l1om_freebsd_vec if bfd_elf64_x86_64_freebsd_vec is supported. (targ_selvecs): Likewise. * configure.in: Support bfd_elf64_l1om_vec and bfd_elf64_l1om_freebsd_vec. * configure: Regenerated. * cpu-l1om.c: New. * elf64-x86-64.c (elf64_l1om_elf_object_p): New. (bfd_elf64_l1om_vec): Likewise. (bfd_elf64_l1om_freebsd_vec): Likewise. * Makefile.am (ALL_MACHINES): Add cpu-l1om.lo. (ALL_MACHINES_CFILES): Add cpu-l1om.c. * Makefile.in: Regenerated. * targets.c (bfd_elf64_l1om_vec): New. (bfd_elf64_l1om_freebsd_vec): Likewise. (_bfd_target_vector): Add bfd_elf64_l1om_vec and bfd_elf64_l1om_freebsd_vec. binutils/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * readelf.c (guess_is_rela): Handle EM_L1OM. (dump_relocations): Likewise. (get_machine_name): Likewise. (get_section_type_name): Likewise. (get_elf_section_flags): Likewise. (get_symbol_index_type): Likewise. (is_32bit_abs_reloc): Likewise. (is_32bit_pcrel_reloc): Likewise. (is_64bit_abs_reloc): Likewise. (is_64bit_pcrel_reloc): Likewise. (is_none_reloc): Likewise. gas/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch): Add l1om. (check_cpu_arch_compatible): New. (set_cpu_arch): Use it. (i386_arch): New. (i386_mach): Return bfd_mach_l1om for Intel L1OM. (md_show_usage): Display l1om. (i386_target_format): Return ELF_TARGET_L1OM_FORMAT if cpu_arch_isa_flags.bitfield.cpul1om is set. * config/tc-i386.h (TARGET_ARCH): Use (i386_arch ()). (i386_arch): New. (ELF_TARGET_L1OM_FORMAT): Likewise. * doc/c-i386.texi: Document l1om. gas/testsuite/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/l1om.d: New. * gas/i386/l1om-inval.l: Likewise. * gas/i386/l1om-inval.s: Likewise. * gas/i386/i386.exp: Run l1om-inval and l1om. include/elf/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * common.h (EM_L1OM): New. ld/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * configure.tgt (targ64_extra_emuls): Add elf_l1om if elf_x86_64 is supported. Add elf_l1om_fbsd if elf_x86_64_fbsd is supported. (targ_extra_emuls): Likewise. * Makefile.am (ALL_64_EMULATIONS): Add eelf_l1om.o and eelf_l1om_fbsd.o (eelf_l1om.c): New. (eelf_l1om_fbsd.c): Likewise. * Makefile.in: Regenerated. * emulparams/elf_l1om.sh: New. * emulparams/elf_l1om_fbsd.sh: Likewise. ld/testsuite/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * ld-x86-64/abs-l1om.d: New. * ld-x86-64/protected2-l1om.d: Likewise. * ld-x86-64/protected3-l1om.d: Likewise. * ld-x86-64/x86-64.exp: Run abs-l1om, protected2-l1om and protected3-l1om. opcodes/ 2009-07-25 H.J. Lu <hongjiu.lu@intel.com> * configure.in: Handle bfd_l1om_arch. * disassemble.c (disassembler): Likewise. * configure: Regenerated. * i386-dis.c (print_insn): Handle bfd_mach_l1om and bfd_mach_l1om_intel_syntax. Use 8 bytes per line for Intel L1OM. * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to ~CpuL1OM. Add CPU_L1OM_FLAGS. (cpu_flags): Add CpuL1OM. (set_bitfield): Take an argument to set the value field. (process_i386_cpu_flag): Support ~CpuXXX and ~(CpuXXX\|CpuYYY). (process_i386_opcode_modifier): Updated. (process_i386_operand_type): Likewise. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. * i386-opc.h (CpuL1OM): New. (CpuXsave): Updated. (i386_cpu_flags): Add cpul1om.	2009-07-25 14:58:58 +00:00
Jan Beulich	309d33736f	gas/ 2009-07-24 Jan Beulich <jbeulich@novell.com> * tc-i386.c (cpu_arch): Add .8087, .287, .387, .no87, .nommx, .nosse, and .noavx. (cpu_flags_and_not): New. (set_cpu_arch): Check whether sub-architecture specified is a feature disable. (md_parse_option): Likewise. (parse_real_register): Don't return floating point register when x87 functionality is disabled. (md_show_usage): Add new sub-options. * doc/c-i386.texi: Update with new command line sub-options. gas/testsuite/ 2009-07-24 Jan Beulich <jbeulich@novell.com> * gas/i386/8087.[ds]: New. * gas/i386/287.[ds]: New. * gas/i386/387.[ds]: New. * gas/i386/no87.[ls]: New. * gas/i386/no87-2.[ls]: New. * gas/i386/i386.exp: Run new tests. * gas/i386/att-regs.s: Also check FPU register access. * gas/i386/intel-regs.s: Likewise. * gas/i386/att-regs.d: Adjust expectations. * gas/i386/intel-regs.d: Likewise. opcodes/ 2009-07-24 Jan Beulich <jbeulich@novell.com> * i386-dis.c (fgrps): Correct annotation for feni/fdisi. Add frstpm. * i386-gen.c (cpu_flag_init): Add FP enabling flags where needed. (cpu_flags): Add Cpu8087, Cpu287, Cpu387, Cpu687, and CpuFISTTP. (set_bitfield): Expand CpuFP to Cpu8087\|Cpu287\|Cpu387. * i386-opc.h (Cpu8087, Cpu287, Cpu387, Cpu687, CpuFISTTP): Define. (union i386_cpu_flags): Add cpu8087, cpu287, cpu387, cpu687, and cpufisttp. * i386-opc.tbl: Qualify floating point instructions by their respective CpuXXX flag. Fix fucom{,p,pp}, fprem1, fsin, fcos, and fsincos to be avilable only on 387. Fix fstsw ax to be available only on 287+. Add f{,n}eni, f{,n}disi, f{,n}setpm, and frstpm. * i386-init.h, i386-tbl.h: Regenerate.	2009-07-24 15:41:20 +00:00
Nick Clifton	7769efb28e	PR 10288 * arm-dis.c (arm_opcodes): Catch non-zero bits 8-11 in register offset or indexed based addressing mode 3.	2009-07-20 12:11:18 +00:00
Nick Clifton	74bdfecf08	PR 10288 * arm-dis.c (arm_opcodes): Catch illegal Addressing Mode 1 patterns. (arm_decode_shift): Catch illegal register based shifts. (print_insn_arm): Properly handle negative register r0 post-indexed addressing.	2009-07-14 14:16:34 +00:00
Doug Kwan	d1aaab3c71	2009-07-10 Doug Kwan <dougkwan@google.com> * arm-disc.c (print_insn_coprocessor, print_insn_arm): Print only lower 32 bits of long types to make hexadecimal output consistent on both 32-bit and 64-bit hosts.	2009-07-10 16:58:54 +00:00
Alan Modra	87337981d9	Regenerate.	2009-07-10 14:20:41 +00:00
Nick Clifton	1103f72c0f	gas/ * config/tc-arm.c (insns): Fix encoding for torvsc. gas/testsuite/ * gas/arm/iwmmxt2.d: Fix insn pattern for torvsc, add patterns for waddsubhx. * gas/arm/iwmmxt2.s: Add tests for waddsubhx. opcodes/ * arm-dis.c (coprocessor_opcodes): Fix mask for waddbhus.	2009-07-07 16:15:32 +00:00
Nick Clifton	78c66db84c	PR 10288 * arm-dis.c (arm_opcodes): Be more strict about decoding scaled addressing modes.	2009-07-07 14:46:14 +00:00
DJ Delorie	22102fb0d9	[cgen] * cpu/mep-core.cpu (fsft, ssarb): Mark as VOLATILE. * cpu/mep-ivc2.cpu (many): Add VOLATILE to more insns that make unspecified accesses to control registers. [sid/component/cgen-cpu/mep] * mep-cop1-16-decode.cxx: Regenerate. * mep-cop1-16-decode.h: Regenerate. * mep-cop1-16-defs.h: Regenerate. * mep-cop1-16-model.cxx: Regenerate. * mep-cop1-16-model.h: Regenerate. * mep-cop1-16-sem.cxx: Regenerate. * mep-cop1-32-decode.cxx: Regenerate. * mep-cop1-32-decode.h: Regenerate. * mep-cop1-32-defs.h: Regenerate. * mep-cop1-32-model.cxx: Regenerate. * mep-cop1-32-model.h: Regenerate. * mep-cop1-32-sem.cxx: Regenerate. * mep-cop1-48-decode.cxx: Regenerate. * mep-cop1-48-decode.h: Regenerate. * mep-cop1-48-defs.h: Regenerate. * mep-cop1-48-model.cxx: Regenerate. * mep-cop1-48-model.h: Regenerate. * mep-cop1-48-sem.cxx: Regenerate. * mep-cop1-64-decode.cxx: Regenerate. * mep-cop1-64-decode.h: Regenerate. * mep-cop1-64-defs.h: Regenerate. * mep-cop1-64-model.cxx: Regenerate. * mep-cop1-64-model.h: Regenerate. * mep-cop1-64-sem.cxx: Regenerate. * mep-core1-decode.cxx: Regenerate. * mep-core1-decode.h: Regenerate. * mep-core1-defs.h: Regenerate. * mep-core1-model.cxx: Regenerate. * mep-core1-model.h: Regenerate. * mep-core1-sem.cxx: Regenerate. * mep-cpu.h: Regenerate. * mep-decode.cxx: Regenerate. * mep-decode.h: Regenerate. * mep-defs.h: Regenerate. * mep-desc.h: Regenerate. * mep-model.cxx: Regenerate. * mep-model.h: Regenerate. * mep-sem.cxx: Regenerate. [opcodes] * mep-desc.c: Regenerate. * mep-desc.h: Regenerate. * mep-opc.c: Regenerate. * mep-opc.h: Regenerate.	2009-07-07 01:56:05 +00:00
Dwarakanath Rajagopal	922d8de8c1	<gas changes> 2009-07-06 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * config/tc-i386.c (cpu_arch): Add .fma4 and CPU_FMA4_FLAGS. (build_modrm_byte): Add support to handle FMA4 instructions. (md_show_usage): Add fma4. <gas/testsuite changes> 2009-07-06 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * gas/i386/i386.exp: Add FMA4 tests. * gas/i386/x86-64-fma4.d: Ditto. * gas/i386/fma4.d: Ditto. * gas/i386/x86-64-fma4.s: Ditto. * gas/i386/fma4.s: Ditto. <opcodes changes> 2009-07-06 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * i386-opc.h (CpuFMA4): Add CpuFMA4. (i386_cpu_flags): New. * i386-gen.c: Add CPU_FMA4_FLAGS. * i386-opc.tbl: Add FMA4 instructions. * i386-tbl.h: Regenerate. * i386-init.h: Regenerate. * i386-dis.c (OP_VEX_FMA): New. Handle FMA4. (OP_XMM_VexW): Ditto. (OP_EX_VexW): Ditto. (VEXI4_Fixup): Ditto. (VexI4, VexFMA, Vex128FMA, EXVexW, EXdVexW, XMVexW): New Macros. (PREFIX_VEX_3A5C, PREFIX_VEX_3A5D, PREFIX_VEX_3A5E): New. (PREFIX_VEX_3A5F, PREFIX_VEX_3A60): New. (PREFIX_VEX_3A68, PREFIX_VEX_3A69, PREFIX_VEX_3A6A): New. (PREFIX_VEX_3A6B, PREFIX_VEX_3A6C, PREFIX_VEX_3A6D): New. (PREFIX_VEX_3A6E, PREFIX_VEX_3A6F, PREFIX_VEX_3A7A): New. (PREFIX_VEX_3A7B, PREFIX_VEX_3A7C, PREFIX_VEX_3A7D): New. (PREFIX_VEX_3A7E, PREFIX_VEX_3A7F): New. (VEX_LEN_3A6A_P_2,VEX_LEN_3A6B_P_2, VEX_LEN_3A6E_P_2): New. (VEX_LEN_3A6F_P_2,VEX_LEN_3A7A_P_2, VEX_LEN_3A7B_P_2): New. (VEX_LEN_3A7E_P_2,VEX_LEN_3A7F_P_2): New. (get_vex_imm8): New. handle FMA4. (OP_EX_VexReg): Ditto.	2009-07-06 19:34:30 +00:00
Nick Clifton	fe56b6cece	PR 10288 * arm-dis.c (coprocessor): Print the LDC and STC versions of the LFM and SFM instructions as comments,. Improve consistency of formatting for instructions displayed as comments and decimal values displayed with their hexadecimal equivalents. Formatting tidy ups. Updated expected disassembler regexps.	2009-06-30 11:57:05 +00:00
Nick Clifton	05413229fd	PR 10288 * arm-dis.c (enum opcode_sentinels): New: Used to mark the boundary between variaant and generic coprocessor instuctions. (coprocessor): Use it. Fix architecture version of MCRR and MRRC instructions. (arm_opcdes): Fix patterns for STRB and STRH instructions. (print_insn_coprocessor): Check architecture and extension masks. Print a hexadecimal version of any decimal constant that is outside of the range of -16 to +32. (print_arm_address): Add a return value of the offset used in the adress, if it is worth printing a hexadecimal version of it. (print_insn_neon): Print a hexadecimal version of any decimal constant that is outside of the range of -16 to +32. (print_insn_arm): Likewise. (print_insn_thumb16): Likewise. (print_insn_thumb32): Likewise. PR 10297 * arm-dis.c (UNDEFINED_INSTRUCTION): New macro for a description of an undefined instruction. (arm_opcodes): Use it. (thumb_opcod): Use it. (thumb32_opc): Use it. Update expected disassembly regrexps in GAS and LD testsuites.	2009-06-29 08:08:15 +00:00
DJ Delorie	dab97f2471	[cgen] * intrinsics.scm: Updates to support IVC2. (belongs-to-group?): Check IVC2 slots. (-slots-attribute): New. (targets::attributes): Add SLOTS. (target:add-well-known-intrinsics): Add CPMOV. (md-insn): Add CPTYPE and CRET?. (add-md-insn): Likewise. (add-intrinsic-for-isa): Disable the duplicate tests, as IVC2 has duplicate insns with different bit patterns. (write-cgen-insn?): Add cret? support. (intrinsics.h): Add vector types. (runtime-op): Add vector support. (intrinsic-protos.h): Let GCC define its types. Add cret? support. * cpu/mep-core.cpu: Add CPTYPE and CRET attributes. * cpu/mep-ivc2.cpu: Update all insns to include type information. (h-cr-ivc2): Default to typeless. (h-ccr-ivc2): Fix register width. (SLOTS): Fix values and default. (ivc2_): Add control register names. (crop, crqp, crpp, croc, crqc, crpc): Default to typeless. [opcodes] mep-desc.c: Regenerate. * mep-desc.h: Regenerate. * mep-dis.c: Regenerate. * mep-ibld.c: Regenerate. * mep-opc.c: Regenerate. [sid/component/cgen-cpu/mep] * ivc2-cop.cxx (ivc2_cphadd_w): Change to return value. (ivc2_cpsubaca0u_b): Remove debug line. * ivc2-cpu.h (ivc2_cpccadd_b): Change to return value. * mep-cop1-16-decode.cxx: Regenerate. * mep-cop1-16-sem.cxx: Regenerate. * mep-cop1-32-decode.cxx: Regenerate. * mep-cop1-32-sem.cxx: Regenerate. * mep-cop1-48-decode.cxx: Regenerate. * mep-cop1-48-sem.cxx: Regenerate. * mep-cop1-64-decode.cxx: Regenerate. * mep-cop1-64-sem.cxx: Regenerate. * mep-core1-decode.cxx: Regenerate. * mep-cpu.h: Regenerate. * mep-decode.cxx: Regenerate. * mep-desc.h: Regenerate.	2009-06-24 03:06:42 +00:00
DJ Delorie	378a0c07ca	[cgen] * cpu/mep.opc (mep_cgen_insn_supported_asm): New, skip the short version of BSR when assembling VLIW bundles. Use it in mep-asm.c [opcodes] * mep-asm.c: Regenerate. * mep-opc.c: Regenerate. * mep-opc.h: Regenerate.	2009-06-24 01:44:53 +00:00
Nick Clifton	aece7d2e74	* po/fi.po: Updated Finish translation.	2009-06-22 11:32:21 +00:00
Alan Modra	1998a8e033	cpu/ * m32c.opc (parse_lab_5_3): Use correct enum. opcodes/ * m32c-asm.c: Regenerate.	2009-06-22 00:53:25 +00:00
Alan Modra	b33bafa0d7	* score-dis.c (print_insn_score48, print_insn_score32): Move default case label to proper lexical block. * score7-dis.c (print_insn_score32): Likewise.	2009-06-22 00:01:57 +00:00
Martin Schwidefsky	ce21feb4ba	* s390-opc.c (INSTR_RR_0R_OPT, INSTR_RX_0RRD_OPT, MASK_RR_0R_OPT, MASK_RX_0RRD_OPT): New instruction formats with optional arguments. * s390-opc.txt (nopr, nop): Use new instruction format.	2009-06-19 10:55:42 +00:00
Nick Clifton	0313a2b8d2	PR 10288 * arm-dis.c (print_insn_coprocessor): Check that a user specified ARM architecture supports the matched instruction. (print_insn_arm): Likewise. (select_arm_features): New function. Fills in the fields of an arm_feature_set structure based on a given arm machine number. (print_insn): Initialise an arm_feature_set structure. * objdump.c (disassemble_bytes): Set the USER_SPECIFIED_MACHINE_TYPE flag in the disassemble_info structure if the user has invoked the -m switch. * doc/binutils.texi: Document the additional behaviour of objdump's -m switch for ARM targets. * dis-asm.h (USER_SPECIFIED_MACHINE_TYPE): New value for the flags field of struct disassemble_info. * gas/arm/align.s: Add labels so that COFF based targets can correctly locate THUMB code. * gas/arm/copro.d: Do not pass --architecture switch to objdump.	2009-06-18 10:31:21 +00:00
Maciej W. Rozycki	6db7e006e4	bfd/ * elf32-vax.c (elf_vax_plt_sym_val): New function. (elf_backend_plt_sym_val): Define. opcodes/ * vax-dis.c (is_function_entry): Return success for synthetic symbols too. (is_plt_tail): New function. (print_insn_vax): Decode PLT entry offset longword.	2009-06-16 02:23:09 +00:00
Nick Clifton	fe2ceba101	PR 10186 * arm-dis.c (thumb32_opcodes): Fix binary value of SEV.W instruction. * gas/arm/thumb32.d: Fix expected binary value of SEV.W instruction. * config/tc-arm.c (T16_32_TAB): Fix binary value of SEV.W instruction.	2009-06-15 15:42:36 +00:00
Nick Clifton	522fe56177	PR 10173 * cr16-dis.c (print_arg): Avoid printing the 0x prefix twice.	2009-06-15 15:24:52 +00:00
Nick Clifton	1316c8b37f	PR 10263 * arm-dis.c (print_insn): Ignore is_data if the user has requested the disassembly of data as well as instructions. * objdump.c (disassemble_bytes): Set the DISASSEMBLE_DATA bit in the flags field of the disassemble_info structure if the -D switch is in operation. * dis-asm.h (struct disassemble_info): New value for the flags field.	2009-06-15 11:37:26 +00:00
Doug Evans	f6475b4872	* cgen.sh: Handle multiple simultaneous runs for parallel makes.	2009-06-14 16:36:56 +00:00
Anthony Green	f865a31d1e	Add PC-relative branch instructions to moxie port.	2009-06-11 11:27:58 +00:00
Anthony Green	0e7c7f11f4	Print moxie addresses nicely.	2009-06-06 13:02:21 +00:00
Alan Modra	67a648f17a	* dep-in.sed: Don't use \n in replacement part of s command. * Makefile.am (DEP1): LC_ALL for uniq. * Makefile.in: Regenerate.	2009-06-04 06:57:56 +00:00
Nick Clifton	06c582ac9d	* po/nl.po: Updated Dutch translation.	2009-06-02 16:31:59 +00:00
Tristan Gingold	3164099e4f	2009-05-29 Tristan Gingold <gingold@adacore.com> * ia64-gen.c (parse_resource_users, print_dependency_table, add_dis_table_ent, finish_distable, insert_bit_table_ent, add_dis_entry, compact_distree, gen_dis_table, completer_entries_eq, get_prefix_len, compute_completer_bits, insert_opcode_dependencies, insert_completer_entry, print_completer_entry, print_completer_table, opcodes_eq, add_opcode_entry, shrink): Use ISO C syntax for functions.	2009-06-02 07:48:05 +00:00
DJ Delorie	d285268e48	[cgen] * cpu/mep.opc (parse_signed16_range): New. (parse_unsigned16_range): New. * cpu/mep-ivc2.cpu (imm16p0, simm16p0): Use them. [opcodes] * mep-asm.c: Regenerate. * mep-desc.c: Regenerate.	2009-05-28 22:53:08 +00:00
DJ Delorie	2f3565a392	[cgen/cpu] * cpu/mep-ivc2.cpu (h-ccr-ivc2): Enable for C3 slots, fix accumulator names. (f-ivc2-ccrn-c3hi): New. (f-ivc2-ccrn-c3lo): New. (f-ivc2-ccrn-c3): New. (ivc2c3ccrn): Use it. [sid/component/cgen-cpu/mep] * mep-cop1-32-decode.cxx: Regenerate. * mep-cop1-32-decode.h: Regenerate. * mep-cop1-32-sem.cxx: Regenerate. * mep-cop1-48-sem.cxx: Regenerate. [opcodes] * mep-asm.c: Regenerate. * mep-desc.c: Regenerate. * mep-desc.h: Regenerate. * mep-dis.c: Regenerate. * mep-ibld.c: Regenerate. * mep-opc.c: Regenerate. * mep-opc.h: Regenerate.	2009-05-27 01:49:46 +00:00
Nick Clifton	f12e7348b2	Update Indonesian translations. Update translation templates.	2009-05-26 16:49:41 +00:00
Alan Modra	9e097a72c9	* dep-in.sed: Don't modify .o to .lo here. Output one filename per line with all lines having continuation backslash. Prefix first line with "A", following lines with "B". * Makefile.am (DEP): Don't use dep.sed here. (DEP1): Run $MKDEP on single files, modify .o to .lo here. Use dep.sed here on dependencies, sort and uniq. * Makefile.in: Regenerate.	2009-05-26 03:19:28 +00:00
Tristan Gingold	4f8318f890	2009-05-25 Tristan Gingold <gingold@adacore.com> * makefile.vms (OPT): New variable. (CFLAGS): Update compilation flags.	2009-05-25 12:43:48 +00:00
DJ Delorie	1d74713bc6	[cgen] * cpu/mep.opc (mep_examine_ivc2_insns): Fix bug in ivc2 decoder. (mep_config_map): Regenerate. * cpu/mep-ivc2.cpu (h-ccr-ivc2): Add generic names as well as ivc2-specific names. (simm8p20): New. (cmovc): move to after field definitions, use ivc2-specific register names. (cpmovi_b_P0S_P1): New. [utils/mep] * mepcfgtool.c (do_cgen_config_opc): Propagate endianness and VLIW size to default configuration. [sid/component/cgen-cpu/mep] * mep-cop1-16-decode.cxx: Regenerate. * mep-cop1-16-decode.h: Regenerate. * mep-cop1-16-model.cxx: Regenerate. * mep-cop1-16-model.h: Regenerate. * mep-cop1-16-sem.cxx: Regenerate. * mep-cop1-64-decode.cxx: Regenerate. * mep-cop1-64-decode.h: Regenerate. * mep-cop1-64-model.cxx: Regenerate. * mep-cop1-64-model.h: Regenerate. * mep-cop1-64-sem.cxx: Regenerate. [opcodes] * mep-asm.c: Regenerate. * mep-desc.c: Regenerate. * mep-desc.h: Regenerate. * mep-dis.c: Regenerate. * mep-ibld.c: Regenerate. * mep-opc.c: Regenerate. * mep-opc.h: Regenerate.	2009-05-22 17:37:45 +00:00
Dwarakanath Rajagopal	c1e679ec0a	<gas changes> 2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * config/tc-i386.c (process_drex): Delete. Remove SSE5 support. (build_modrm_byte): Remove DREX handling support. (DREX_): Delete. (drex_byte): Delete. (md_assemble): Remove DREX handling support. (process_operands): Remove DREX, SSE5 support. (i386_insn): Remove DREX. <gas/testsuite changes> 2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> gas/i386/i386.exp: Remove SSE5 tests. * gas/i386/x86-64-sse5.s: Delete. Remove SSE5 tests. * gas/i386/x86-64-sse5.d: Ditto. * gas/i386/arch-10-1.l: Remove SSE5 tests. * gas/i386/arch-10-2.l: Ditto. * gas/i386/arch-10-3.l: Ditto. * gas/i386/arch-10-4.l: Ditto. * gas/i386/arch-10.d: Ditto. * gas/i386/arch-10.s: Ditto. * gas/i386/arch-4.s: Delete. Remove SSE5 tests. * gas/i386/arch-4.d: Ditto. * gas/i386/arch-8.s: Ditto. * gas/i386/arch-8.d: Ditto. * gas/i386/arch-2.s: Remove SSE5 tests. * gas/i386/arch-2.d: Remove SSE5 tests. * gas/i386/x86-64-arch-2.s: Ditto. <opcodes changes> 2009-05-22 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> * i386-opc.h (Cpusse5): Delete. (i386_cpu_flags): Delete. * i386-gen.c: Remove CpuSSE5, Drex, Drexv and Drexc. * i386-opc.tbl: Remove SSE5 instructions. * i386-tbl.h: Regenerate. * i386-init.h: Regenerate. * i386-dis.c (OP_E_memeory, OP_E_extended): Remove drex handling. (print_drex_arg): Delete. (OP_DREX4): Delete. (OP_DREX3): Delete. (OP_DREX_ICMP): Delete. (OP_DREX_FCMP): Delete. (DREX_*): Delete. (THREE_BYTE_0F24, THREE_BYTE_0F25, THREE_BYTE_0f7B): Delete.	2009-05-22 15:57:25 +00:00
Alan Modra	2b3decb5e1	Run "make dep-am" and regenerate	2009-05-22 09:33:16 +00:00
DJ Delorie	eb9568003a	* mep-asm.c: Regenerate. * mep-opc.c: Regenerate.	2009-05-19 23:35:47 +00:00
DJ Delorie	3526b6802e	Index: opcodes * mep-asm.c: Regenerate. * mep-desc.c: Regenerate. * mep-desc.h: Regenerate. * mep-dis.c: Regenerate. * mep-ibld.c: Regenerate. * mep-opc.c: Regenerate. * mep-opc.h: Regenerate. Index: gas * config/tc-mep.c (md_begin): Check coprocessor type. (md_check_parallel64_scheduling): Use memset to initialize the buffer. (md_check_parallel32_scheduling): Likewise. (slot_ok): New. (mep_check_ivc2_scheduling): New. (mep_check_parallel_scheduling): Call it. (mep_process_saved_insns): Add IVC2 slot support. (md_assemble): Likewise.	2009-04-30 21:23:30 +00:00
Anthony Green	59b1530d0b	Add missing disassembler patch for moxie.	2009-04-30 04:54:08 +00:00
DJ Delorie	45be3704c8	[cgen] * cpu/mep-c5.cpu (f-12s20): Change to signed. (lhucpm1): Limit to C5 mach. (dsp0,dsp1): Rewrite as aliases so that intrinsics are generated. * cpu/mep-core.cpu (extend-cdisp10): New. (f-cdisp10): Change to signed, use extend-cdisp10 to sign extend. [opcodes] * mep-desc.c: Regenerate. * mep-ibld.c: Regenerate. * mep-opc.c: Regenerate. * mep-opc.h: Regenerate. [sid/component/cgen-cpu/mep] * mep-core1-decode.cxx: Regenerate. * mep-core1-decode.h: Regenerate. * mep-decode.cxx: Regenerate. * mep-decode.h: Regenerate.	2009-04-18 02:56:43 +00:00
DJ Delorie	52de720d5d	Add missing ChangeLog entry: * mep-asm.c: Regenerate. * mep-desc.c: Regenerate. * mep-desc.h: Regenerate. * mep-dis.c: Regenerate. * mep-ibld.c: Regenerate. * mep-opc.c: Regenerate. * mep-opc.h: Regenerate.	2009-04-18 01:50:02 +00:00
Nick Clifton	20135e4cea	Add new binutils target: moxie	2009-04-16 15:39:48 +00:00
Jan Beulich	ac5c19e6ba	gas/testsuite/ 2009-04-15 Jan Beulich <jbeulich@novell.com> * gas/i386/x86-64-sse5.s: Add test of protd. * gas/i386/x86-64-sse5.d: Adjust expectations to match input. opcodes/ 2009-04-15 Jan Beulich <jbeulich@novell.com> * i386-opc.tbl (protb, protw, protd, protq): Set opcode extension to None. (pshab, pshaw, pshad, pshaq): Likewise. * i386-tbl.h: Re-generate.	2009-04-15 13:31:28 +00:00
DJ Delorie	40493983ad	[cgen] * cpu/mep-c5.cpu: New. * cpu/mep-core.cpu: Add C5 support. * cpu/mep.opc: Likewise. [opcodes] * mep-asm.c: Regenerate. * mep-desc.c: Regenerate. * mep-desc.h: Regenerate. * mep-dis.c: Regenerate. * mep-ibld.c: Regenerate. * mep-opc.c: Regenerate. * mep-opc.h: Regenerate. [sid] * component/cache/cache.cxx (cache_component::cache_component): Add write_hint_pin(). Attach it to write-hint. (cache_component::write_hint): New. * component/cache/cache.h (write_hint_pin): New. (write_hint): New. * component/cgen-cpu/mep/Makefile.am: Regenerate. * component/cgen-cpu/mep/Makefile.in: Regenerate. * component/cgen-cpu/mep/mep-core1-decode.cxx: Regenerate. * component/cgen-cpu/mep/mep-core1-decode.h: Regenerate. * component/cgen-cpu/mep/mep-core1-defs.h: Regenerate. * component/cgen-cpu/mep/mep-core1-model.cxx: Regenerate. * component/cgen-cpu/mep/mep-core1-model.h: Regenerate. * component/cgen-cpu/mep/mep-core1-sem.cxx: Regenerate. * component/cgen-cpu/mep/mep-decode.cxx: Regenerate. * component/cgen-cpu/mep/mep-decode.h: Regenerate. * component/cgen-cpu/mep/mep-defs.h: Regenerate. * component/cgen-cpu/mep/mep-desc.h: Regenerate. * component/cgen-cpu/mep/mep-model.cxx: Regenerate. * component/cgen-cpu/mep/mep-model.h: Regenerate. * component/cgen-cpu/mep/mep-sem.cxx: Regenerate. * component/cgen-cpu/mep/mep.cxx (mep_cpu): Connect write-hint pin. (do_cache): Add C5 support. (do_cache_prefetch): Likewise. (do_casb3, do_cash3, do_casw3): New. * component/cgen-cpu/mep/mep.h: Add C5 support and write-hint pin. (do_casb3, do_cash3, do_casw3): New. * component/families/mep/Makefile.in: Regenerate. * component/families/mep/dsu.in: Add C5 support. * main/dynamic/mainDynamic.cxx: Add C5 support. * main/dynamic/mepCfg.cxx: Connect write-hint pin. * main/dynamic/mepCfg.h: Add C5 support.	2009-04-08 20:39:35 +00:00
Peter Bergner	858d7a6db2	opcodes/ * ppc-opc.c (powerpc_opcodes) <"tlbilxlpid", "tlbilxpid", "tlbilxva", "tlbilx">: Use secondary opcode "18" as per the ISA 2.06 documentation. Reorder entries so the extended mnemonics are listed before tlbilx. gas/testsuite/ * gas/ppc/e500mc.d: Update to match extended mnemonics.	2009-04-07 18:28:02 +00:00
Peter Bergner	70dc4e324b	opcodes/ * ppc-dis.c (powerpc_init_dialect): Do not choose a default dialect due to -many/-Many. (print_insn_powerpc): Make sure we only deprecate instructions using the original dialect and not a modified dialect due to -Many handling. Move the handling of the condition register and default operands to the end of the if/else if/else chain. * ppc-opc.c (powerpc_opcodes): Reorder the opcode table so that instructions from newer processors are listed before older ones. <"icblce", "sync", "eieio", "tlbld">: Deprecate for processors that have instructions with conflicting opcodes.	2009-04-02 13:30:56 +00:00
Peter Bergner	e401b04ca7	opcodes/ * ppc-opc.c (powerpc_opcodes) <"dcbzl">: Merge the POWER4 and E500MC entries.	2009-04-02 00:42:29 +00:00
Christophe Lyon	b8f9ee44f9	2009-04-01 Christophe Lyon <christophe.lyon@st.com> opcodes/ * arm-dis.c (print_insn): Print BE8 opcodes in little endianness. ld/testsuite/ * ld-arm/arm-elf.exp: BE8 tests expect the same output as the default ones. * ld-arm/arm-be8.d: Print opcodes in little endian. * ld-arm/farcall-thumb-arm-be8.d: Removed useless expected result. * ld-arm/farcall-arm-arm-be8.d: Likewise.	2009-04-01 15:45:13 +00:00
Joseph Myers	d460e92e41	gas/testsuite: * gas/arm/mapsecs.d, gas/arm/mapsecs.s: New. opcodes: * arm-dis.c (print_insn): Also check section matches in backwards search for mapping symbol.	2009-03-30 14:41:31 +00:00
H.J. Lu	d34b50065a	2009-03-26 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (get_valid_dis386): Abort on unhandled table.	2009-03-27 00:28:32 +00:00
Nick Clifton	02b1cb404a	* Makefile.am (BFD32_BACKENDS): Remove elf32-score and elf32-score7 files. (BFD32_BACKEND_CFILES): Likewise. (BFD64_BACKENDS): Add elf32-score and elf32-score7 files. (BFD64_BACKENDS_CFILES): Likewise. * Makefile.in: Regenerate. * config.bfd: More Score targets into BFD64 list. * configure.in: Move score vectors to 64-bit list. * targets.c: Likewise. * score-dis.c: Only compile when 64-bit bfds are enabled.	2009-03-18 16:58:33 +00:00
Alan Modra	3889c459bb	bfd/ * vms-hdr.c: Don't include alloca.h. opcodes/ * cgen-opc.c: Include alloca-conf.h rather than alloca.h. * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate.	2009-03-18 11:47:18 +00:00
Alan Modra	8d25cc3de0	include/ * alloca-conf.h: Revise based on autoconf-2.61, autoconf-2.13 documentation. bfd/ * elf32-m68hc1x.c: Include alloca-conf.h. * xsym.c: Likewise. * elf64-hppa.c: Likewise. Remove existing #if's handling alloca. * som.c: Likewise. * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. binutils/ * sysdep.h: Include alloca-conf.h instead of config.h and remove existing #if's handling alloca. * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. gas/ * as.h: Include alloca-conf.h instead of config.h and remove existing #if's handling alloca. * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. opcodes/ * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * openrisc-opc.c: Regenerate. ld/ * ld.h: Remove alloca handling.	2009-03-18 11:27:18 +00:00
Nick Clifton	34dd024a28	Add Spanish translation to gold. Update Indonesian translation for opcodes.	2009-03-10 09:21:01 +00:00
Alan Modra	69fe9ce501	include/opcode/ * ppc.h (ppc_parse_cpu): Declare. opcodes/ * ppc-dis.c: Include "opintl.h". (struct ppc_mopt, ppc_opts): New. (ppc_parse_cpu): New function. (powerpc_init_dialect): Use it. (print_ppc_disassembler_options): Dump options from ppc_opts. Internationalize message. gas/ * config/tc-ppc.c (parse_cpu): Delete. (md_parse_option, ppc_machine): Use ppc_parse_cpu. gas/testsuite/ * gas/ppc/altivec_and_spe.d (objdump): Add -Maltivec. * gas/ppc/common.d: Adjust for -Mcom not including -Mppc.	2009-03-10 06:53:46 +00:00
Nick Clifton	d11fd24905	Updated Spanish translations.	2009-03-06 12:14:40 +00:00
Alan Modra	51dec22749	bfd/ PR 6768 * configure.in: Test for ld --as-needed support. Link shared libbfd against libm. * configure: Regenerate. opcodes/ PR 6768 * configure.in: Test for ld --as-needed support. Link shared libopcodes against libm. * configure: Regenerate.	2009-03-04 02:10:34 +00:00
Alan Modra	a1f7ca36bf	missing from make dep-am commit	2009-03-04 01:16:15 +00:00
Peter Bergner	c72ab5f2c5	opcodes/ * ppc-opc.c (powerpc_opcodes): Reorder the opcode table so that instructions from newer processors are listed before older ones.	2009-03-04 01:00:53 +00:00
Alan Modra	500b1f4473	make dep-am and regen opcodes/ * Makefile.am (HFILES): Move lm32-desc.h and lm32-opc.h from.. (CFILES): ..here.	2009-03-03 02:41:14 +00:00
Nick Clifton	c3b7224ae4	Add support for Score7 architecture.	2009-03-02 10:33:08 +00:00
Ralf Wildenhues	58e2467181	Backport from git Libtool: 2009-01-19 Robert Millan <rmh@aybabtu.com> Support GNU/kOpenSolaris. * libltdl/m4/libtool.m4 (_LT_SYS_DYNAMIC_LINKER) (_LT_CHECK_MAGIC_METHOD, _LT_COMPILER_PIC, _LT_LINKER_SHLIBS) (_LT_LANG_CXX_CONFIG) [kopensolaris-gnu]: Recognize GNU/kOpenSolaris. binutils/ configure: Regenerate. opcodes/ * configure: Regenerate. bfd/ * configure: Regenerate. gas/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * configure: Regenerate.	2009-03-01 18:57:19 +00:00
H.J. Lu	d6f574e0ed	2009-02-27 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_EX): Call OP_E_memory instead of OP_E.	2009-02-27 20:13:04 +00:00
Peter Bergner	066be9f7bd	gas/ * config/tc-ppc.c (pre_defined_registers): Add "f32" to "f63", "f.32" to "f.63", "vs0" to "vs63" and "vs.0" to "vs.63". (parse_cpu): Extend -mpower7 to accept power7 and isel instructions. gas/testsuite/ * gas/ppc/e500mc.d ("wait", "waitsrv", "waitimpl"): Add tests. * gas/ppc/e500mc.s: Likewise. * gas/ppc/power6.d ("cdtbcd", "cbcdtd", "addg6s"): Add tests. * gas/ppc/power6.s: Likewise. * gas/ppc/power7.d ("lfdpx", "mffgpr", "mftgpr"): Remove invalid tests. ("wait", "waitsrv", "waitimpl", "divwe", "divwe.", "divweo", "divweo.", "divweu", "divweu.", "divweuo", "divweuo.", "bpermd", "popcntw", "popcntd", "ldbrx", "stdbrx", "lfiwzx", "lfiwzx", "fcfids", "fcfids.", "fcfidus", "fcfidus.", "fctiwu", "fctiwu.", "fctiwuz", "fctiwuz.", "fctidu", "fctidu.", "fctiduz", "fctiduz.", "fcfidu", "fcfidu.", "ftdiv", "ftdiv", "ftsqrt", "ftsqrt", "dcbtt", "dcbtstt", "dcffix", "dcffix.", "lbarx", "lbarx", "lbarx", "lharx", "lharx", "lharx", "stbcx.", "sthcx.", "fre", "fre.", "fres", "fres.", "frsqrte", "frsqrte.", "frsqrtes", "frsqrtes.", "isel"): Add tests. * gas/ppc/power7.s: Likewise. * gas/ppc/vsx.d: New test. * gas/ppc/vsx.s: Likewise. * gas/ppc/ppc.exp: Run it. include/opcode/ * ppc.h (PPC_OPCODE_POWER7): New. opcodes/ * ppc-dis.c (powerpc_init_dialect): Extend -Mpower7 to disassemble the power7 and the isel instructions. * ppc-opc.c (insert_xc6, extract_xc6): New static functions. (insert_dm, extract_dm): Likewise. (XB6): Update comment to include XX2 form. (WC, XC6, SHW, DMEX, UIM, XX2, XX3RC, XX4, XX2_MASK, XX2UIM_MASK, XX2BF_MASK, XX3BF_MASK, XX3SHW_MASK, XX4_MASK, XWC_MASK, POWER7): New. (RemoveXX3DM): Delete. (powerpc_opcodes): <"lfdp", "lfdpx", "mcrxr", "mftb", "mffgpr", "mftgpr">: Deprecate for POWER7. <"fres", "fres.", "frsqrtes", "frsqrtes.", "fre", "fre.", "frsqrte", "frsqrte.">: Deprecate the three operand form and enable the two operand form for POWER7 and later. <"wait">: Extend to accept optional parameter. Enable for POWER7. <"waitsrv", "waitimpl">: Add extended opcodes. <"ldbrx", "stdbrx">: Enable for POWER7. <"cdtbcd", "cbcdtd", "addg6s">: Add POWER6 opcodes. <"bpermd", "dcbtstt", "dcbtt", "dcffix.", "dcffix", "divde.", "divde", "divdeo.", "divdeo", "divdeu.", "divdeu", "divdeuo.", "divdeuo", "divwe.", "divwe", "divweo.", "divweo", "divweu.", "divweu", "divweuo.", "divweuo", "fcfids.", "fcfids", "fcfidu.", "fcfidu", "fcfidus.", "fcfidus", "fctidu.", "fctidu", "fctiduz.", "fctiduz", "fctiwu.", "fctiwu", "fctiwuz.", "fctiwuz", "ftdiv", "ftsqrt", "lbarx", "lfiwzx", "lharx", "popcntd", "popcntw", "stbcx.", "sthcx.">: Add POWER7 opcodes. <"lxsdux", "lxsdx", "lxvdsx", "lxvw4ux", "lxvw4x", "stxsdux", "stxsdx", "stxvw4ux", "stxvw4x", "xsabsdp", "xsadddp", "xscmpodp", "xscmpudp", "xscpsgndp", "xscvdpsp", "xscvdpsxds", "xscvdpsxws", "xscvdpuxds", "xscvdpuxws", "xscvspdp", "xscvsxddp", "xscvuxddp", "xsdivdp", "xsmaddadp", "xsmaddmdp", "xsmaxdp", "xsmindp", "xsmsubadp", "xsmsubmdp", "xsmuldp", "xsnabsdp", "xsnegdp", "xsnmaddadp", "xsnmaddmdp", "xsnmsubadp", "xsnmsubmdp", "xsrdpi", "xsrdpic", "xsrdpim", "xsrdpip", "xsrdpiz", "xsredp", "xsrsqrtedp", "xssqrtdp", "xssubdp", "xstdivdp", "xstsqrtdp", "xvabsdp", "xvabssp", "xvadddp", "xvaddsp", "xvcmpeqdp.", "xvcmpeqdp", "xvcmpeqsp.", "xvcmpeqsp", "xvcmpgedp.", "xvcmpgedp", "xvcmpgesp.", "xvcmpgesp", "xvcmpgtdp.", "xvcmpgtdp", "xvcmpgtsp.", "xvcmpgtsp", "xvcpsgnsp", "xvcvdpsp", "xvcvdpsxds", "xvcvdpsxws", "xvcvdpuxds", "xvcvdpuxws", "xvcvspdp", "xvcvspsxds", "xvcvspsxws", "xvcvspuxds", "xvcvspuxws", "xvcvsxddp", "xvcvsxdsp", "xvcvsxwdp", "xvcvsxwsp", "xvcvuxddp", "xvcvuxdsp", "xvcvuxwdp", "xvcvuxwsp", "xvdivdp", "xvdivsp", "xvmaddadp", "xvmaddasp", "xvmaddmdp", "xvmaddmsp", "xvmaxdp", "xvmaxsp", "xvmindp", "xvminsp", "xvmovsp", "xvmsubadp", "xvmsubasp", "xvmsubmdp", "xvmsubmsp", "xvmuldp", "xvmulsp", "xvnabsdp", "xvnabssp", "xvnegdp", "xvnegsp", "xvnmaddadp", "xvnmaddasp", "xvnmaddmdp", "xvnmaddmsp", "xvnmsubadp", "xvnmsubasp", "xvnmsubmdp", "xvnmsubmsp", "xvrdpi", "xvrdpic", "xvrdpim", "xvrdpip", "xvrdpiz", "xvredp", "xvresp", "xvrspi", "xvrspic", "xvrspim", "xvrspip", "xvrspiz", "xvrsqrtedp", "xvrsqrtesp", "xvsqrtdp", "xvsqrtsp", "xvsubdp", "xvsubsp", "xvtdivdp", "xvtdivsp", "xvtsqrtdp", "xvtsqrtsp", "xxland", "xxlandc", "xxlnor", "xxlor", "xxlxor", "xxmrghw", "xxmrglw", "xxsel", "xxsldwi", "xxspltd", "xxspltw", "xxswapd">: Add VSX opcodes.	2009-02-26 22:07:33 +00:00
H.J. Lu	4c664d7bf7	gas/ 2009-02-23 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (vex_imm4): Removed. (VEX_check_operands): Likewise. (match_template): Updated. opcodes/ 2009-02-23 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEX_IMM4. (operand_types): Remove Vex_Imm4. * i386-opc.h (Vex_Imm4): Removed. (OTMax): Updated. (i386_operand_type): Remove vex_imm4. * i386-opc.tbl: Remove Vex_Imm4 comments. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	2009-02-23 20:41:46 +00:00
Richard Earnshaw	4ce8808b2c	* arm-dis.c (neon_opcodes): Correct bit-mask and patterns for vq{r}shr{u}n.s64 insnstructions.	2009-02-23 14:58:34 +00:00
Peter Bergner	0e55be1624	gas/testsuite/ * gas/ppc/e500mc.d ("lfdepx", "stfdepx"): Fix tests to expect a floating point register. opcodes/ * ppc-opc.c (powerpc_opcodes) <"lfdepx", "stfdepx">: Fix the first operand to be a float point register (FRT/FRS).	2009-02-19 21:18:46 +00:00
Adam Nemet	b1c9882d1b	opcodes/ * mips-opc.c (mips_builtin_opcodes): Move the Octeon-specific dmfc2 and dmtc2 before the architecture-level variants. gas/testsuite/ * gas/mips/octeon.s: Add more tests for dmfc2 and dmtc2. * gas/mips/octeon.d: Update. * gas/mips/octeon-ill.l: Update error message.	2009-02-18 20:51:59 +00:00
Nick Clifton	137f2437e0	* fr30-opc.c: Regenerate. * frv-opc.c: Regenerate. * ip2k-opc.c: Regenerate. * iq2000-opc.c: Regenerate. * lm32-opc.c: Regenerate. * m32c-opc.c: Regenerate. * m32r-opc.c: Regenerate. * mep-opc.c: Regenerate. * mt-opc.c: Regenerate. * xc16x-opc.c: Regenerate. * xstormy16-opc.c: Regenerate. * tic54x-dis.c (print_instruction): Avoid compiler warning on sprintf call. * opc-itab.scm (<>_cgen_init_opcode_table): Avoid compiler warning about calling memset with a zero length.	2009-02-18 17:13:04 +00:00
Nathan Sidwell	872989673f	gas/ * config/tc-m68k.c (mcf51qe_ctrl): Add CPUCR. (mcf52259_ctrl, mcf52277_ctrl, mcf53017_ctrl): New. (mcf5307_ctrl): Add VBR. (no_mac): New variable. (m68k_extensions): Refer to no_mac mask. (m68k_cpus): Add 51, 51ac, 51cn, 51em, 51jm, 52274, 52277, 52252..52259, 53011..53017. (m68k_ip): Process CPUCR. (init_table): Add cpucr entry. (m68k_set_extension): Allow negated mask to refer to a variable. (md_show_usage): Use '%s' to silence fprintf warning. * config/m68k-parse.h (CPUCR): New control register. gas/testsuite/ * m68k/br-isac.d, m68k/br-isac.s: Add stldsr test. opcodes/ * m68k-opc.c (m68k_opcodes): Add stldsr instruction.	2009-02-12 08:31:03 +00:00
Peter Bergner	80890a619b	gas/testsuite/ * gas/ppc/booke.s ("dcbt", "dcbtst"): New tests. * gas/ppc/booke.d: Likewise. * gas/ppc/power4_32.s: Likewise. * gas/ppc/power4_32.d: Likewise. opcodes/ * ppc-opc.c: Update copyright year. (powerpc_opcodes) <"dcbt", "dcbtst">: Deprecate the Embedded operand ordering for POWER4 and later and use the correct Server ordering.	2009-02-06 01:50:54 +00:00
H.J. Lu	ce2f5b3ce7	gas/ 2009-02-04 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (January, 2009) * config/tc-i386.c (CPU_FLAGS_PCLMUL_MATCH): New. (CPU_FLAGS_AVX_MATCH): Updated. (CPU_FLAGS_32BIT_MATCH): Likewise. (cpu_flags_match): Likewise. gas/testsuite/ 2009-02-04 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (January, 2009) * gas/i386/arch-avx-1-3.l: New. * gas/i386/arch-avx-1-3.s: Likewise. * gas/i386/arch-avx-1-4.l: Likewise. * gas/i386/arch-avx-1-4.s: Likewise. * gas/i386/arch-avx-1-5.l: Likewise. * gas/i386/arch-avx-1-5.s: Likewise. * gas/i386/arch-avx-1-6.l: Likewise. * gas/i386/arch-avx-1-6.s: Likewise. * gas/i386/arch-10.s: Add vpclmul instructions. * gas/i386/arch-avx-1.s: Likewise. * gas/i386/avx.s: Likewise. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/x86-64-avx.s: Likewise. * gas/i386/sse2avx.s: Add pclmul instructions. * gas/i386/x86-64-sse2avx.s: Likewise. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/arch-avx-1.d: Likewise. * gas/i386/arch-avx-1-1.l: Likewise. * gas/i386/arch-avx-1-2.l: Likewise. * gas/i386/avx.d: Likewise. * gas/i386/avx-intel.d: Likewise. * gas/i386/sse2avx.d: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. * gas/i386/x86-64-sse2avx.d: Likewise. * gas/i386/i386.exp: Run arch-avx-1-3, arch-avx-1-4, arch-avx-1-5 and arch-avx-1-6. opcodes/ 2009-02-04 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (January, 2009) * i386-dis.c (PREFIX_VEX_3A44): New. (VEX_LEN_3A44_P_2): Likewise. (PREFIX_VEX_3A48): Updated. (VEX_LEN_3A4C_P_2): Likewise. (prefix_table): Add PREFIX_VEX_3A44. (vex_table): Likewise. (vex_len_table): Add VEX_LEN_3A44_P_2. * i386-opc.tbl: Add PCLMUL + AVX instructions. * i386-tbl.h: Regenerated.	2009-02-04 16:03:31 +00:00
Joseph Myers	52b6b6b972	bfd: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * aoutx.h (NAME (aout, machine_type)): Handle bfd_mach_mips_xlr. * archures.c (bfd_mach_mips_xlr): Define. * bfd-in2.h: Regenerate. * cpu-mips.c (I_xlr): Define. (arch_info_struct): Add XLR entry. * elfxx-mips.c (_bfd_elf_mips_mach): Handle E_MIPS_MACH_XLR. (mips_set_isa_flags): Handle bfd_mach_mips_xlr (mips_mach_extensions): Add XLR entry. binutils: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * readelf.c (get_machine_flags): Handle E_MIPS_MACH_XLR. gas: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * config/tc-mips.c (macro): Handle M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT and M_MSGWAIT_T. (mips_cpu_info_table): Add XLR entry. * doc/c-mips.texi (-march): Document xlr. gas/testsuite: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * gas/mips/mips.exp (xlr): New architecture. (xlr-ext): Run test. * gas/mips/xlr-ext.d, gas/mips/xlr-ext.s: New. include/elf: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * mips.h (E_MIPS_MACH_XLR): Define. include/opcode: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * mips.h (INSN_XLR): Define. (INSN_CHIP_MASK): Update. (CPU_XLR): Define. (OPCODE_IS_MEMBER): Update. (M_MSGSND, M_MSGLD, M_MSGLD_T, M_MSGWAIT, M_MSGWAIT_T): Define. opcodes: 2009-02-03 Sandip Matte <sandip@rmicorp.com> * mips-dis.c (mips_cp0_names_xlr, mips_cp0sel_names_xlr): Define. (mips_arch_choices): Add XLR entry. * mips-opc.c (XLR): Define. (mips_builtin_opcodes): Add XLR instructions.	2009-02-03 18:16:04 +00:00
Joseph Myers	31dd3154f4	bfd: 2009-02-03 Carlos O'Donell <carlos@codesourcery.com> * configure.in: AC_SUBST pdfdir. * Makefile.am: Add install-pdf, install-pdf-am and install-pdf-recursive targets. Define pdfdir. * doc/Makefile.am: Define pdf__strip_dir. Add install-pdf and install-pdf-am targets. * po/Make-in: Add install-pdf target. * configure: Regenerate. * Makefile.in: Regenerate * doc/Makefile.in: Regenerate. binutils: 2009-02-03 Carlos O'Donell <carlos@codesourcery.com> * configure.in: AC_SUBST pdfdir. * Makefile.am: Add install-pdf, install-pdf-am, and install-pdf-recursive targets. * doc/Makefile.am: Define pdf__strip_dir. Add install-pdf and install-pdf-am targets. * po/Make-in: Add install-pdf target. * configure: Regenerate. * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. etc: 2009-02-03 Carlos O'Donell <carlos@codesourcery.com> * configure.in: AC_SUBST pdfdir. * configure: Regenerate. gas: 2009-02-03 Carlos O'Donell <carlos@codesourcery.com> * configure.in: AC_SUBST pdfdir. * Makefile.am: Add install-pdf, install-pdf-am, and install-pdf-recursive targets. * doc/Makefile.am: Define pdf__strip_dir. Add install-pdf and install-pdf-am targets. * po/Make-in: Add install-pdf target. * configure: Regenerate. * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. gprof: 2009-02-03 Carlos O'Donell <carlos@codesourcery.com> * configure.in: AC_SUBST pdfdir. * Makefile.am: Add install-pdf, install-pdf-am, and install-pdf-recursive targets. Define pdf__strip_dir. * po/Make-in: Add install-pdf target. * configure: Regenerate. * Makefile.in: Regenerate. ld: 2009-02-03 Carlos O'Donell <carlos@codesourcery.com> * configure.in: AC_SUBST pdfdir. * Makefile.am: Add install-pdf, install-pdf-am, and install-pdf-recursive targets. Define pdf__strip_dir. * po/Make-in: Add install-pdf target. * configure: Regenerate. * Makefile.in: Regenerate. opcodes: 2009-02-03 Carlos O'Donell <carlos@codesourcery.com> * Makefile.am: Add install-pdf target. * po/Make-in: Add install-pdf target. * Makefile.in: Regenerate.	2009-02-03 15:54:05 +00:00
DJ Delorie	c1a0a41faa	* elf32-mep.c (config_names): Regenerate configuration. * mep-asm.c: Regenerate. * mep-desc.c: Regenerate. * mep-desc.h: Regenerate. * mep-dis.c: Regenerate. * mep-ibld.c: Regenerate. * mep-opc.c: Regenerate. * mep-opc.h: Regenerate.	2009-02-03 02:15:57 +00:00
Joseph Myers	087b80de6e	gas: 2009-01-29 Mark Mitchell <mark@codesourcery.com> * config/tc-arm.c (insns): Correct encoding of qadd, qdadd, qsub, qdsub in Thumb-2 mode. gas/testsuite: 2009-01-29 Mark Mitchell <mark@codesourcery.com> * gas/arm/thumb32.s (qadd): Add qadd, qdadd, qsub, and qdsub. * gas/arm/thumb32.d: Likewise. opcodes: 2009-01-29 Mark Mitchell <mark@codesourcery.com> * arm-dis.c (thumb32_opcodes): Correct decoding for qadd, qdadd, qsub, and qdsub.	2009-01-29 11:48:34 +00:00
Nick Clifton	159073e6aa	* mips-opc.c (suxc1): Add the flag of FP_D.	2009-01-28 08:45:47 +00:00
Alan Modra	6f3b91a621	Regenerate for copyright date update.	2009-01-20 07:22:30 +00:00
Alan Modra	29670fb929	bfd/ * Makefile.am (libbfd_la_LIBADD, libbfd_la_LDFLAGS): Substitute SHARED_LIBADD and SHARED_LDFLAGS rather than WIN32LIBADD, WIN32LDFLAGS. * configure.in (commonbfdlib): Delete. (SHARED_LDFLAGS): Rename from WIN32LDFLAGS/ (SHARED_LIBADD): Rename from WIN32LIBADD. Add pic libiberty if such is available, not just for linux. * po/SRC-POTFILES.in: Regenerate. * Makefile.in: Regenerate. * configure: Regenerate. opcodes/ * configure.in (commonbfdlib): Delete. (SHARED_LIBADD): Add pic libiberty if such is available. * configure: Regenerate. * po/POTFILES.in: Regenerate. binutils/ * configure.in (commonbfdlib): Delete. * configure: Regenerate. gas/ * configure.in (commonbfdlib): Delete. * configure: Regenerate. * po/POTFILES.in: Regenerate.	2009-01-16 08:02:29 +00:00
Peter Bergner	21169fcfad	opcodes/ * ppc-dis.c (print_insn_powerpc): Skip insn if it is deprecated. * ppc-opc.c (powerpc_opcodes) <mtfsf, mtfsf.>: Deprecate the two operand form and enable the four operand form for POWER6 and later. <mtfsfi, mtfsfi.>: Deprecate the two operand form and enable the three operand form for POWER6 and later. gas/testsuite/ * gas/ppc/power6.s ("mtfsf", "mtfsf.", "mtfsfi", "mtfsfi."): Add tests. * gas/ppc/power6.d: Likewise.	2009-01-15 04:27:28 +00:00
Mike Frysinger	4ca47a519d	2009-01-14 Mike Frysinger <vapier@gentoo.org> * bfin-dis.c (OUTS): Use "%s" as format string.	2009-01-14 19:35:12 +00:00
H.J. Lu	8acd537727	2009-01-13 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Remove a white space. (operand_type_init): Likewise.	2009-01-14 00:42:07 +00:00
H.J. Lu	c1ec187589	gas/testsuite/ 2009-01-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/sse-noavx.s: Add tests for lfence, mfence and movnti. * gas/i386/x86-64-sse-noavx.s: Likewise. * gas/i386/sse-noavx.d: Updated. * gas/i386/x86-64-sse-noavx.d: Likewise. opcodes/ 2009-01-12 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add NoAVX to movnti, lfence and mfence. * i386-tbl.h: Regenerated.	2009-01-13 00:00:35 +00:00
H.J. Lu	c7532693f2	gas/testsuite/ 2009-01-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/opts.s: Add tests for add, adc, and, cmp, or, sbb, sub and xor. * gas/i386/x86-64-opts.s: Likewise. * gas/i386/opts.d: Updated. * gas/i386/opts-intel.d: Likewise. * gas/i386/x86-64-opts.d: Likewise. * gas/i386/x86-64-opts-intel.d: Likewise. opcodes/ 2009-01-12 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (dis386): Use EbS on addB, orB, adcB, sbbB, andB, subB, xorB and cmpB. Use EvS on addS, orS, adcS, sbbS, andS, subS, xorS and cmpS.	2009-01-12 16:04:11 +00:00
H.J. Lu	bd5295b282	gas/ 2009-01-10 H.J. Lu <hongjiu.lu@intel.com> * gas/config/tc-i386.c (cpu_arch): Add corei7, .clflush and .syscall. (i386_align_code): Handle PROCESSOR_COREI7. (md_show_usage): Add corei7, clflush and syscall. (i386_target_format): Replace cpup4 with cpuclflush. * gas/config/tc-i386.h (processor_type): Add PROCESSOR_COREI7. * doc/c-i386.texi: Document corei7, clflush and syscall. gas/testsuite/ 2009-01-10 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-10.s: Add clflush and syscall. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. opcodes/ 2009-01-10 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Replace CpuP4 and CpuK6 with CpuClflush and CpuSYSCALL, respectively. Remove CpuK8. Add CPU_COREI7_FLAGS, CPU_CLFLUSH_FLAGS and CPU_SYSCALL_FLAGS. (cpu_flags): Remove CpuP4, CpuK6 and CpuK8. Add CpuClflush and CpuSYSCALL. (lineno): Removed. (set_bitfield): Take an argument, lineno. Don't report lineno on error if it is -1. (process_i386_cpu_flag): Take an argument, lineno. (process_i386_opcode_modifier): Likewise. (process_i386_operand_type): Likewise. (output_i386_opcode): Likewise. (opcode_hash_entry): Add lineno. (process_i386_opcodes): Updated. (process_i386_registers): Likewise. (process_i386_initializers): Likewise. * i386-opc.h (CpuP4): Removed. (CpuK6): Likewise. (CpuK8): Likewise. (CpuClflush): New. (CpuSYSCALL): Likewise. (CpuMMX): Updated. (i386_cpu_flags): Remove cpup4, cpuk6 and cpuk8. Add cpuclflush and cpusyscall. * i386-opc.tbl: Update movnti, clflush, lfence, mfence, pause, syscall and sysret. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	2009-01-10 17:25:52 +00:00
H.J. Lu	1b7f3fb0dd	gas/ 2009-01-09 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch): Add .rdtscp. (md_show_usage): Display rdtscp. * doc/c-i386.texi: Document rdtscp. gas/testsuite/ 2009-01-09 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-10.s: Add rdtscp. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. opcodes/ 2009-01-09 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Add CpuRdtscp to CPU_K8_FLAGS and CPU_AMDFAM10_FLAGS. Add CPU_RDTSCP_FLAGS. (cpu_flags): Add CpuRdtscp. (set_bitfield): Remove CpuSledgehammer check. * i386-opc.h (CpuRdtscp): New. (CpuLM): Updated. (i386_cpu_flags): Add cpurdtscp. * i386-opc.tbl: Replace CpuSledgehammer with CpuRdtscp. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	2009-01-09 20:32:32 +00:00
Peter Bergner	1cb0a76746	gas/ * config/tc-ppc.c (ppc_setup_opcodes): Remove PPC_OPCODE_NOPOWER4 test. Test the new "deprecated" opcode field. include/opcode/ * ppc.h (struct powerpc_opcode): New field "deprecated". (PPC_OPCODE_NOPOWER4): Delete. opcodes/ * ppc-opc.c (PPCNONE): Define. (NOPOWER4): Delete. (powerpc_opcodes): Initialize the new "deprecated" field.	2009-01-09 18:50:58 +00:00
H.J. Lu	168e309712	gas/testsuite/ 2009-01-06 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (December, 2008) * gas/i386/avx.s: Add tests for 256bit vmovntdq, vmovntpd and vmovntps. * gas/i386/x86-64-avx.s: Likewise. * gas/i386/avx.d: Updated. * gas/i386/avx-intel.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. opcodes/ 2009-01-06 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (December, 2008) * i386-dis.c (VEX_LEN_2B_M_0): Removed. (VEX_LEN_E7_P_2_M_0): Likewise. (VEX_LEN_2C_P_1): Updated. (VEX_LEN_E8_P_2): Likewise. (vex_len_table): Remove VEX_LEN_2B_M_0 and VEX_LEN_E7_P_2_M_0. (mod_table): Likewise. * i386-opc.tbl: Add 256bit vmovntdq, vmovntpd and vmovntps. * i386-tbl.h: Regenerated.	2009-01-06 17:15:28 +00:00
H.J. Lu	22da050bbf	2009-01-05 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (process_copyright): Update for 2009. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	2009-01-06 01:14:45 +00:00
H.J. Lu	0bfee64967	gas/ 2009-01-05 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (December, 2008) * config/tc-i386.c (build_modrm_byte): Remove 5 operand instruction support. Don't swap REG and NDS for FMA. gas/testsuite/ 2009-01-05 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (December, 2008) * gas/i386/arch-10.s: Replace vfmaddpd with vfmadd132pd. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/avx.d: Likewise. * gas/i386/avx-intel.d: Likewise. * gas/i386/inval-avx.l: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. * gas/i386/x86-64-inval-avx.l: Likewise. * gas/i386/avx.s: Remove vpermil2ps/vpermil2pd and FMA instructions. Update tests. * gas/i386/inval-avx.s: Likewise. * gas/i386/x86-64-avx.s: Likewise. * gas/i386/x86-64-inval-avx.s: Likewise. * gas/i386/fma.d: New. * gas/i386/fma.s: Likewise. * gas/i386/fma-intel.d: Likewise. * gas/i386/x86-64-fma.d: Likewise. * gas/i386/x86-64-fma.s: Likewise. * gas/i386/x86-64-fma-intel.d: Likewise. * gas/i386/i386.exp: Run fma, fma-intel, x86-64-fma and x86-64-fma-intel. opcodes/ 2009-01-05 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (December, 2008) * i386-dis.c (OP_VEX_FMA): Removed. (OP_EX_VexW): Likewise. (OP_EX_VexImmW): Likewise. (OP_XMM_VexW): Likewise. (VEXI4_Fixup): Likewise. (VPERMIL2_Fixup): Likewise. (VexI4): Likewise. (VexFMA): Likewise. (Vex128FMA): Likewise. (EXVexW): Likewise. (EXdVexW): Likewise. (EXqVexW): Likewise. (EXVexImmW): Likewise. (XMVexW): Likewise. (VPERMIL2): Likewise. (PREFIX_VEX_3A48...PREFIX_VEX_3A4A): Likewise. (PREFIX_VEX_3A5C...PREFIX_VEX_3A5F): Likewise. (PREFIX_VEX_3A68...PREFIX_VEX_3A6F): Likewise. (PREFIX_VEX_3A78...PREFIX_VEX_3A7F): Likewise. (VEX_LEN_3A6A_P_2...VEX_LEN_3A6F_P_2): Likewise. (VEX_LEN_3A7A_P_2...VEX_LEN_3A7F_P_2): Likewise. (get_vex_imm8): Likewise. (OP_EX_VexReg): Likewise. vpermil2_op): Likewise. (EXVexWdq): New. (vex_w_dq_mode): Likewise. (PREFIX_VEX_3896...PREFIX_VEX_389F): Likewise. (PREFIX_VEX_38A6...PREFIX_VEX_38AF): Likewise. (PREFIX_VEX_38B6...PREFIX_VEX_38BF): Likewise. (es_reg): Updated. (PREFIX_VEX_38DB): Likewise. (PREFIX_VEX_3A4A): Likewise. (PREFIX_VEX_3A60): Likewise. (PREFIX_VEX_3ADF): Likewise. (VEX_LEN_3ADF_P_2): Likewise. (prefix_table): Remove PREFIX_VEX_3A48...PREFIX_VEX_3A4A, PREFIX_VEX_3A5C...PREFIX_VEX_3A5F, PREFIX_VEX_3A68...PREFIX_VEX_3A6F and PREFIX_VEX_3A78...PREFIX_VEX_3A7F. Add PREFIX_VEX_3896...PREFIX_VEX_389F, PREFIX_VEX_38A6...PREFIX_VEX_38AF and PREFIX_VEX_38B6...PREFIX_VEX_38BF. (vex_table): Likewise. (vex_len_table): Remove VEX_LEN_3A6A_P_2...VEX_LEN_3A6F_P_2 and VEX_LEN_3A7A_P_2...VEX_LEN_3A7F_P_2. (putop): Support "%XW". (intel_operand_size): Handle vex_w_dq_mode. * i386-opc.h (VexNDS): Add a comment for VEX NDS and VEX DDS. * i386-opc.tbl: Remove vpermil2pd/vpermil2ps and old FMA instructions. Add new FMA instructions. * i386-tbl.h: Regenerated.	2009-01-06 01:03:27 +00:00
Nick Clifton	4ef2cf8be8	* or32-opc.c (or32_print_register, or32_print_immediate, disassemble_insn): Don't rely on undefined sprintf behaviour. * itbl-ops.c (itbl_disassemble): Don't rely on undefined sprintf behaviour.	2009-01-02 14:21:54 +00:00
Martin Schwidefsky	03a9f008a5	2008-12-30 Martin Schwidefsky <schwidefskyy@de.ibm.com> * s390-opc.txt: Add ptff instruction.	2008-12-30 10:00:47 +00:00
Jan Kratochvil	dffece59b8	Fix the LM32 port entry timestamp for the time of its application.	2008-12-24 10:06:43 +00:00
Jan Kratochvil	828c0124d0	opcodes/ * Makefile.am (CFILES, ALL_MACHINES): Add LM32 source and object files. * Makefile.in: Regenerate.	2008-12-24 09:58:03 +00:00
Nick Clifton	84e94c9023	Add LM32 port.	2008-12-23 19:10:25 +00:00
H.J. Lu	fa99fab222	gas/ 2008-12-23 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (match_template): Changed to return const template . Handle i.swap_operand for 3 operands. (build_vex_prefix): Take const template . Swap operand for 2-byte VEX prefix if possible. (md_assemble): Updated. (build_modrm_byte): Handle RegMem bit for SSE2AVX. gas/testsuite/ 2008-12-23 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run x86-64-avx-swap and x86-64-avx-swap-intel. * gas/i386/opts.s: Add tests for movsd, movss, vmovsd and vmovss. * gas/i386/x86-64-opts.s: Likewise. * gas/i386/opts.d: Updated. * gas/i386/opts-intel.d: Likewise. * gas/i386/sse2avx-opts.d: Likewise. * gas/i386/sse2avx-opts-intel.d: Likewise. * gas/i386/x86-64-opts.d: Likewise. * gas/i386/x86-64-opts-intel.d: Likewise. * gas/i386/x86-64-sse2avx-opts.d: Likewise. * gas/i386/x86-64-sse2avx-opts-intel.d: Likewise. * gas/i386/x86-64-avx-swap.d: New. * gas/i386/x86-64-avx-swap.s: Likewise. * gas/i386/x86-64-avx-swap-intel.d: Likewise. opcodes/ 2008-12-23 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (EXdS): New. (EXdVexS): Likewise. (EXqVexS): Likewise. (d_swap_mode): Likewise. (q_mode): Updated. (prefix_table): Use EXdS on movss and EXqS on movsd. (vex_len_table): Use EXdVexS on vmovss and EXqVexS on vmovsd. (intel_operand_size): Handle d_swap_mode. (OP_EX): Likewise. * i386-opc.h (S): Update comments. * i386-opc.tbl: Add S to movss, movsd, vmovss and vmovsd. * i386-tbl.h: Regenerated.	2008-12-23 15:14:15 +00:00
Nick Clifton	b06f3b1b03	* po/ga.po: Updated Irish translation.	2008-12-23 09:54:26 +00:00
Ralf Wildenhues	22e8c8e0c1	Add missing ChangeLog entries for my last commit.	2008-12-21 12:45:53 +00:00
H.J. Lu	b6169b206a	gas/ 2008-12-20 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (_i386_insn): Add swap_operand. (parse_insn): Handle ".s". (match_template): Handle swap_operand. * doc/c-i386.texi: Document .s suffix. gas/testsuite/ 2008-12-20 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run opts, opts-intel, sse2avx-opts, sse2avx-opts-intel, x86-64-opts, x86-64-opts-intel, x86-64-sse2avx-opts and x86-64-sse2avx-opts-intel. * gas/i386/opts.d: New. * gas/i386/opts-intel.d: Likewise. * gas/i386/opts.s: Likewise. * gas/i386/sse2avx-opts.d: Likewise. * gas/i386/sse2avx-opts-intel.d: Likewise. * gas/i386/x86-64-opts.d: Likewise. * gas/i386/x86-64-opts-intel.d: Likewise. * gas/i386/x86-64-opts.s: Likewise. * gas/i386/x86-64-sse2avx-opts.d: Likewise. * gas/i386/x86-64-sse2avx-opts-intel.d: Likewise. opcodes/ 2008-12-20 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (EbS): New. (EvS): Likewise. (EMS): Likewise. (EXqS): Likewise. (EXxS): Likewise. (b_swap_mode): Likewise. (v_swap_mode): Likewise. (q_swap_mode): Likewise. (x_swap_mode): Likewise. (v_mode): Updated. (w_mode): Likewise. (t_mode): Likewise. (xmm_mode): Likewise. (swap_operand): Likewise. (dis386): Use EbS on movB. Use EvS on moveS. (dis386_twobyte): Use EXxS on movapX. (prefix_table): Use EXxS on movups, movupd, movdqu, movdqa, vmovups, vmovdqu, vmovdqa. Use EMS and EXqS on movq. (vex_table): Use EXxS on vmovapX. (vex_len_table): Use EXqS on vmovq. (intel_operand_size): Handle b_swap_mode, v_swap_mode, q_swap_mode and x_swap_mode. (OP_E_register): Handle b_swap_mode and v_swap_mode. (OP_EM): Handle v_swap_mode. (OP_EX): x_swap_mode and q_swap_mode. * i386-gen.c (opcode_modifiers): Add S. * i386-opc.h (S): New. (Modrm): Updated. (i386_opcode_modifier): Add s. * i386-opc.tbl: Add S to movapd, movaps, movdqa, movdqu, movq, movupd, movups, vmovapd, vmovaps, vmovdqa, vmovdqu and vmovq. * i386-tbl.h: Regenerated.	2008-12-20 17:40:51 +00:00
H.J. Lu	ea397f5b07	gas/testsuite/ 2008-12-18 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/intel.d: Remove trailing white spaces after nop. * gas/i386/intelpic.d: Likewise. * gas/i386/nops16-1.d: Likewise. * gas/i386/nops-1-i686.d: Likewise. * gas/i386/nops-3.d: Likewise. * gas/i386/nops-3-i386.d: Likewise. * gas/i386/nops-3-i686.d: Likewise. * gas/i386/nops-4.d: Likewise. * gas/i386/nops-4-i386.d: Likewise. * gas/i386/nops-4-i686.d: Likewise. * gas/i386/opcode.d: Likewise. * gas/i386/opcode-suffix.d: Likewise. * gas/i386/reloc.d: Likewise. * gas/i386/tlsnopic.d: Likewise. * gas/i386/x86-64-nops-1.d: Likewise. * gas/i386/x86-64-nops-1-nocona.d: Likewise. * gas/i386/x86-64-nops-2.d: Likewise. * gas/i386/x86-64-nops-3.d: Likewise. * gas/i386/x86-64-nops-4-core2.d: Likewise. * gas/i386/x86-64-nops-4.d: Likewise. * gas/i386/x86-64-nops-4-k8.d: Likewise. * gas/i386/x86-64-opcode.d: Likewise. ld/testsuite/ 2008-12-18 H.J. Lu <hongjiu.lu@intel.com> * ld-i386/tlsld1.dd: Remove trailing white spaces after nop. opcodes/ 2008-12-18 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (mnemonicendp): New. (op): Likewise. (print_insn): Use mnemonicendp. (OP_3DNowSuffix): Likewise. (CMP_Fixup): Likewise. (CMPXCHG8B_Fixup): Likewise. (CRC32_Fixup): Likewise. (OP_DREX_FCMP): Likewise. (OP_DREX_ICMP): Likewise. (VZERO_Fixup): Likewise. (VCMP_Fixup): Likewise. (PCLMUL_Fixup): Likewise. (VPERMIL2_Fixup): Likewise. (MOVBE_Fixup): Likewise. (putop): Update mnemonicendp. (oappend): Use stpcpy. (simd_cmp_op): Changed to struct op. (vex_cmp_op): Likewise. (pclmul_op): Likewise. (vpermil2_op): Likewise.	2008-12-18 22:47:32 +00:00
Ralf Wildenhues	3914465446	Backport link test fix from upstream Libtool: * libltdl.m4 (_LT_SYS_DYNAMIC_LINKER, _LT_LINKER_SHLIBS): Add cache variables to tests that require the linker to work. For shlibpath_overrides_runpath, this also changes the semantics to let the result from the C compiler take precedence. compiler take precedence. binutils/ * configure: Regenerate. opcodes/ * configure: Regenerate. bfd/ * configure: Regenerate. gas/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * configure: Regenerate.	2008-12-18 21:36:47 +00:00
Richard Earnshaw	7df76b802e	opcodes: * arm-dis.c (coprocessor_opcodes): Disassemble VFP instructions using unified syntax. gas/testsuite: * gas/arm/group-reloc-ldc.d: Disassembly of VFP instructions now uses unified syntax. * gas/arm/vfp-non-overlap.d: Likewise. * gas/arm/vfp-neon-syntax.d: Likewise. * gas/arm/vfp-neon-syntax_t2.d: Likewise. * gas/arm/vfp1.d: Likewise. * gas/arm/vfp1_t2.d: Likewise. * gas/arm/vfp1xD.d: Likewise. * gas/arm/vfp1xD_t2.d: Likewise. * gas/arm/vfp2.d: Likewise. * gas/arm/vfp2_t2.d: Likewise. * gas/arm/vfpv3-32drs.d: Likewise. * gas/arm/vfpv3-const-conv.d: Likewise. ld/testsuite: * ld-arm/vfp11-fix-scalar.d: Disassembly of VFP instructions now uses unified syntax. * ld-arm/vfp11-fix-vector.d: Likewise.	2008-12-15 17:24:13 +00:00
H.J. Lu	035475035d	2008-12-08 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Move VexNDS before VexNDD.	2008-12-08 18:07:26 +00:00
H.J. Lu	efa7dee728	2008-12-08 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (putop): Remove strayed comments.	2008-12-08 17:43:06 +00:00
Ben Elliston	2f3bb96af7	opcodes/ * ppc-dis.c (powerpc_init_dialect): Do not set PPC_OPCODE_BOOKE for -Mbooke. (print_ppc_disassembler_options): Update usage. * ppc-opc.c (DE, DES, DEO, DE_MASK): Remove. (BOOKE64): Remove. (PPCCHLK64): Likewise. (powerpc_opcodes): Remove all BOOKE64 instructions. gas/ * config/tc-ppc.c (parse_cpu): Remove booke64 support. Update usage strings. (ppc_setup_opcodes): Likewise, remove booke64 support. * doc/c-ppc.texi (PowerPC-Opts): Remove -mbooke32 and -mbooke64. * doc/as.texinfo (Overview): Likewise. binutils/ * doc/binutils.texi (objdump): Update booke documentation. * NEWS: Document user-visible changes to command line options.	2008-12-04 10:29:16 +00:00
Thiemo Seufer	3aa3176b2d	* aoutx.h (NAME): Add case statements for bfd_mach_mips14000, bfd_mach_mips16000. * archures.c (bfd_architecture): Add .#defines for bfd_mach_mips14000, bfd_mach_mips16000. * bfd-in2.h: Regenerate. * cpu-mips.c: Add enums I_mips14000, I_mips16000. (arch_info_struct): Add refs to R14000, R16000. * elfxx-mips.c (mips_set_isa_flags): Handle bfd_mach_mips14000, bfd_mach_mips16000. (mips_mach_extensions): Map R14000, R16000 to R10000. * config/tc-mips.c (hilo_interlocks): Handle CPU_R14000, CPU_R16000. (mips_cpu_info_table): Add r14000, r16000. * doc/c-mips.texi: Add entries for 14000, 16000. * mips-dis.c (mips_arch_choices): Add r14000, r16000. * mips.h: Define CPU_R14000, CPU_R16000. (OPCODE_IS_MEMBER): Include R14000, R16000 in test.	2008-11-28 18:02:17 +00:00
M R Swami Reddy	59b098c970	* cr16-dis.c (match_opcode): Truncate mcode to 32 bit and adjusted the mask for 32-bit branch instruction.	2008-11-27 11:30:33 +00:00
Alan Modra	e1c93c699b	* ppc-opc.c (extract_sprg): Correct operand range check.	2008-11-27 10:47:23 +00:00
Andreas Schwab	3c6528a8d8	Fix typo.	2008-11-26 10:49:06 +00:00
Andreas Schwab	9f7678f6ca	(NEXTBYTE, NEXTWORD, NEXTLONG, NEXTULONG, NEXTSINGLE) (NEXTDOUBLE, NEXTEXTEND, NEXTPACKED): Fix error handling. (save_printer, save_print_address): Remove. (fetch_data): Don't use them. (match_insn_m68k): Always restore printing functions. (print_insn_m68k): Don't save/restore printing functions.	2008-11-26 10:43:18 +00:00
Nick Clifton	62443ade10	* m68k-dis.c: Rewrite to remove use of setjmp/longjmp.	2008-11-25 10:33:06 +00:00
Catherine Moore	8e79c3df51	Add support for ARM half-precision conversion instructions.	2008-11-18 15:45:05 +00:00
Tristan Gingold	d387240a63	bfd/ 2008-11-14 Tristan Gingold <gingold@adacore.com> * configure.com: Handle bfd_default_target_size, BFD_HOST_LONG_LONG, BFD_HOST_64BIT_LONG_LONG, BFD_HOSTPTR_T, bfd_file_ptr. Generate bfdver.h. * vms-hdr.c (_bfd_vms_write_hdr): Use strdup/free instead of alloca. * hosts/alphavms.h: Defines macros to bypass i18n. * makefile.vms (OBJS): Update file list. (DEFS): Remove VMS_DEBUG, const, add DEBUGDIR. (CFLAGS): Update flags. * bfdio.c (real_fopen): Add code specific to VMS: extract attributes from modes. binutils/ 2008-11-14 Tristan Gingold <gingold@adacore.com> * configure.com: Get version from configure.in of bfd. * makefile.vms-in (DEBUG_OBJS): Add dwarf.obj. (CFLAGS): Update flags. include/ 2008-11-14 Tristan Gingold <gingold@adacore.com> * fopen-vms.h (FOPEN_RB): Use a single string to match the standard prototype. (FOPEN_WB): Ditto. (FOPEN_AB): Ditto. (FOPEN_RUB): Ditto. (FOPEN_WUB): Ditto. (FOPEN_AUB): Ditto. libiberty/ 2008-11-14 Tristan Gingold <gingold@adacore.com> * makefile.vms (OBJS): Update objects list. (CFLAGS): Update. (libiberty.olb): Remove alloca-conf.h dependency. * config.h-vms: Use new macro sets, use builtin alloca. opcodes/ 2008-11-14 Tristan Gingold <gingold@adacore.com> * makefile.vms (OBJS): Update list of objects. (DEFS): Update (CFLAGS): Update.	2008-11-14 09:57:35 +00:00
Chao-ying Fu	4dc48ef654	2008-11-06 Chao-ying Fu <fu@mips.com> * mips-opc.c (synciobdma, syncs, syncw, syncws): Move these before sync. (sync): New instruction with 5-bit sync type. * mips-dis.c (print_insn_args: Add case '1' to print 5-bit values.	2008-11-06 19:40:10 +00:00
Nick Clifton	c8941035c5	* avr-dis.c: Replace uses of sprintf without a format string with calls to strcpy.	2008-11-06 12:03:24 +00:00
H.J. Lu	a7bea99dc6	gas/testsuite/ 2008-11-03 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/intel.s: Add tests for cmovpe and cmovpo. * gas/i386/opcode.s: Likewise. * gas/i386/intel.d: Updated. * gas/i386/opcode.d: Likewise. * gas/i386/opcode-intel.d: Likewise. * gas/i386/opcode-suffix.d: Likewise. opcodes/ 2008-11-03 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add cmovpe and cmovpo. * i386-tbl.h: Regenerated.	2008-11-03 19:38:09 +00:00
Nick Clifton	4267b19fc7	PR 6937 * configure.in (SHARED_LIBADD): Revert previous change. Add a comment explaining why. (SHARED_DEPENDENCIES): Revert previous change. * configure: Regenerate.	2008-10-22 14:45:34 +00:00
Nick Clifton	8a9629d090	PR 6937 * configure.in (SHARED_LIBADD): Add libiberty.a. (SHARED_DEPENDENCIES): Add libiberty.a.	2008-10-10 11:35:36 +00:00
H.J. Lu	c587b3f982	2008-09-30 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c: Include "hashtab.h". (next_field): Take a new argument, last. Check last. (process_i386_cpu_flag): Updated. (process_i386_opcode_modifier): Likewise. (process_i386_operand_type): Likewise. (process_i386_registers): Likewise. (output_i386_opcode): New. (opcode_hash_entry): Likewise. (opcode_hash_table): Likewise. (opcode_hash_hash): Likewise. (opcode_hash_eq): Likewise. (process_i386_opcodes): Use opcode hash table and opcode array.	2008-09-30 19:47:14 +00:00
Andreas Krebbel	34b23dab7e	2008-09-30 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-opc.txt (stdy, stey): Fix description	2008-09-30 08:49:54 +00:00
Alan Modra	782e11fd41	run "make dep-am"	2008-09-30 07:49:32 +00:00
H.J. Lu	1927a18f31	2008-09-29 H.J. Lu <hongjiu.lu@intel.com> * aclocal.m4: Regenerated. * configure: Likewise. * Makefile.in: Likewise.	2008-09-29 16:54:07 +00:00
Nick Clifton	afac680a76	* po/vi.po: Updated Vietnamese translation. * po/fr.po: Updated French translation.	2008-09-29 09:48:31 +00:00
Andreas Krebbel	b40d5eb9ef	2008-09-26 Florian Krohm <fkrohm@us.ibm.com> * s390-opc.txt (thder, thdr): Change RRE_RR to RRE_FF. (cfxr, cfdr, cfer, clclu): Add esa flag. (sqd): Instruction added. (qadtr, qaxtr): Change RRF_FFFU to RRF_FUFF. * s390-opc.c: (INSTR_RRF_FFFU, MASK_RRF_FFFU): Removed. 2008-09-26 Andreas Krebbel <krebbel1@de.ibm.com> * gas/s390/esa-g5.d: Adjust according to the s390-opc changes. * gas/s390/esa-g5.s: Likewise. * gas/s390/esa-z990.d: Likewise. * gas/s390/esa-z990.s: Likewise. * gas/s390/zarch-z900.d: Likewise. * gas/s390/zarch-z900.s: Likewise. * gas/s390/zarch-z990.d: Likewise. * gas/s390/zarch-z990.s: Likewise.	2008-09-26 13:44:33 +00:00
Arnold Metselaar	d04117369b	Fix bugs in the disassembly of some ld-instructions	2008-09-14 08:38:02 +00:00
H.J. Lu	3e12678445	gas/testsuite/ 2008-09-11 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/sse2avx.s: Remove pclmulXXX tests. Add tests for Intel syntax. * gas/i386/x86-64-sse2avx.s: Likewise. * gas/i386/sse2avx.d: Updated. * gas/i386/x86-64-sse2avx.d: Likewise. opcodes/ 2008-09-11 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Fix memory operand size for cmpXXXs[sd]. * i386-tbl.h: Regenerated.	2008-09-11 23:15:59 +00:00
Jan Beulich	ddab3d5917	gas/testsuite/ 2008-08-28 Jan Beulich <jbeulich@novell.com> * gas/i386/intel.s: Add retf. * gas/i386/intel.{d,e}: Adjust. * gas/i386/opcode-intel.d: Replace lret with retf. opcodes/ 2008-08-28 Jan Beulich <jbeulich@novell.com> * i386-dis.c (dis386): Adjust far return mnemonics. * i386-opc.tbl: Add retf. * i386-tbl.h: Re-generate.	2008-08-28 15:59:32 +00:00
Jan Beulich	b19d538532	gas/testsuite/ 2008-08-28 Jan Beulich <jbeulich@novell.com> * gas/i386/gas/i386/opcode-suffix.d: Add suffixes to cmovXX. opcodes/ 2008-08-28 Jan Beulich <jbeulich@novell.com> * i386-dis.c (dis386_twobyte): Adjust cmovXX mnemonics.	2008-08-28 15:30:30 +00:00
H.J. Lu	1ca35711f4	gas/ 2008-08-28 H.J. Lu <hongjiu.lu@intel.com> * config/tc-ia64.c (CR_IIB0): New. (CR_IIB1): Likewise. (cr): Add cr.iib0 and cr.iib1. (specify_resource): Handle IA64_RS_CR_IIB and CR_IIB0/CR_IIB1. gas/testsuite/ 2008-08-28 H.J. Lu <hongjiu.lu@intel.com> * gas/ia64/dv-raw-err.s: Add tests for cr.iib0 and cr.iib1. * gas/ia64/dv-waw-err.s: Likewise. * gas/ia64/regs.s: Likewise. * gas/ia64/dv-raw-err.l: Updated. * gas/ia64/dv-waw-err.l: Likewise. * gas/ia64/regs.d: Likewise. include/opcode/ 2008-08-28 H.J. Lu <hongjiu.lu@intel.com> * ia64.h (ia64_resource_specifier): Add IA64_RS_CR_IIB. Update IA64_RS_CR. opcodes/ 2008-08-28 H.J. Lu <hongjiu.lu@intel.com> * ia64-dis.c (print_insn_ia64): Handle cr.iib0 and cr.iib1. * ia64-gen.c (lookup_specifier): Likewise. * ia64-ic.tbl: Add support for cr.iib0 and cr.iib1. * ia64-raw.tbl: Likewise. * ia64-waw.tbl: Likewise. * ia64-asmtab.c: Regenerated.	2008-08-28 14:07:50 +00:00
H.J. Lu	515c56e780	gas/testsuite/ 2008-08-27 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/intel.s: Add tests for fidivr. * gas/i386/intel.d: Updated. opcodes/ 2008-08-27 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Correct fidivr operand size. * i386-tbl.h: Regenerated.	2008-08-27 17:53:42 +00:00
Alan Modra	da594c4a29	Update a number of obsolete autoconf macros.	2008-08-24 03:13:05 +00:00
H.J. Lu	a5ff0eb22b	gas/ 2008-08-20 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (August, 2008) * config/tc-i386.c (CPU_FLAGS_AES_MATCH): New. (CPU_FLAGS_AVX_MATCH): Likewise. (CPU_FLAGS_32BIT_MATCH): Updated. (cpu_flags_match): Likewise. gas/testsuite/ 2008-08-20 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (August, 2008) * gas/i386/avx.s: Add AES + AVX tests. * gas/i386/arch-10.s: Likewise. * gas/i386/sse2avx.s: Likewise. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/x86-64-avx.s: Likewise. * gas/i386/x86-64-sse2avx.s: Likewise. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/avx.d: Likewise. * gas/i386/avx-intel.d: Likewise. * gas/i386/sse2avx.d: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. * gas/i386/x86-64-sse2avx.d: Likewise. * gas/i386/i386.exp: Run arch-avx-1, arch-avx-1-1 and arch-avx-1-2. * gas/i386/arch-avx-1.d: New. * gas/i386/arch-avx-1.s: Likewise. * gas/i386/arch-avx-1-1.l: Likewise. * gas/i386/arch-avx-1-1.s: Likewise. * gas/i386/arch-avx-1-2.l: Likewise. * gas/i386/arch-avx-1-2.s: Likewise. opcodes/ 2008-08-20 H.J. Lu <hongjiu.lu@intel.com> AVX Programming Reference (August, 2008) * i386-dis.c (PREFIX_VEX_38DB): New. (PREFIX_VEX_38DC): Likewise. (PREFIX_VEX_38DD): Likewise. (PREFIX_VEX_38DE): Likewise. (PREFIX_VEX_38DF): Likewise. (PREFIX_VEX_3ADF): Likewise. (VEX_LEN_38DB_P_2): Likewise. (VEX_LEN_38DC_P_2): Likewise. (VEX_LEN_38DD_P_2): Likewise. (VEX_LEN_38DE_P_2): Likewise. (VEX_LEN_38DF_P_2): Likewise. (VEX_LEN_3ADF_P_2): Likewise. (PREFIX_VEX_3A04): Updated. (VEX_LEN_3A06_P_2): Likewise. (prefix_table): Add PREFIX_VEX_38DB, PREFIX_VEX_38DC, PREFIX_VEX_38DD, PREFIX_VEX_38DE and PREFIX_VEX_3ADF. (x86_64_table): Likewise. (vex_len_table): Add VEX_LEN_38DB_P_2, VEX_LEN_38DC_P_2, VEX_LEN_38DD_P_2, VEX_LEN_38DE_P_2, VEX_LEN_38DF_P_2 and VEX_LEN_3ADF_P_2. * i386-opc.tbl: Add AES + AVX instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	2008-08-20 18:38:40 +00:00
Andreas Krebbel	7dc6076f0c	2008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * s390-opc.c (INSTR_RRF_FFRU, MASK_RRF_FFRU): New instruction format. * s390-opc.txt (lxr, rrdtr, rrxtr): Fix instruction format. 2008-08-15 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> * gas/s390/esa-g5.d: lxr operands are floating point. * gas/s390/esa-g5.s: Likewise. * gas/testsuite/gas/s390/zarch-z9-ec.d: rrdtr, rrxtr third operands is gpr. * gas/testsuite/gas/s390/zarch-z9-ec.s: Likewise.	2008-08-15 12:10:21 +00:00
Alan Modra	7357c5b6a6	PR 6526 * configure.in: Invoke AC_USE_SYSTEM_EXTENSIONS.	2008-08-15 08:31:52 +00:00
Alan Modra	899d85bead	PR 6825 * ppc-opc.c (powerpc_opcodes): Enable rfci, mfpmr, mtpmr for e300.	2008-08-14 13:56:00 +00:00
H.J. Lu	dfb0759252	gas/testsuite/ 2008-08-12 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/amd.s: Add syscall and sysret. Remove padding. * gas/i386/amd.d: Updated. * gas/i386/x86-64-opcode.d: Likewise. * gas/i386/i386.exp: Run x86-64-intel64. * gas/i386/x86-64-intel64.d: New. * gas/i386/x86-64-intel64.s: Likewise. * gas/i386/x86-64-opcode.s: Add syscall and sysret. opcodes/ 2008-08-12 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add syscall and sysret for Cpu64. * i386-tbl.h: Regenerated.	2008-08-12 21:44:56 +00:00
Alan Modra	323ee3f41c	Set LC_ALL=C rather than unsetting LC_COLLATE for sort.	2008-08-04 06:55:33 +00:00
Peter Bergner	9b4e57660d	gas/ * config/tc-ppc.c (parse_cpu): Rename altivec_or_spe to retain_flags. Handle -mvsx and -mpower7. (md_show_usage): Document -mpower7 and -mvsx. * doc/as.texinfo (Target PowerPC): Document -mvsx. * doc/c-ppc.texi (PowerPC-Opts): Document -mvsx and -mpower7. gas/testsuite/ * gas/ppc/power7.d: New. * gas/ppc/power7.s: Likewise. * gas/ppc/ppc.exp: Run power7 test. include/opcode/ * ppc.h (PPC_OPCODE_VSX, PPC_OPERAND_VSR): New. opcodes/ * ppc-dis.c (powerpc_init_dialect): Handle power7 and vsx options. (print_insn_powerpc): Prepend 'vs' when printing VSX registers. (print_ppc_disassembler_options): Document -Mpower7 and -Mvsx. * ppc-opc.c (insert_xt6): New static function. (extract_xt6): Likewise. (insert_xa6): Likewise. (extract_xa6: Likewise. (insert_xb6): Likewise. (extract_xb6): Likewise. (insert_xb6s): Likewise. (extract_xb6s): Likewise. (XS6, XT6, XA6, XB6, XB6S, DM, XX3, XX3DM, XX1_MASK, XX3_MASK, XX3DM_MASK, PPCVSX): New. (powerpc_opcodes): Add opcodes "lxvd2x", "lxvd2ux", "stxvd2x", "stxvd2ux", "xxmrghd", "xxmrgld", "xxpermdi", "xvmovdp", "xvcpsgndp".	2008-08-02 04:38:51 +00:00
Pedro Alves	20fd6e2eb1	Missed ChangeLog entry for last change. * Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation. * Makefile.in: Regenerate.	2008-08-01 16:53:56 +00:00
Pedro Alves	e316cf6e3e	* Makefile.am ($(srcdir)/ia64-asmtab.c): Remove line continuation. * Makefile.in: Regenerate.	2008-08-01 14:35:06 +00:00
H.J. Lu	a656ed5bea	binutils/ 2008-08-01 H.J. Lu <hongjiu.lu@intel.com> * dwarf.c (dwarf_regnames_i386): Remove AVX registers. (dwarf_regnames_x86_64): Likewise. gas/testsuite/ 2008-08-01 H.J. Lu <hongjiu.lu@intel.com> * gas/cfi/cfi-i386.s: Remove tests for AVX register maps. * gas/cfi/cfi-x86_64.s: Likewise. * gas/cfi/cfi-i386.d: Updated. * gas/cfi/cfi-x86_64.d: Likewise. opcodes/ 2008-08-01 H.J. Lu <hongjiu.lu@intel.com> * i386-reg.tbl: Use Dw2Inval on AVX registers. * i386-tbl.h: Regenerated.	2008-08-01 14:21:30 +00:00
Alan Modra	081ba1b3c0	include/opcode/ * ppc.h (PPC_OPCODE_405): Define. (PPC_OPERAND_FSL, PPC_OPERAND_FCR, PPC_OPERAND_UDI): Define. gas/ * config/tc-ppc.c (parse_cpu): Separate handling of -m403/405. (md_show_usage): Likewise. opcodes/ * ppc-dis.c (print_insn_powerpc): Disassemble FSL/FCR/UDI fields. * ppc-opc.c (powerpc_operands): Add Xilinx APU related operands. (insert_sprg, PPC405): Use PPC_OPCODE_405. (powerpc_opcodes): Add Xilinx APU related opcodes.	2008-07-30 06:29:22 +00:00
Alan Modra	0af1713e7c	Silence gcc printf warnings	2008-07-30 04:34:58 +00:00
Richard Sandiford	30c0909079	include/elf/ * mips.h (ELF_ST_IS_MIPS16, ELF_ST_SET_MIPS16): New macros. bfd/ * elfxx-mips.c (mips_elf_check_mips16_stubs): Use ELF_ST_IS_MIPS16. (mips_elf_calculate_relocation): Likewise. (_bfd_mips_elf_add_symbol_hook): Likewise. (_bfd_mips_elf_finish_dynamic_symbol): Likewise. (_bfd_mips_vxworks_finish_dynamic_symbol): Likewise. opcodes/ * mips-dis.c (_print_insn_mips): Use ELF_ST_IS_MIPS16. gas/ * config/tc-mips.c (mips16_mark_labels): Use ELF_ST_SET_MIPS16. (mips_fix_adjustable): Likewise. (mips_frob_file_after_relocs): Likewise. gas/testsuite/ * gas/mips/mips16-vis-1.d, gas/mips/mips16-vis-1.s: New tests. * gas/mips/mips.exp: Run them.	2008-07-10 19:05:29 +00:00
Adam Nemet	c27e721e3e	* mips-opc.c (CP): New macro. (mips_builtin_opcodes): Mark c0, c2 and c3 as CP. Add Octeon to the membership of di, dmfc0, dmtc0, ei, mfc0 and mtc0. Add dmfc2 and dmtc2 Octeon instructions.	2008-07-07 19:11:15 +00:00
Stan Shebs	bd2e25575c	2008-07-07 Stan Shebs <stan@codesourcery.com> * dis-init.c (init_disassemble_info): Init endian_code field. * arm-dis.c (print_insn): Disassemble code according to setting of endian_code. (print_insn_big_arm): Detect when BE8 extension flag has been set.	2008-07-07 18:35:24 +00:00
Richard Sandiford	6ba2a41553	bfd/ * syms.c (BSF_SYNTHETIC): New flag. * elf.c (_bfd_elf_get_synthetic_symtab): Set it. * elf32-ppc.c (ppc_elf_get_synthetic_symtab): Likewise. * elf64-ppc.c (ppc64_elf_get_synthetic_symtab): Likewise. * bfd-in.h (bfd_asymbol_flavour): Return bfd_target_unknown_flavour for synthetic symbols. * bfd-in2.h: Regenerate. opcodes/ * mips-dis.c (_print_insn_mips): Use bfd_asymbol_flavour to check for ELF symbols.	2008-06-30 20:51:58 +00:00
Peter Bergner	c8187e1509	gas/ * config/tc-ppc.c (parse_cpu): Handle -m464. (md_show_usage): Likewise. opcodes/ * ppc-dis.c (powerpc_init_dialect): Handle -M464. (print_ppc_disassembler_options): Likewise. * ppc-opc.c (PPC464): Define. (powerpc_opcodes): Add mfdcrux and mtdcrux.	2008-06-25 16:49:03 +00:00
Ralf Wildenhues	7a283e077b	* configure: Regenerate. config/ * override.m4: Use m4_version_prereq throughout. (_AC_ARG_VAR_VALIDATE, AC_MSG_FAILURE): Backport from git Autoconf: output pwd along with fatal errors, so the right config.log file is hinted at more prominently. (PARSE_ARGS): Push setting of ac_pwd in this diversion. (_GCC_AUTOCONF_VERSION): New, define to 2.59 if not defined. (_GCC_AUTOCONF_VERSION_CHECK): New macro, require use of Autoconf version _GCC_AUTOCONF_VERSION throughout the tree. (m4_wrap): New override, fix for Posix semantics of m4wrap. binutils/ * configure: Regenerate. opcodes/ * configure: Regenerate. bfd/ * configure: Regenerate. gas/ * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * config.in: Regenerate. * configure: Regenerate.	2008-06-17 23:14:44 +00:00
Peter Bergner	fa452fa683	include/opcode/ * ppc.h (ppc_cpu_t): New typedef. (struct powerpc_opcode <flags>): Use it. (struct powerpc_operand <insert, extract>): Likewise. (struct powerpc_macro <flags>): Likewise. gas/ * config/tc-ppc.c (ppc_cpu): Use ppc_cpu_t typedef. (ppc_insert_operand): Likewise. (ppc_machine): Likewise. * config/tc-ppc.h: #include "opcode/ppc.h" (struct _ppc_fix_extra <ppc_cpu>): Use ppc_cpu_t typedef. (ppc_cpu): Update extern decl. opcodes/ * ppc-dis.c (print_insn_powerpc): Update prototye to use new ppc_cpu_t typedef. (struct dis_private): New. (POWERPC_DIALECT): New define. (powerpc_dialect): Renamed to... (powerpc_init_dialect): This. Update to use ppc_cpu_t and struct dis_private. (print_insn_big_powerpc): Update for using structure in info->private_data. (print_insn_little_powerpc): Likewise. (operand_value_powerpc): Change type of dialect param to ppc_cpu_t. (skip_optional_operands): Likewise. (print_insn_powerpc): Likewise. Remove initialization of dialect. * ppc-opc.c (extract_bat, extract_bba, extract_bdm, extract_bdp, extract_bo, extract_boe, extract_fxm, extract_mb6, extract_mbe, extract_nb, extract_nsi, extract_rbs, extract_sh6, extract_spr, extract_sprg, extract_tbr insert_bat, insert_bba, insert_bdm, insert_bdp, insert_bo, insert_boe, insert_fxm, insert_mb6, insert_mbe, insert_nsi, insert_ral, insert_ram, insert_raq, insert_ras, insert_rbs, insert_sh6, insert_spr, insert_sprg, insert_tbr): Change the dialect param to be of type ppc_cpu_t. Update prototype.	2008-06-13 20:16:00 +00:00
Nick Clifton	dd3cbb7ef7	* mips.h: Document new field descriptors +Q. (OP_SH_SEQI, OP_MASK_SEQI): New bit mask and shift count for SEQI. opcodes/ * mips-dis.c (print_insn_args): Handle field descriptor +Q. * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions seq, seqi, sne and snei. gas/ * config/tc-mips.c (validate_mips_insn): Handle field descriptor +Q. (mips_ip): Likewise. (macro_build): Likewise. (CPU_HAS_SEQ): New macro. (macro2) <M_SEQ_I, M_SNE_I>: Use it. Emit seq/sne and seqi/snei. gas/testsuite/ * gas/mips/octeon.s, gas/mips/octeon.d: Add tests for seq* and sne. gas/mips/octeon-ill.s, gas/mips/octeon-ill.s: Add tests for seqi and snei.	2008-06-12 21:44:54 +00:00
Nick Clifton	bb35fb24c1	include/opcode/ * mips.h: Document new field descriptors +x, +X, +p, +P, +s, +S. Update comment before MIPS16 field descriptors to mention MIPS16. (OP_SH_BBITIND, OP_MASK_BBITIND): New bit mask and shift count for BBIT. (OP_SH_CINSPOS, OP_MASK_CINSPOS, OP_SH_CINSLM1, OP_MASK_CINSLM1): New bit masks and shift counts for cins and exts. gas/ * config/tc-mips.c (validate_mips_insn): Handle field descriptors +x, +X, +p, +P, +s, +S. (mips_ip): Likewise. opcodes/ * mips-dis.c (print_insn_args): Handle field descriptors +x, +p, +s, +S. * mips-opc.c (mips_builtin_opcodes): Add Octeon instructions baddu, bbit, cins, dmul, pop, dpop, exts, mtm, mtp, syncs, syncw, syncws, vm3mulu, vm0 and vmulu. gas/testsuite/ gas/mips/octeon.s, gas/mips/octeon.d: Add tests for baddu, bbit, cins, dmul, pop, dpop, exts, mtm, mtp, syncs, syncw, syncws, vm3mulu, vm0 and vmulu. gas/mips/octeon-ill.s, gas/mips/octeon-ill.s: New test. * gas/mips/mips.exp: Run it. Run octeon test with run_dump_test_arches.	2008-06-12 16:14:52 +00:00
H.J. Lu	a5dabbb023	gas/testsuite/ 2008-05-30 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/x86-64-avx.s: Add tests for vmovd on 64bit operands. * gas/i386/x86-64-sse2avx.s: Add tests for movd on 64bit operands. * gas/testsuite/gas/i386/x86-64-avx.d: Updated. * gas/testsuite/gas/i386/x86-64-avx-intel.d: Likewise. * gas/testsuite/gas/i386/x86-64-sse2avx.d: Likewise. opcodes/ 2008-05-30 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add vmovd with 64bit operand. * i386-tbl.h: Regenerated.	2008-05-30 19:49:18 +00:00
Martin Schwidefsky	725a9891bc	2008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com> * s390-opc.c (INSTR_RRF_R0RR): Fix RRF_R0RR operand format. 2008-05-27 Martin Schwidefsky <schwidefsky@de.ibm.com> * gas/s390/zarch-z990.d (idte): Fix operand format.	2008-05-27 12:52:44 +00:00
H.J. Lu	cbc80391d0	gas/testsuite/ 2008-05-22 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/sse-noavx.s: Add tests for cvtpd2pi, cvtpi2pd and cvttpd2pi. * gas/i386/x86-64-sse-noavx.s: Likewise. * gas/i386/sse-noavx.d: Updated. * gas/i386/x86-64-sse-noavx.d: Likewise. opcodes/ 2008-05-22 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add NoAVX to cvtpd2pi, cvtpi2pd and cvttpd2pi. * i386-tbl.h: Regenerated.	2008-05-23 00:18:52 +00:00
H.J. Lu	116615c5f7	gas/testsuite/ 2008-05-22 H.J. Lu <hongjiu.lu@intel.com> PR gas/6517 * gas/i386/avx.s: Add tests for unspecified memory operand size in Intel syntax. * gas/i386/x86-64-avx.s: Likewise. * gas/i386/simd.s: Add tests for cvtsi2ss and cvtsi2sd with unspecified memory operand size in Intel syntax. * gas/i386/avx.d: Updated. * gas/i386/avx-intel.d: Likewise. * gas/i386/simd.d: Likewise. * gas/i386/simd-intel.d: Likewise. * gas/i386/simd-suffix.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. opcodes/ 2008-05-22 H.J. Lu <hongjiu.lu@intel.com> PR gas/6517 * i386-opc.tbl: Break cvtsi2ss/cvtsi2sd/vcvtsi2sd/vcvtsi2ss into 32bit and 64bit. Remove Reg64\|Qword and add IgnoreSize\|No_qSuf on 32bit version. * i386-tbl.h: Regenerated.	2008-05-22 20:52:54 +00:00
H.J. Lu	d9479f2d8d	gas/testsuite/ 2008-05-21 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/sse-noavx.s: Add tests for movdq2q and movq2dq. * gas/i386/x86-64-sse-noavx.s: Likewise. * gas/i386/sse-noavx.d: Updated. * gas/i386/x86-64-sse-noavx.d: Likewise. opcodes/ 2008-05-21 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add NoAVX to movdq2q and movq2dq. * i386-tbl.h: Regenerated.	2008-05-21 21:40:57 +00:00
Nick Clifton	3ce6fddb77	* cr16-dis.c (build_mask): Adjust the mask for 32-bit bcond.	2008-05-21 07:50:55 +00:00
Alan Modra	8944f3c277	update dependencies	2008-05-14 06:45:42 +00:00
H.J. Lu	f1f8f695c0	gas/ 2008-05-02 H.J. Lu <hongjiu.lu@intel.com> * NEWS: Mention XSAVE, EPT and MOVBE. * config/tc-i386.c (cpu_arch): Add .movbe and .ept. (md_show_usage): Add .movbe and .ept. * doc/c-i386.texi: Add movbe and ept to -march=. Document .movbe and .ept. gas/testsuite/ 2008-05-02 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run movbe, movbe-intel, inval-movbe, ept, ept-intel, inval-ept, x86-64-movbe, x86-64-movbe-intel, x86-64-inval-movbe. x86-64-ept, x86-64-ept-intel and x86-64-inval-ept. * gas/i386/arch-10.s: Add movbe and invept. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/ept.d: New file * gas/i386/ept-intel.d: Likewise. * gas/i386/ept.s: Likewise. * gas/i386/inval-ept.l: Likewise. * gas/i386/inval-ept.s: Likewise. * gas/i386/inval-movbe.l: Likewise. * gas/i386/inval-movbe.s: Likewise. * gas/i386/movbe.d: Likewise. * gas/i386/movbe-intel.d: Likewise. * gas/i386/movbe.s: Likewise. * gas/i386/x86-64-inval-ept.l: Likewise. * gas/i386/x86-64-inval-ept.s: Likewise. * gas/i386/x86-64-inval-movbe.l: Likewise. * gas/i386/x86-64-inval-movbe.s: Likewise. * gas/i386/x86-64-ept.d: Likewise. * gas/i386/x86-64-ept-intel.d: Likewise. * gas/i386/x86-64-ept.s: Likewise. * gas/i386/x86-64-movbe.d: Likewise. * gas/i386/x86-64-movbe-intel.d: Likewise. * gas/i386/x86-64-movbe.s: Likewise. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. opcodes/ 2008-05-02 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (MOVBE_Fixup): New. (Mo): Likewise. (PREFIX_0F3880): Likewise. (PREFIX_0F3881): Likewise. (PREFIX_0F38F0): Updated. (prefix_table): Add PREFIX_0F3880 and PREFIX_0F3881. Update PREFIX_0F38F0 and PREFIX_0F38F1 for movbe. (three_byte_table): Use PREFIX_0F3880 and PREFIX_0F3881. * i386-gen.c (cpu_flag_init): Add CPU_MOVBE_FLAGS and CPU_EPT_FLAGS. (cpu_flags): Add CpuMovbe and CpuEPT. * i386-opc.h (CpuMovbe): New. (CpuEPT): Likewise. (CpuLM): Updated. (i386_cpu_flags): Add cpumovbe and cpuept. * i386-opc.tbl: Add entries for movbe and EPT instructions. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	2008-05-02 16:53:40 +00:00
Adam Nemet	89aa3097c2	* mips-opc.c (mips_builtin_opcodes): Set field `match' to 0 for the two drem and the two dremu macros.	2008-04-29 23:27:01 +00:00
Adam Nemet	39c5c16818	* mips-opc.c (mips_builtin_opcodes): Mark prefx and c1 instructions FP_S. Mark l.s, li.s, lwc1, swc1, s.s, trunc.w.s and cop1 macros INSN2_M_FP_S. Mark l.d, li.d, ldc1 and sdc1 macros INSN2_M_FP_D. Mark trunc.w.d macro INSN2_M_FP_S and INSN2_M_FP_D.	2008-04-28 17:03:58 +00:00
David S. Miller	f04d18b76a	gas/ * config/tc-sparc.c: Accept 'softint_clear' and 'softint_set' %asr aliases. * doc/c-sparc.texi: Consistently refer to architecture 'versions', rather than occaisionally 'levels'. Consistently refer to Sun's UNIX variant as SunOS, every version of Solaris is also SunOS. Document new 'softint_clear' and 'softint_set' aliases. Clarify which architecture versions support '%dcr', '%cq', and '%gl'. Add section on 32-bit/64-bit opcode translations. opcodes/ * sparc-dis.c: Emit %stick instead of %sys_tick, and %stick_cmpr instead of %sys_tick_cmpr, as suggested in architecture manuals.	2008-04-25 19:58:03 +00:00
H.J. Lu	6194aaaba7	bfd/ 2008-04-23 Paolo Bonzini <bonzini@gnu.org> * aclocal.m4: Regenerate. * configure: Regenerate. binutils/ 2008-04-23 Paolo Bonzini <bonzini@gnu.org> * aclocal.m4: Regenerate. * configure: Regenerate. gas/ 2008-04-23 Paolo Bonzini <bonzini@gnu.org> * aclocal.m4: Regenerate. * configure: Regenerate. gold/ 2008-04-23 Paolo Bonzini <bonzini@gnu.org> * aclocal.m4: Regenerate. * configure: Regenerate. gprof/ 2008-04-23 Paolo Bonzini <bonzini@gnu.org> * aclocal.m4: Regenerate. * configure: Regenerate. ld/ 2008-04-23 Paolo Bonzini <bonzini@gnu.org> * aclocal.m4: Regenerate. * configure: Regenerate. opcodes/ 2008-04-23 Paolo Bonzini <bonzini@gnu.org> * aclocal.m4: Regenerate. * configure: Regenerate.	2008-04-23 16:11:47 +00:00
David S. Miller	1a6b486f73	opcodes/ * sparc-opc.c (asi_table): Add UltraSPARC and Niagara extended values. (prefetch_table): Add missing values. gas/ * config/tc-sparc.c (v9a_asr_table): Add missing 'stick' and 'stick_cmpr', and document ordering rules of table. (tc_gen_reloc): Accept BFD_RELOC_SPARC_PC22 and BFD_RELOC_SPARC_PC10. * doc/c-sparc.texi: New section on Sparc constants. Add documentation for %stick and %stick_cmpr. gas/testsuite/ * gas/sparc/pc2210.d: New file. * gas/sparc/pc2210.d: Likewise. * gas/sparc/sparc.exp: Run new %pc22/%pc10 relocation test.	2008-04-23 07:49:33 +00:00
H.J. Lu	81f8a9131a	gas/ 2008-04-22 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (md_assemble): Don't check SSE instructions if noavx is 0. opcodes/ 2008-04-22 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Add NoAVX. * i386-opc.h (NoAVX): New. (OldGcc): Updated. (i386_opcode_modifier): Add noavx. * i386-opc.tbl: Add NoAVX to SSE, SSE2, SSE3 and SSSE3 instructions which don't have AVX equivalent. * i386-tbl.h: Regenerated.	2008-04-22 22:27:13 +00:00
H.J. Lu	dae39accc2	gas/ 2008-04-18 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (build_modrm_byte): Swap REG and NDS for FMA. gas/testsuite/ 2008-04-18 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-10.d: Updated. * gas/i386/avx.d: Likewise. * gas/i386/avx-intel.d: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. opcodes/ 2008-04-18 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_VEX_FMA): New. (OP_EX_VexImmW): Likewise. (VexFMA): Likewise. (Vex128FMA): Likewise. (EXVexImmW): Likewise. (get_vex_imm8): Likewise. (OP_EX_VexReg): Likewise. (vex_i4_done): Renamed to ... (vex_w_done): This. (prefix_table): Replace EXVexW with EXVexImmW on vpermil2ps and vpermil2pd. Replace Vex/Vex128 with VexFMA/Vex128FMA on FMA instructions. (print_insn): Updated. (OP_EX_VexW): Rewrite to swap register in VEX with EX. (OP_REG_VexI4): Check invalid high registers.	2008-04-18 13:10:32 +00:00
Dwarakanath Rajagopal	ce886ab1f8	<opcode changes> 2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> Michael Meissner <michael.meissner@amd.com> * i386-opc.tbl: Fix protX to allow memory in the middle operand. * i386-tbl.h: Regenerate from i386-opc.tbl. <gas/testsuite changes> 2008-04-16 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> Michael Meissner <michael.meissner@amd.com> * gas/i386/x86-64-sse5.s: Add protX tests to allow memory in the middle operand. * gas/i386/x86-64-sse5.d: Likewise.	2008-04-16 15:31:33 +00:00
Alan Modra	19a6653ce8	ppc e500mc support	2008-04-14 11:01:38 +00:00
Andreas Krebbel	112b7c5071	2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com> * s390-dis.c (init_disasm): Evaluate disassembler_options. (print_s390_disassembler_options): New function. * disassemble.c (disassembler_usage): Invoke print_s390_disassembler_options. 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com> * dis-asm.h (print_s390_disassembler_options): Prototype added.	2008-04-10 13:36:43 +00:00
Andreas Krebbel	7ff4264847	2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com> * s390-mkopc.c (insertExpandedMnemonic): Expand string sizes of local variables used for mnemonic parsing: prefix, suffix and number.	2008-04-10 13:05:07 +00:00
Andreas Krebbel	45a5551e74	2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com> * s390-mkopc.c (s390_cond_ext_format): Add back the mnemonic extensions for conditional jumps (o, p, m, nz, z, nm, np, no). (s390_crb_extensions): New extensions table. (insertExpandedMnemonic): Handle '$' tag. * s390-opc.txt: Remove conditional jump variants which can now be expanded automatically. Replace '' tag with '$' in the compare and branch instructions. 2008-04-10 Andreas Krebbel <krebbel1@de.ibm.com> gas/s390/zarch-z10.d: Map the compare and branch variants with odd condition code mask to version with an even mask.	2008-04-10 08:59:46 +00:00
H.J. Lu	06c8514ace	2008-04-07 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (PREFIX_VEX_38XX): Add a tab. (PREFIX_VEX_3AXX): Likewis.	2008-04-07 21:29:50 +00:00
H.J. Lu	b122c2853a	2008-04-07 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Remove 4 extra blank lines.	2008-04-07 17:35:12 +00:00
H.J. Lu	594ab6a333	gas/ 2008-04-04 H.J. Lu <hongjiu.lu@intel.com> * NEWS: Mention XSAVE. Change CLMUL to PCLMUL. * config/tc-i386.c (cpu_arch): Add .pclmul. (md_show_usage): Replace clmul with pclmul. * doc/c-i386.texi: Likewise. gas/testsuite/ 2008-04-04 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-10-1.l: Replace CLMUL with PCLMUL. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/arch-10.s: Likewise. * gas/i386/clmul-intel.d: Likewise. * gas/i386/clmul.d: Likewise. * gas/i386/clmul.s: Likewise. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/x86-64-clmul-intel.d: Likewise. * gas/i386/x86-64-clmul.d: Likewise. * gas/i386/x86-64-clmul.s: Likewise. * gas/i386/arch-10.d: Replace clmul with pclmul. * gas/i386/x86-64-arch-2.d: Likewise. opcodes/ 2008-04-04 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Replace CPU_CLMUL_FLAGS/CpuCLMUL with CPU_PCLMUL_FLAGS/CpuPCLMUL. (cpu_flags): Replace CpuCLMUL with CpuPCLMUL. * i386-opc.tbl: Likewise. * i386-opc.h (CpuCLMUL): Renamed to ... (CpuPCLMUL): This. (CpuFMA): Updated. (i386_cpu_flags): Replace cpuclmul with cpupclmul. * i386-init.h: Regenerated.	2008-04-04 16:34:23 +00:00
H.J. Lu	c0f3af977b	binutils/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * dwarf.c (dwarf_regnames_i386): Add AVX registers. (dwarf_regnames_x86_64): Likewise. gas/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * NEWS: Mention AES, CLMUL, AVX/FMA and -msse2avx. * doc/c-i386.texi: Add avx, aes, clmul and fma to -march=. Document -msse2avx, .avx, .aes, .clmul and .fma. * config/tc-i386.c (YMMWORD_MNEM_SUFFIX): New. (vex_prefix): Likewise. (sse2avx): Likewise. (CPU_FLAGS_ARCH_MATCH): Likewise. (CPU_FLAGS_64BIT_MATCH): Likewise. (CPU_FLAGS_32BIT_MATCH): Likewise. (CPU_FLAGS_PERFECT_MATCH): Likewise. (regymm): Likewise. (vex_imm4): Likewise. (fits_in_imm4): Likewise. (build_vex_prefix): Likewise. (VEX_check_operands): Likewise. (bad_implicit_operand): Likewise. (OPTION_MSSE2AVX): Likewise. (T_YMMWORD): Likewise. (_i386_insn): Add vex. (cpu_arch): Add .avx, .aes, .clmul and .fma. (cpu_flags_match): Changed to take a pointer to const template. Enable encoding SSE instructions with VEX prefix for -msse2avx. (match_mem_size): Also check ymmword. (operand_type_match): Clear ymmword. (md_begin): Allow '_' in mnemonic. (type_names): Add OPERAND_TYPE_VEX_IMM4. (process_immext): Update assert. (md_assemble): Don't call process_immext if sse2avx and immext are true. Call build_vex_prefix if vex is true. (parse_insn): Updated for cpu_flags_match. (swap_operands): Handle 5 operands. (match_template): Handle 5 operands. Updated for cpu_flags_match. Check regymm. Call VEX_check_operands. Handle YMMWORD_MNEM_SUFFIX. (process_suffix): Handle YMMWORD_MNEM_SUFFIX. (check_byte_reg): Check regymm. (process_operands): Duplicate the destination register for -msse2avx if needed. (build_modrm_byte): Updated for instructions with VEX encoding. (output_insn): Output VEX prefix if needed. (md_longopts): Add msse2avx. (md_parse_option): Handle OPTION_MSSE2AVX. (md_show_usage): Add avx, aes, clmul, fma and -msse2avx. (intel_e09): Support YMMWORD. (intel_e11): Likewise. (intel_get_token): Likewise. gas/testsuite/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run aes, aes-intel, x86-64-aes, x86-64-aes-intel, avx, avx-intel, inval-avx, x86-64-avx, x86-64-avx-intel and x86-64-inval-avx. * gas/cfi/cfi-i386.s: Add tests for AVX register maps. * gas/cfi/cfi-x86_64.s: Likewise. * gas/i386/aes.d: New. * gas/i386/aes.s: Likewise. * gas/i386/aes-intel.d: Likewise. * gas/i386/avx.d: Likewise. * gas/i386/avx.s: Likewise. * gas/i386/avx-intel.d: Likewise. * gas/i386/clmul.d: Likewise. * gas/i386/clmul-intel.d: Likewise. * gas/i386/clmul.s: Likewise. * gas/i386/i386.exp: Likewise. * gas/i386/inval-avx.l: Likewise. * gas/i386/inval-avx.s: Likewise. * gas/i386/sse2avx.d: Likewise. * gas/i386/sse2avx.s: Likewise. * gas/i386/x86-64-aes.d: Likewise. * gas/i386/x86-64-aes.s: Likewise. * gas/i386/x86-64-aes-intel.d: Likewise. * gas/i386/x86-64-avx.d: Likewise. * gas/i386/x86-64-avx.s: Likewise. * gas/i386/x86-64-avx-intel.d: Likewise. * gas/i386/x86-64-clmul.d: Likewise. * gas/i386/x86-64-clmul-intel.d: Likewise. * gas/i386/x86-64-clmul.s: Likewise. * gas/i386/x86-64-inval-avx.l: Likewise. * gas/i386/x86-64-inval-avx.s: Likewise. * gas/i386/x86-64-sse2avx.d: Likewise. * gas/i386/x86-64-sse2avx.s: Likewise. * gas/i386/arch-10.s: Add tests for AVX, AES, CLMUL and FMA. * gas/i386/x86-64-arch-2.s: Likewise. * gas/i386/rexw.s: Add AVX tests. * gas/i386/x86-64-opcode-inval.s: Remove lds/les test. * gas/cfi/cfi-i386.d: Updated. * gas/cfi/cfi-x86_64.d: Likewise. * gas/i386/arch-10.d: Likewise. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/rexw.d: Likewise. * gas/i386/x86-64-arch-2.d: Likewise. * gas/i386/x86-64-opcode-inval.d: Likewise. * gas/i386/x86-64-opcode-inval-intel.d: Likewise. include/opcode/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * i386.h (MAX_OPERANDS): Set to 5. (MAX_MNEM_SIZE): Changed to 20. opcodes/ 2008-04-03 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_E_register): New. (OP_E_memory): Likewise. (OP_VEX): Likewise. (OP_EX_Vex): Likewise. (OP_EX_VexW): Likewise. (OP_XMM_Vex): Likewise. (OP_XMM_VexW): Likewise. (OP_REG_VexI4): Likewise. (PCLMUL_Fixup): Likewise. (VEXI4_Fixup): Likewise. (VZERO_Fixup): Likewise. (VCMP_Fixup): Likewise. (VPERMIL2_Fixup): Likewise. (rex_original): Likewise. (rex_ignored): Likewise. (Mxmm): Likewise. (XMM): Likewise. (EXxmm): Likewise. (EXxmmq): Likewise. (EXymmq): Likewise. (Vex): Likewise. (Vex128): Likewise. (Vex256): Likewise. (VexI4): Likewise. (EXdVex): Likewise. (EXqVex): Likewise. (EXVexW): Likewise. (EXdVexW): Likewise. (EXqVexW): Likewise. (XMVex): Likewise. (XMVexW): Likewise. (XMVexI4): Likewise. (PCLMUL): Likewise. (VZERO): Likewise. (VCMP): Likewise. (VPERMIL2): Likewise. (xmm_mode): Likewise. (xmmq_mode): Likewise. (ymmq_mode): Likewise. (vex_mode): Likewise. (vex128_mode): Likewise. (vex256_mode): Likewise. (USE_VEX_C4_TABLE): Likewise. (USE_VEX_C5_TABLE): Likewise. (USE_VEX_LEN_TABLE): Likewise. (VEX_C4_TABLE): Likewise. (VEX_C5_TABLE): Likewise. (VEX_LEN_TABLE): Likewise. (REG_VEX_XX): Likewise. (MOD_VEX_XXX): Likewise. (PREFIX_0F38DB..PREFIX_0F38DF): Likewise. (PREFIX_0F3A44): Likewise. (PREFIX_0F3ADF): Likewise. (PREFIX_VEX_XXX): Likewise. (VEX_OF): Likewise. (VEX_OF38): Likewise. (VEX_OF3A): Likewise. (VEX_LEN_XXX): Likewise. (vex): Likewise. (need_vex): Likewise. (need_vex_reg): Likewise. (vex_i4_done): Likewise. (vex_table): Likewise. (vex_len_table): Likewise. (OP_REG_VexI4): Likewise. (vex_cmp_op): Likewise. (pclmul_op): Likewise. (vpermil2_op): Likewise. (m_mode): Updated. (es_reg): Likewise. (PREFIX_0F38F0): Likewise. (PREFIX_0F3A60): Likewise. (reg_table): Add REG_VEX_71...REG_VEX_73 and REG_VEX_AE. (prefix_table): Add PREFIX_0F38DB..PREFIX_0F38DF, PREFIX_0F3ADF and PREFIX_VEX_XXX entries. (x86_64_table): Use VEX_C4_TABLE and VEX_C5_TABLE. (three_byte_table): Use PREFIX_0F38DB..PREFIX_0F38DF and PREFIX_0F3ADF. (mod_table): Use VEX_C4_TABLE, VEX_C5_TABLE and VEX_LEN_TABLE. Add MOD_VEX_XXX entries. (ckprefix): Initialize rex_original and rex_ignored. Store the REX byte in rex_original. (get_valid_dis386): Handle the implicit prefix in VEX prefix bytes and USE_VEX_LEN_TABLE/USE_VEX_C4_TABLE/USE_VEX_C5_TABLE. (print_insn): Set need_vex/need_vex_reg/vex_i4_done to 0 before calling get_valid_dis386. Use rex_original and rex_ignored when printing out REX. (putop): Handle "XY". (intel_operand_size): Handle VEX, xmm_mode, xmmq_mode and ymmq_mode. (OP_E_extended): Updated to use OP_E_register and OP_E_memory. (OP_XMM): Handle VEX. (OP_EX): Likewise. (XMM_Fixup): Likewise. (CMP_Fixup): Use ARRAY_SIZE. * i386-gen.c (cpu_flag_init): Add CpuAES, CPU_CLMUL_FLAGS, CPU_FMA_FLAGS and CPU_AVX_FLAGS. (operand_type_init): Add OPERAND_TYPE_REGYMM and OPERAND_TYPE_VEX_IMM4. (cpu_flags): Add CpuAVX, CpuAES, CpuCLMUL and CpuFMA. (opcode_modifiers): Add Implicit1stXmm0, Vex, Vex256, VexNDD, VexNDS, VexW0, VexW1, Vex0F, Vex0F38, Vex0F3A, Vex3Sources, VexImmExt and SSE2AVX. (operand_types): Add RegYMM, Ymmword and Vex_Imm4. * i386-opc.h (CpuAVX): New. (CpuAES): Likewise. (CpuCLMUL): Likewise. (CpuFMA): Likewise. (Vex): Likewise. (Vex256): Likewise. (VexNDS): Likewise. (VexNDD): Likewise. (VexW0): Likewise. (VexW1): Likewise. (Vex0F): Likewise. (Vex0F38): Likewise. (Vex0F3A): Likewise. (Vex3Sources): Likewise. (VexImmExt): Likewise. (SSE2AVX): Likewise. (RegYMM): Likewise. (Ymmword): Likewise. (Vex_Imm4): Likewise. (Implicit1stXmm0): Likewise. (CpuXsave): Updated. (CpuLM): Likewise. (ByteOkIntel): Likewise. (OldGcc): Likewise. (Control): Likewise. (Unspecified): Likewise. (OTMax): Likewise. (i386_cpu_flags): Add cpuavx, cpuaes, cpuclmul and cpufma. (i386_opcode_modifier): Add implicit1stxmm0, vex, vex256, vexnds, vexndd, vexw0, vexw1, vex0f, vex0f38, vex0f3a, vex3sources, veximmext and sse2avx. (i386_operand_type): Add regymm, ymmword and vex_imm4. * i386-opc.tbl: Add AES, CLMUL, AVX and FMA new instructions. * i386-reg.tbl: Add AVX registers, ymm0..ymm15. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	2008-04-03 14:03:21 +00:00
Bernd Schmidt	086134ec0e	gas/testsuite/: From Robin Getz <rgetz@blackfin.uclinux.org> * gas/bfin/arithmetic.d: Update to reflect spaces/capitalization in recent changes in opcodes/bfin-dis.c. gas/bfin/arithmetic.s: Likewise. gas/bfin/bit.d: Likewise. gas/bfin/bit2.d: Likewise. gas/bfin/control_code.d: Likewise. gas/bfin/control_code2.d: Likewise. gas/bfin/event.d: Likewise. gas/bfin/event2.d: Likewise. gas/bfin/flow.d: Likewise. gas/bfin/flow2.d: Likewise. gas/bfin/load.d: Likewise. gas/bfin/logical.d: Likewise. gas/bfin/logical2.d: Likewise. gas/bfin/move.d: Likewise. gas/bfin/move2.d: Likewise. gas/bfin/parallel.d: Likewise. gas/bfin/parallel2.d: Likewise. gas/bfin/parallel3.d: Likewise. gas/bfin/parallel4.d: Likewise. gas/bfin/shift.d: Likewise. gas/bfin/shift2.d: Likewise. gas/bfin/stack.d: Likewise. gas/bfin/stack2.d: Likewise. gas/bfin/store.d: Likewise. gas/bfin/vector.d: Likewise. gas/bfin/vector2.d: Likewise. gas/bfin/video.d: Likewise. gas/bfin/video2.d: Likewise. opcodes/: * bfin-dis.c: (c_uimm4s4d, c_imm5d, c_imm7d, c_imm16d, c_uimm16s4d, c_imm32, c_huimm32e): Define. (constant_formats): Add flags for printing decimal, leading spaces, and exact symbols. (comment, parallel): Add global flags in all disassembly. (fmtconst): Take advantage of new flags, and print default in hex. (fmtconst_val): Likewise. (decode_macfunc): Be consistant with spaces, tabs, comments, capitalization in disassembly, fix minor coding style issues. (reg_names, amod0, amod1, amod0amod2, aligndir, get_allreg): Likewise. (decode_ProgCtrl_0, decode_PushPopMultiple_0, decode_CCflag_0, decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0, decode_REGMV_0, decode_ALU2op_0, decode_PTR2op_0, decode_LOGI2op_0, decode_COMP3op_0, decode_COMPI2opD_0, decode_COMPI2opP_0, decode_LDSTpmod_0, decode_dagMODim_0, decode_dagMODik_0, decode_dspLDST_0, decode_LDST_0, decode_LDSTiiFP_0, decode_LDSTii_0, decode_LoopSetup_0, decode_LDIMMhalf_0, decode_CALLa_0, decode_LDSTidxI_0, decode_linkage_0, decode_dsp32alu_0, decode_dsp32shift_0, decode_dsp32shiftimm_0, decode_pseudodbg_assert_0, _print_insn_bfin, print_insn_bfin): Likewise.	2008-03-26 16:48:32 +00:00
Bernd Schmidt	ee171c8f94	gas/ * config/bfin-parse.y (check_macfunc_option): Allow (IU) option for multiply and multiply-accumulate to data register instruction. (check_macfuncs): Don't check if accumulator matches the data register here. (assign_macfunc): Check if accumulator matches the data register in each rule that moves to the data register. gas/testsuite/ * gas/bfin/arithmetic.s, gas/bfin/arithmetic.d: Add check for IU option. * gas/bfin/expected_errors.l, gas/bfin/expected_errors.s: Add check for mismatch of accumulator and data register. opcodes/ * bfin-dis.c (decode_dsp32mac_0): Decode (IU) option for multiply and multiply-accumulate to data register instruction.	2008-03-26 16:21:10 +00:00
Bernd Schmidt	b21c9cb440	opcodes: From Robin Getz <robin.getz@analog.com> * bfin-dis.c (bu32): Typedef. (enum const_forms_t): Add c_uimm32 and c_huimm32. (constant_formats[]): Add uimm32 and huimm16. (fmtconst_val): New. (uimm32): Define. (huimm32): Define. (imm16_val): Define. (luimm16_val): Define. (struct saved_state): Define. (GREG, DPREG, DREG, PREG, SPREG, FPREG, IREG, MREG, BREG, LREG, A0XREG, A0WREG, A1XREG, A1WREG,CCREG, LC0REG, LT0REG, LB0REG, LC1REG, LT1REG, LB1REG, RETSREG, PCREG): Define. (get_allreg): New. (decode_LDIMMhalf_0): Print out the whole register value. gas/testsuite: From Jie Zhang <jie.zhang@analog.com> * gas/bfin/load.d: Update.	2008-03-26 14:50:52 +00:00
Andreas Krebbel	5746fb46c8	2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com> * opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z10 added. (s390_cond_extensions): Reduced extensions to the compare related. (main): z10 cpu type option added. (expandConditionalJump): Renamed to ... (insertExpandedMnemonic): ... this. * opcodes/s390-opc.c: Re-group the operand format makros. (INSTR_RIE_RRPU, INSTR_RIE_RRP0, INSTR_RIE_RUPI, INSTR_RIE_R0PI, INSTR_RIE_RUPU, INSTR_RIE_R0PU, INSTR_RIE_R0IU, INSTR_RIE_R0I0, INSTR_RIE_R0UU, INSTR_RIE_R0U0, INSTR_RIE_RRUUU, INSTR_RIS_RURDI, INSTR_RIS_R0RDI, INSTR_RIS_RURDU, INSTR_RIS_R0RDU, INSTR_RRF_U0RR, INSTR_RRF_00RR, INSTR_RRS_RRRDU, INSTR_RRS_RRRD0, INSTR_RXY_URRD, INSTR_SIY_IRD, INSTR_SIL_RDI, INSTR_SIL_RDU): New instruction formats added. (MASK_RIE_RRPU, MASK_RIE_RRP0, MASK_RIE_RUPI, MASK_RIE_R0PI, MASK_RIE_RUPU, MASK_RIE_R0PU, MASK_RIE_R0IU, MASK_RIE_R0I0, MASK_RIE_R0UU, MASK_RIE_R0U0, MASK_RIE_RRUUU, MASK_RIS_RURDI, MASK_RIS_R0RDI, MASK_RIS_RURDU, MASK_RIS_R0RDU, MASK_RRF_U0RR, MASK_RRF_00RR, MASK_RRS_RRRDU, MASK_RRS_RRRD0, MASK_RXY_URRD, MASK_SIY_IRD, MASK_SIL_RDI, MASK_SIL_RDU): New instruction format masks added. (s390_opformats): New formats added "ris", "rrs", "sil". * opcodes/s390-opc.txt: Add the conditional jumps with the extensions removed from automatic expansion in s390-mkopc.c manually. (asi - trtre): Add new System z10 EC instructions. * include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z10 added. 2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com> * config/tc-s390.c (md_parse_option): z10 option added. 2008-03-19 Andreas Krebbel <krebbel1@de.ibm.com> * gas/s390/zarch-z10.d: New file. * gas/s390/zarch-z10.s: New file. * gas/s390/s390.exp: Run the z10 testcases.	2008-03-19 10:29:18 +00:00
Ralf Wildenhues	58c85be758	* configure.ac: m4_include config/proginstall.m4. * configure: Regenerate. config/ * proginstall.m4: New file, with fixed AC_PROG_INSTALL. bfd/ * aclocal.m4: Regenerate. * configure: Likewise. * Makefile.in: Likewise. bfd/doc/ * Makefile.in: Regenerate. intl/ * aclocal.m4: Regenerate. * configure: Likewise. gas/ * aclocal.m4: Regenerate. * configure: Likewise. * Makefile.in: Likewise. * doc/Makefile.in: Likewise. ld/ * aclocal.m4: Regenerate. * configure: Likewise. * Makefile.in: Likewise. opcodes/ * aclocal.m4: Regenerate. * configure: Likewise. * Makefile.in: Likewise. binutils/ * aclocal.m4: Regenerate. * configure: Likewise. * Makefile.in: Likewise. * doc/Makefile.in: Likewise. gprof/ * aclocal.m4: Regenerate. * configure: Likewise. * Makefile.in: Likewise.	2008-03-17 22:17:33 +00:00
Alan Modra	50e7d84b42	bfd/ * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * po/SRC-POTFILES.in: Regenerate. bfd/doc/ * Makefile.in: Regenerate. binutils/ * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * doc/Makefile.in: Regenerate. * configure: Regenerate. gas/ * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * configure: Regenerate. gprof/ * configure: Regenerate. ld/ * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * configure: Regenerate. opcodes/ * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate. * configure: Regenerate.	2008-03-13 02:05:23 +00:00
Alan Modra	de866fccd8	* ppc-opc.c (powerpc_opcodes): Order and format.	2008-03-06 23:00:34 +00:00
Andreas Krebbel	98c3d90597	2008-03-06 Florian Krohm <fkrohm@us.ibm.com> * s390-opc.c (INSTR_RSL_R0RD): Fix operands. * s390-opc.txt (cmpsc): Duplicate entry removed. (dxr, sqdr, sqer, cxfbr, cdfbr, cefbr, lzer, lzdr, lzxr, cegbr, cdgbr, cxgbr, cegr, cdgr, cxgr, cxfr, cdfr, cefr, fixr, fidr, fier, cu42, cu41): Fix operand format. 2008-03-06 Andreas Krebbel <krebbel1@de.ibm.com> * gas/s390/esa-g5.d (cdfbr, cdfr, cefbr, cefr, cxfbr, cxfr, dxr, fidr, fier, fixr, lzdr, lzer, lzxr, sqdr, sqer, tp): Fix operand format. * gas/s390/esa-g5.s: Likewise. * gas/s390/zarch-z900.d (cdgbr, cdgr, cegbr, cegr, cxgbr, cxgr): Likewise. * gas/s390/zarch-z900.s: Likewise. * gas/s390/zarch-z9-109.d (cu41, cu42): Remove mask operand. * gas/s390/zarch-z9-109.s: Likewise.	2008-03-06 12:01:13 +00:00
H.J. Lu	28dbc07952	gas/testsuite/ 2008-03-01 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/x86-64-branch.s: Add tests for 16-bit near indirect branches. * gas/i386/x86-64-inval.s: Remove tests for 16-bit near indirect branches. * gas/i386/x86-64-branch.d: Updated. * gas/i386/x86-64-inval.l: Likewise. opcodes/ 2008-03-01 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Allow 16-bit near indirect branches for x86-64. * i386-tbl.h: Regenerated.	2008-03-01 23:30:51 +00:00
H.J. Lu	849830bdfb	gas/testsuite/ 2008-02-23 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/jump.s: Add tests for far branches. * gas/i386/jump16.s: Likewise. * gas/i386/jump.d: Updated. * gas/i386/jump16.d: Likewise. * gas/i386/x86-64-inval.l: Likewise. * gas/i386/x86-64-inval.s: Add tests for 16-bit near indirect branches. opcodes/ 2008-02-23 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Disallow 16-bit near indirect branches for x86-64. * i386-tbl.h: Regenerated.	2008-02-23 17:29:17 +00:00
Jan Beulich	743ddb6b3d	opcodes/ 2008-02-21 Jan Beulich <jbeulich@novell.com> * i386-opc.tbl: Allow Dword for far indirect call. Allow Dword and Fword for far indirect jmp. Allow Reg16 and Word for near indirect jmp on x86-64. Disallow Fword for lcall. * i386-tbl.h: Re-generate.	2008-02-21 16:18:04 +00:00
Nick Clifton	796d53134a	* cr16.h (cr16_num_optab): Declared. * cr16-opc.c (cr16_num_optab): Defined	2008-02-18 13:46:45 +00:00
H.J. Lu	65da13b5e0	gas/ 2008-02-16 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (inoutportreg): New. (process_immext): New. (md_assemble): Use it. (update_imm): Use imm16 and imm32s. (i386_att_operand): Use inoutportreg. opcodes/ 2008-02-16 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (operand_type_init): Add OPERAND_TYPE_INOUTPORTREG. * i386-init.h: Regenerated.	2008-02-16 16:16:48 +00:00
Nick Clifton	0e3361806e	PR binutils/5524 * configure.in (SHARED_LIBADD): Select the correct host specific file extension for shared libraries. * configure: Regenerate.	2008-02-14 12:33:17 +00:00
Jan Beulich	b7240065b3	gas/ 2008-02-13 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (parse_real_register): Don't return 'FLAT' if not in Intel mode. (i386_intel_operand): Ignore segment overrides in immediate and offset operands. (intel_e11): Range-check i.mem_operands before use as array index. Filter out FLAT for uses other than as segment override. (intel_get_token): Remove broken promotion of "FLAT:" to mean "offset FLAT:". gas/testsuite/ 2008-02-13 Jan Beulich <jbeulich@novell.com> * gas/i386/intelok.s: Replace invalid offset expression with valid ones. * gas/i386/x86_64.s: Likewise. opcodes/ 2008-02-13 Jan Beulich <jbeulich@novell.com> * i386-opc.h (RegFlat): New. * i386-reg.tbl (flat): Add. * i386-tbl.h: Re-generate.	2008-02-13 13:41:26 +00:00
Jan Beulich	34b772a651	gas/ 2008-02-13 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (intel_e09): Also special-case 'bound'. gas/testsuite/ 2008-02-13 Jan Beulich <jbeulich@novell.com> * gas/i386/intelbad.s, gas/i386/intelok.s: Add 'bound' tests. * gas/i386/intelbad.l, gas/i386/intelok.l, gas/i386/intelok.e, gas/i386/opcode-intel.d: Adjust. opcodes/ 2008-02-13 Jan Beulich <jbeulich@novell.com> * i386-dis.c (a_mode): New. (cond_jump_mode): Adjust. (Ma): Change to a_mode. (intel_operand_size): Handle a_mode. * i386-opc.tbl: Allow Dword and Qword for bound. * i386-tbl.h: Re-generate.	2008-02-13 13:29:31 +00:00
Jan Beulich	a60de03c61	gas/ 2008-02-13 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (allow_pseudo_reg): New. (parse_real_register): Check for NULL just once. Allow all register table entries when allow_pseudo_reg is non-zero. Don't allow any registers without type when allow_pseudo_reg is zero. (tc_x86_regname_to_dw2regnum): Replace with ... (tc_x86_parse_to_dw2regnum): ... this. (tc_x86_frame_initial_instructions): Adjust for above change. * config/tc-i386.h (tc_regname_to_dw2regnum): Remove. (tc_parse_to_dw2regnum): New. (tc_x86_regname_to_dw2regnum): Replace with ... (tc_x86_parse_to_dw2regnum): ... this. * dw2gencfi.c (tc_parse_to_dw2regnum): New, broken out of ... (cfi_parse_reg): ... this. Use tc_parse_to_dw2regnum. Adjust error handling. gas/testsuite/ 2008-02-13 Jan Beulich <jbeulich@novell.com> * gas/cfi/cfi-i386.s: Add code testing use of all registers. Fix a few comments. * gas/cfi/cfi-x86_64.s: Likewise. * gas/cfi/cfi-i386.d, gas/cfi/cfi-x86_64.d: Adjust. opcodes/ 2008-02-13 Jan Beulich <jbeulich@novell.com> * i386-gen.c (process_i386_registers): Process new fields. * i386-opc.h (reg_entry): Shrink reg_flags and reg_num to unsigned char. Add dw2_regnum and Dw2Inval. * i386-reg.tbl: Provide initializers for dw2_regnum. Add pseudo register names. * i386-tbl.h: Re-generate.	2008-02-13 10:14:40 +00:00
H.J. Lu	4b6bc8ebeb	Correct last 2 ChangeLog entries.	2008-02-12 17:22:02 +00:00
H.J. Lu	f03fe4c110	gas/ 2008-02-11 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (cpu_arch): Add .xsave. (md_show_usage): Add .xsave. * doc/c-i386.texi: Add xsave to -march=. gas/testsuite/ 2008-02-11 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-10.s: Add xgetbv. * gas/i386/arch-10.d: Updated. * gas/i386/arch-10-1.l: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/x86-64-arch-10.d: Likewise. opcodes/ 2008-02-11 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Add CPU_XSAVE_FLAGS. * i386-init.h: Updated.	2008-02-12 05:35:36 +00:00
H.J. Lu	475a2301db	gas/testsuite/ 2002-02-11 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run xsave, xsave-intel, x86-64-xsave and x86-64-xsave-intel. * gas/i386/x86-64-xsave-intel.d: New file. * gas/i386/x86-64-xsave.d: Likewise. * gas/i386/x86-64-xsave.s: Likewise. * gas/i386/xsave-intel.d: Likewise. * gas/i386/xsave.d: Likewise. * gas/i386/xsave.s: Likewise. opcodes/ 2008-02-11 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flags): Add CpuXsave. * i386-opc.h (CpuXsave): New. (Cpu64): Updated. (i386_cpu_flags): Add cpuxsave. * i386-dis.c (MOD_0FAE_REG_4): New. (RM_0F01_REG_2): Likewise. (MOD_0FAE_REG_5): Updated. (RM_0F01_REG_3): Likewise. (reg_table): Use MOD_0FAE_REG_4. (mod_table): Use RM_0F01_REG_2. Add MOD_0FAE_REG_4. Updated for xrstor. (rm_table): Add RM_0F01_REG_2. * i386-opc.tbl: Add xsave, xrstor, xgetbv and xsetbv. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	2008-02-12 00:04:45 +00:00
Ben Elliston	041179fc63	Fix formatting of most recent entry.	2008-02-11 22:56:13 +00:00
Jan Beulich	595785c698	opcodes/ 2008-02-11 Jan Beulich <jbeulich@novell.com> * i386-opc.tbl: Remove Disp32S from CpuNo64 opcodes. Remove Disp16 from Cpu64 non-jump opcodes (including loop and j?cxz). * i386-tbl.h: Re-generate.	2008-02-11 15:11:06 +00:00
H.J. Lu	bb8541b9c4	bfd/ 2008-02-04 Kai Tietz <kai.tietz@onevision.com> H.J. Lu <hongjiu.lu@intel.com> PR 5715 * warning.m4: Enable -Wno-format by default when using gcc on mingw. * configure: Regenerated. binutils/ 2008-02-04 H.J. Lu <hongjiu.lu@intel.com> PR 5715 * configure: Regenerated. gas/ 2008-02-04 H.J. Lu <hongjiu.lu@intel.com> PR 5715 * configure: Regenerated. ld/ 2008-02-04 H.J. Lu <hongjiu.lu@intel.com> PR 5715 * configure: Regenerated. opcodes/ 2008-02-04 H.J. Lu <hongjiu.lu@intel.com> PR 5715 * configure: Regenerated.	2008-02-04 19:43:51 +00:00
Adam Nemet	57b592a36d	* mips-dis.c: Update copyright. (mips_arch_choices): Add Octeon. * mips-opc.c: Update copyright. (IOCT): New macro. (mips_builtin_opcodes): Add Octeon instruction synciobdma.	2008-02-04 19:26:11 +00:00
Alan Modra	930bb4cfae	* ppc-opc.c: Support optional L form mtmsr.	2008-01-29 08:24:43 +00:00
H.J. Lu	82c18208b8	gas/testsuite/ 2008-01-24 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/x86-64-sib.s: Add tests for r12. * gas/i386/x86-64-sib-intel.d: Updated. * gas/i386/x86-64-sib.d: Likewise. opcodes/ 2008-01-24 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_E_extended): Handle r12 like rsp.	2008-01-24 15:11:35 +00:00
H.J. Lu	599121aa77	gas/ 2008-01-23 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (md_show_usage): Replace tabs with spaces. gas/testsuite/ 2008-01-23 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp : Run x86-64-arch-1 and x86-64-arch-10. * gas/i386/x86-64-arch-1.d: New. * gas/i386/x86-64-arch-1.s: Likewise. * gas/i386/x86-64-arch-10.d: Likewise. opcodes/ 2008-01-23 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Add CpuLM to CPU_GENERIC64_FLAGS. * i386-init.h: Regenerated.	2008-01-23 19:05:12 +00:00
Tristan Gingold	80098f5188	2008-01-23 Tristan Gingold <gingold@adacore.com> * ia64-dis.c (print_insn_ia64): Display symbolic name of ar.fcr, ar.eflag, ar.csd, ar.ssd, ar.cflg, ar.fsr, ar.fir and ar.fdr.	2008-01-23 08:53:44 +00:00
H.J. Lu	115c7c25fe	gas/ 2008-01-22 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (i386_target_format): Remove cpummx2. gas/testsuite/ 2008-01-22 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-10.d: New. * gas/i386/arch-11.s: Likewise. * gas/i386/arch-12.d: Likewise. * gas/i386/arch-12.s: Likewise. * gas/i386/i386.exp: Run arch-11 and arch-12. opcodes/ 2008-01-22 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Remove CpuMMX2. (cpu_flags): Likewise. * i386-opc.h (CpuMMX2): Removed. (CpuSSE): Updated. * i386-opc.tbl: Replace CpuMMX2 with CpuSSE\|Cpu3dnowA. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	2008-01-22 19:57:30 +00:00
H.J. Lu	6305a20382	gas/ 2008-01-22 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (XXX_PREFIX): Moved from tc-i386.h. (XXX_MNEM_SUFFIX): Likewise. (END_OF_INSN): Likewise. (templates): Likewise. (modrm_byte): Likewise. (rex_byte): Likewise. (DREX_XXX): Likewise. (drex_byte): Likewise. (sib_byte): Likewise. (processor_type): Likewise. (arch_entry): Likewise. (cpu_sub_arch_name): Remove const. (cpu_arch): Add .vmx and .smx. (set_cpu_arch): Append cpu_sub_arch_name. (md_parse_option): Support -march=CPU[,+EXTENSION...]. (md_show_usage): Updated. * config/tc-i386.h (XXX_PREFIX): Moved to tc-i386.c. (XXX_MNEM_SUFFIX): Likewise. (END_OF_INSN): Likewise. (templates): Likewise. (modrm_byte): Likewise. (rex_byte): Likewise. (DREX_XXX): Likewise. (drex_byte): Likewise. (sib_byte): Likewise. (processor_type): Likewise. (arch_entry): Likewise. * doc/as.texinfo: Update i386 -march option. * doc/c-i386.texi: Update -march= for ISA. gas/testsuite/ 2008-01-22 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-10-1.l: New. * gas/i386/arch-10-1.s: Likewise. * gas/i386/arch-10-2.l: Likewise. * gas/i386/arch-10-2.s: Likewise. * gas/i386/arch-10-3.l: Likewise. * gas/i386/arch-10-3.s: Likewise. * gas/i386/arch-10-4.l: Likewise. * gas/i386/arch-10-4.s: Likewise. * gas/i386/arch-10.d: Likewise. * gas/i386/arch-10.s: Likewise. * gas/i386/i386.exp: Run arch-10, arch-10-1, arch-10-2, arch-10-3 and arch-10-4. * gas/i386/nops-2.s: Use movsbl instead of cmove. * gas/i386/nops-2-i386.d: Updated. * gas/i386/nops-2-merom.d: Likewise. * gas/i386/nops-2.d: Likewise. * gas/i386/x86-64-nops-2.d: Likewise. opcodes/ 2008-01-22 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Add CPU_VMX_FLAGS and CPU_SMX_FLAGS. * i386-init.h: Regenerated.	2008-01-22 19:16:45 +00:00
H.J. Lu	fd07a1c880	gas/testsuite/ 2008-01-15 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/prescott.s: Add tests for movddup in Intel syntax. * gas/i386/x86-64-prescott.s: Likewise. * gas/i386/prescott.d: Updated. * gas/i386/x86-64-prescott.d: Likewise. opcodes/ 2008-01-15 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Use Qword on movddup. * i386-tbl.h: Regenerated.	2008-01-16 00:05:56 +00:00
H.J. Lu	321fd21e2f	gas/ 2008-01-15 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (md_assemble): Also zap movzx and movsx suffix for AT&T syntax. gas/testsuite/ 2008-01-15 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.s: Add more tests for movsx and movzx. * gas/i386/x86_64.s: Likewise. * gas/i386/inval.s: Remove tests for movsxw and movzxw. * gas/i386/x86-64-inval.s: Remove tests for movsxb, movsxw, movsxl, movzxb and movzxw. * gas/i386/i386.d: Updated. * gas/i386/inval.l: Likewise. * gas/i386/x86_64.d: Likewise. * gas/i386/x86-64-inval.l: Likewise. opcodes/ 2008-01-15 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Put back 16bit movsx/movzx for AT&T syntax. * i386-tbl.h: Regenerated.	2008-01-15 18:50:44 +00:00
H.J. Lu	4ee521786f	2008-01-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (Mx): New. (PREFIX_0FC3): Likewise. (PREFIX_0FC7_REG_6): Updated. (dis386_twobyte): Use PREFIX_0FC3. (prefix_table): Add PREFIX_0FC3. Use Mq on movntq and movntsd. Use Mx on movntps, movntpd, movntdq and movntdqa. Use Md on movntss.	2008-01-15 17:20:50 +00:00
H.J. Lu	5c07affcae	gas/ 2008-01-14 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (match_reg_size): New. (match_mem_size): Likewise. (operand_size_match): Likewise. (operand_type_match): Also clear all size fields. (match_template): Skip Intel syntax when in AT&T syntax. Call operand_size_match to check operand size. (i386_att_operand): Set the mem field to 1 for memory operand. (i386_intel_operand): Likewise. gas/testsuite/ 2008-01-14 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.s: Add tests for movsx, movzx and movnti. * gas/i386/inval.s: Likewise. * gas/i386/x86_64.s: Likewise. * gas/i386/x86-64-inval.s: Likewise. * gas/i386/i386.d: Updated. * gas/i386/inval.l: Likewise. * gas/i386/x86_64.d: Likewise. * gas/i386/x86-64-inval.l: Likewise. opcodes/ 2008-01-14 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Add IntelSyntax. (operand_types): Add Mem. * i386-opc.h (IntelSyntax): New. * i386-opc.h (Mem): New. (Byte): Updated. (Opcode_Modifier_Max): Updated. (i386_opcode_modifier): Add intelsyntax. (i386_operand_type): Add mem. * i386-opc.tbl: Remove Reg16 from movnti. Add sizes to more instructions. * i386-reg.tbl: Add size for accumulator. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	2008-01-15 01:37:56 +00:00
H.J. Lu	0d6a2f58b8	2008-01-13 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h (Byte): Fix a typo.	2008-01-14 05:15:06 +00:00
H.J. Lu	7d5e4556a3	gas/testsuite/ 2008-01-12 H.J. Lu <hongjiu.lu@intel.com> PR gas/5534 * gas/i386/i386.s: Add tests for fnstsw and fstsw. * gas/i386/inval.s: Likewise. * gas/i386/x86_64.s: Likewise. * gas/i386/intel.s: Use word instead of dword on ss. * gas/i386/x86-64-inval.s: Add tests for fnstsw, fstsw, in and out. * gas/i386/prefix.s: Remove invalid fstsw. * gas/i386/inval.l: Updated. * gas/i386/intelbad.l: Likewise. * gas/i386/i386.d: Likewise. * gas/i386/x86_64.d: Likewise. * gas/i386/x86-64-inval.l: Likewise. * gas/i386/prefix.d: Updated. gas/ 2008-01-12 H.J. Lu <hongjiu.lu@intel.com> PR gas/5534 * config/tc-i386.c (_i386_insn): Update comment. (operand_type_match): Also clear unspecified. (operand_type_register_match): Likewise. (parse_operands): Initialize unspecified. (i386_intel_operand): Likewise. (match_template): Check memory and accumulator operand size. (i386_att_operand): Clear unspecified on register operand. (intel_e11): Likewise. (intel_e09): Set operand size and clean unspecified for "XXX PTR". opcodes/ 2008-01-12 H.J. Lu <hongjiu.lu@intel.com> PR gas/5534 * i386-gen.c (operand_type_init): Add Dword to OPERAND_TYPE_ACC32. Add Qword to OPERAND_TYPE_ACC64. (opcode_modifiers): Remove CheckSize, Byte, Word, Dword, Qword and Xmmword. (operand_types): Add Byte, Word, Dword, Fword, Qword, Tbyte, Xmmword, Unspecified and Anysize. (set_bitfield): Make Mmword an alias of Qword. Make Oword an alias of Xmmword. * i386-opc.h (CheckSize): Removed. (Byte): Updated. (Word): Likewise. (Dword): Likewise. (Qword): Likewise. (Xmmword): Likewise. (FWait): Updated. (OTMax): Likewise. (i386_opcode_modifier): Remove checksize, byte, word, dword, qword and xmmword. (Fword): New. (TBYTE): Likewise. (Unspecified): Likewise. (Anysize): Likewise. (i386_operand_type): Add byte, word, dword, fword, qword, tbyte xmmword, unspecified and anysize. * i386-opc.tbl: Updated to use Byte, Word, Dword, Fword, Qword, Tbyte, Xmmword, Unspecified and Anysize. * i386-reg.tbl: Add size for accumulator. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	2008-01-12 16:05:42 +00:00
H.J. Lu	b5b1fc4fc8	gas/testsuite/ 2008-01-10 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/nops.s: Add more tests with opcodes from 0x0f19 to 0x0f1f. * gas/i386/x86-64-nops.s: Likewise. * gas/i386/nops.d: Updated. * gas/i386/x86-64-nops.d: Likewise. opcodes/ 2008-01-10 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (REG_0F0E): Renamed to REG_0F0D. (REG_0F18): Updated. (reg_table): Updated. (dis386_twobyte): Updated. Use "nopQ" on 0x19 to 0x1e. (twobyte_has_modrm): Set 1 for 0x19 to 0x1e.	2008-01-10 14:52:35 +00:00
H.J. Lu	50e8458f68	2008-01-08 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (set_bitfield): Use fail () on error.	2008-01-09 01:24:07 +00:00
H.J. Lu	3d4d5afaf0	2008-01-08 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (lineno): New. (filename): Likewise. (set_bitfield): Report filename and line numer on error. (process_i386_opcodes): Set filename and update lineno. (process_i386_registers): Likewise.	2008-01-08 21:24:16 +00:00
H.J. Lu	e1d4d8936f	gas/ 2008-01-05 H.J. Lu <hongjiu.lu@intel.com> * doc/c-i386.texi: Update .att_mnemonic and .intel_mnemonic. * config/tc-i386.c (set_intel_mnemonic): Set intel_mnemonic only. (md_assemble): Remove Intel mode workaround. (match_template): Check support for old gcc, AT&T mnemonic and Intel Syntax. (md_parse_option): Don't set intel_mnemonic to 0 for OPTION_MOLD_GCC. gas/testsuite/ 2008-01-05 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/intel.s: Add tests for fadd, faddp, fdiv, fdivp, fdivr, fdivrp, fmul, fmulp, fsub, fsubp, fsubr and fsubrp. * gas/i386/intel.d: Updated. * gas/i386/intel.e: Likewise. opcodes/ 2008-01-05 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Rename IntelMnemonic to ATTSyntax. * i386-opc.h (IntelMnemonic): Renamed to .. (ATTSyntax): This (Opcode_Modifier_Max): Updated. (i386_opcode_modifier): Remove intelmnemonic. Add attsyntax and intelsyntax. * i386-opc.tbl: Remove IntelMnemonic and update with ATTSyntax on fsub, fubp, fsubr, fsubrp, div, fdivp, fdivr and fdivrp. * i386-tbl.h: Regenerated.	2008-01-05 17:07:25 +00:00
H.J. Lu	6f143e4d77	2008-01-04 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c: Update copyright to 2008. * i386-opc.h: Likewise. * i386-opc.tbl: Likewise. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	2008-01-04 18:10:08 +00:00
H.J. Lu	c6add5371c	gas/testsuite/ 2008-01-04 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/rexw.d: New. * gas/i386/rexw.s: Likewise. * gas/i386/x86-64-sse4_1-intel.d: Updated. * gas/i386/x86-64-sse4_1.d: Likewise. opcodes/ 2008-01-04 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Add NoRex64 to extractps, movmskpd, movmskps, pextrb, pextrw, pinsrb, pinsrw and pmovmskb. * i386-tbl.h: Regenerated.	2008-01-04 18:03:02 +00:00
H.J. Lu	3629bb00a8	gas/ 2008-01-03 H.J. Lu <hongjiu.lu@intel.com> * gas/config/tc-i386.c (cpu_arch_flags_not): Removed. (cpu_flags_not): Likewise. (cpu_flags_match): Updated to check 64bit and arch. (set_code_flag): Remove cpu_arch_flags_not. (set_16bit_gcc_code_flag): Likewise. (set_cpu_arch): Likewise. (md_begin): Likewise. (parse_insn): Call cpu_flags_match to check 64bit and arch. (match_template): Likewise. gas/testsuite/ 2008-01-03 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-9.d: New file. * gas/i386/arch-9.s: Likewise. * gas/i386/i386.exp: Run arch-9. opcodes/ 2008-01-03 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Remove CpuSSE4_1_Or_5 and CpuSSE4_2_Or_ABM. (cpu_flags): Likewise. * i386-opc.h (CpuSSE4_1_Or_5): Removed. (CpuSSE4_2_Or_ABM): Likewise. (CpuLM): Updated. (i386_cpu_flags): Remove cpusse4_1_or_5 and cpusse4_2_or_abm. * i386-opc.tbl: Replace CpuSSE4_1_Or_5, CpuSSE4_2_Or_ABM and Cpu686\|CpuPadLock with CpuSSE4_1\|CpuSSE5, CpuABM\|CpuSSE4_2 and CpuPadLock, respectively. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	2008-01-04 01:05:45 +00:00
H.J. Lu	24995bd6e3	gas/ 2008-01-03 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (match_template): Use the xmmword field instead of no_xsuf. opcodes/ 2008-01-03 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Remove No_xSuf. * i386-opc.h (No_xSuf): Removed. (CheckSize): Updated. * i386-tbl.h: Regenerated.	2008-01-03 20:09:38 +00:00
H.J. Lu	e0329a2266	gas/testsuite/ 2008-01-02 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-5.d: New file. * gas/i386/arch-5.s: Likewise. * gas/i386/arch-6.d: Likewise. * gas/i386/arch-6.s: Likewise. * gas/i386/arch-7.d: Likewise. * gas/i386/arch-7.s: Likewise. * gas/i386/arch-8.d: Likewise. * gas/i386/arch-8.s: Likewise. * gas/i386/i386.exp: Run arch-5, arch-6, arch-7 and arch-8. opcodes/ 2008-01-02 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Add CpuSSE4_2_Or_ABM to CPU_AMDFAM10_FLAGS, CPU_SSE4_2_FLAGS, CpuABM and CPU_SSE5_FLAGS. (cpu_flags): Add CpuSSE4_2_Or_ABM. * i386-opc.h (CpuSSE4_2_Or_ABM): New. (CpuLM): Updated. (i386_cpu_flags): Add cpusse4_2_or_abm. * i386-opc.tbl: Use CpuSSE4_2_Or_ABM instead of CpuABM\|CpuSSE4_2 on popcnt. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	2008-01-03 05:29:53 +00:00
H.J. Lu	18a2244ddd	Add a missing ','.	2008-01-03 05:27:55 +00:00
H.J. Lu	f2a9c676b7	gas/testsuite/ 2008-01-02 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.s: Add tests for movq. * gas/i386/x86_64.s: Likewise. * gas/i386/i386.d Updated. * gas/i386/x86_64.d: Likewise. opcodes/ 2008-01-02 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h: Update comments.	2008-01-03 03:28:35 +00:00
H.J. Lu	615888ae9f	Fix a typo.	2008-01-03 00:02:26 +00:00
H.J. Lu	d978b5be20	2008-01-02 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Use Qword instead of QWord. * i386-opc.h: Likewise. * i386-opc.tbl: Likewise.	2008-01-02 23:54:47 +00:00
H.J. Lu	582d5eddfe	gas/ 2008-01-02 H.J. Lu <hongjiu.lu@intel.com> PR gas/5534 * config/tc-i386.c (match_template): Handle XMMWORD_MNEM_SUFFIX. Check memory size in Intel mode. (process_suffix): Handle XMMWORD_MNEM_SUFFIX. (intel_e09): Likewise. * config/tc-i386.h (XMMWORD_MNEM_SUFFIX): New. gas/testsuite/ 2008-01-02 H.J. Lu <hongjiu.lu@intel.com> PR gas/5534 * gas/i386/intel.s: Use QWORD on movq instead of DWORD. * gas/i386/inval.s: Add tests for movq. * gas/i386/x86-64-inval.s: Likewise. * gas/i386/inval.l: Updated. * gas/i386/x86-64-inval.l: Likewise. opcodes/ 2008-01-02 H.J. Lu <hongjiu.lu@intel.com> PR gas/5534 * i386-gen.c (opcode_modifiers): Add No_xSuf, CheckSize, Byte, Word, Dword, QWord and Xmmword. * i386-opc.h (No_xSuf): New. (CheckSize): Likewise. (Byte): Likewise. (Word): Likewise. (Dword): Likewise. (QWord): Likewise. (Xmmword): Likewise. (FWait): Updated. (i386_opcode_modifier): Add No_xSuf, CheckSize, Byte, Word, Dword, QWord and Xmmword. * i386-opc.tbl: Add CheckSize\|QWord to movq if IgnoreSize is used. * i386-tbl.h: Regenerated.	2008-01-02 21:43:34 +00:00
H.J. Lu	6c7ac64e17	Move 2007 ChangeLog entries to ChangeLog-2007.	2008-01-02 21:41:02 +00:00
Mark Kettenis	3fe15143a8	* m88k-dis.c (instructions): Fix fcvt.* instructions. From Miod Vallat.	2008-01-02 00:37:44 +00:00
H.J. Lu	4ae6d70300	Fix a typo in ChangeLog.	2007-12-31 16:17:43 +00:00
H.J. Lu	98b528ac84	gas/testsuite/ 2007-12-31 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/inval.s: Add test for cvtsi2ss/cvtsi2sd. * gas/i386/simd.s: Likewise. * gas/i386/x86-64-simd.s: Likewise. * gas/i386/inval.l: Updated. * gas/i386/simd-intel.d: Likewise. * gas/i386/simd-suffix.d: Likewise. * gas/i386/simd.d: Likewise. * gas/i386/sse2.d: Likewise. * gas/i386/x86-64-opcode.d: Likewise. * gas/i386/x86-64-simd-intel.d: Likewise. * gas/i386/x86-64-simd-suffix.d: Likewise. * gas/i386/x86-64-simd.d: Likewise. opcodes/ 2007-12-31 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (prefix_table): Use "%LQ" on cvtpi2ps/cvtsi2sd. (putop): Handle '%' and "LQ". * i386-opc.tbl: Remove IgnoreSize from cvtpi2ps/cvtsi2sd. * i386-tbl.h: Regenerated.	2007-12-31 15:42:22 +00:00
H.J. Lu	70ad4a561e	Add ',' at the end of cpu_flag_init.	2007-12-28 19:42:53 +00:00
H.J. Lu	8d79a8c8d5	gas/testsuite/ 2007-12-28 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/arch-1.d: New file. * gas/i386/arch-1.s: Likewise. * gas/i386/arch-2.d: Likewise. * gas/i386/arch-2.s: Likewise. * gas/i386/arch-3.d: Likewise. * gas/i386/arch-3.s: Likewise. * gas/i386/arch-4.d: Likewise. * gas/i386/arch-4.s: Likewise. * gas/i386/i386.exp: Run arch-1, arch-2, arch-3 and arch-4. opcodes/ 2007-12-28 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (cpu_flag_init): Add CpuSSE4_1_Or_5 to CPU_SSE4_1_FLAGS, CPU_SSE4_2_FLAGS and CPU_SSE5_FLAGS. (cpu_flags): Add CpuSSE4_1_Or_5. * i386-init.h: Regenerated. * i386-tbl.h: Likewise. * i386-opc.h (CpuSSE4_1_Or_5): New. (CpuLM): Updated. (i386_cpu_flags): Add cpusse4_1_or_5. * i386-opc.tbl: Use CpuSSE4_1_Or_5 instead of CpuSSE4_1\|CpuSSE5 on ptest roundpd, roundps, roundsd and roundss.	2007-12-28 16:04:41 +00:00
H.J. Lu	1efbbeb461	gas/ 2007-12-23 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (set_intel_mnemonic): New. (intel_mnemonic): Likewise. (old_gcc): Likewise. (OPTION_MMNEMONIC): Likewise. (OPTION_MSYNTAX): Likewise. (OPTION_MINDEX_REG): Likewise. (OPTION_MNAKED_REG): Likewise. (OPTION_MOLD_GCC): Likewise. (md_pseudo_table): Add .intel_mnemonic and .att_mnemonic. (match_template): Don't allow AT&T/Intel mnemonic if Intel/AT&T mnemonic is specified. Don't allow old gcc support if old_gcc is 0. (md_longopts): Add -mmnemonic, -msyntax, -mindex-reg, -mmnaked-reg and -mold-gcc. (md_parse_option): Handle OPTION_MMNEMONIC, OPTION_MSYNTAX, OPTION_MINDEX_REG, OPTION_MNAKED_REG and OPTION_MOLD_GCC. * doc/c-i386.texi: Docoument -mmnemonic, -msyntax, --mnaked-reg and AT&T mnemonic vs. Intel mnemonic. gas/testsuite/ 2007-12-23 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/compat-intel.d: Pass -mmnemonic=att to assembler. * gas/i386/compat.d: Likewise. * gas/i386/i386.exp: Pass -mmnemonic=att to assembler for "float". Pass -mold-gcc to assembler for "general". opcodes/ 2007-12-23 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Add OldGcc, ATTMnemonic and IntelMnemonic. * i386-opc.h (OldGcc): New. (ATTMnemonic): Likewise. (IntelMnemonic): Likewise. (Opcode_Modifier_Max): Updated. (i386_opcode_modifier): Add oldgcc, attmnemonic and intelmnemonic. * i386-opc.tbl: Update fadd, fdiv, fdivp, fdivr, fdivrp, fmul, fsub, fsubp, fsubr and fsubrp with OldGcc, ATTMnemonic and IntelMnemonic. * i386-tbl.h: Regeneratd.	2007-12-24 05:27:39 +00:00
H.J. Lu	9d14166966	binutils/ 2007-12-22 H.J. Lu <hongjiu.lu@intel.com> * doc/binutils.texi: Document the new intel-mnemonic and intel-mnemonic options for i386 disassembler. gas/testsuite/ 2007-12-22 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/compat-intel.d: New file. * gas/i386/compat.d: Likewise. * gas/i386/compat.s: Likewise. * gas/i386/i386.exp: Run compat. opcodes/ 2007-12-22 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (intel_mnemonic): New. (print_i386_disassembler_options): Display att-mnemonic and intel-mnemonic options. (print_insn): Handle att-mnemonic and intel-mnemonic. (float_reg): Replace SYSV386_COMPAT with "!M" and "M". (putop): Handle "!M" and "M".	2007-12-22 14:06:31 +00:00
H.J. Lu	df1764b8ab	2007-12-21 H.J. Lu <hongjiu.lu@intel.com> * Makefile.am (i386-gen.o): Also depend on $(srcdir)/../include/opcode/i386.h. * Makefile.in: Regenerated.	2007-12-21 17:04:04 +00:00
Mark Shinwell	350cc38db2	bfd/ * archures.c (bfd_mach_mips_loongson_2e): New. (bfd_mach_mips_loongson_2f): New. * bfd-in2.h (bfd_mach_mips_loongson_2e): New. (bfd_mach_mips_loongson_2f): New. * cpu-mips.c: Add I_loongson_2e and I_loongson_2f to anonymous enum. (arch_info_struct): Add Loongson-2E and Loongson-2F entries. * elfxx-mips.c (_bfd_elf_mips_mach): Handle Loongson-2E and Loongson-2F flags. (mips_set_isa_flags): Likewise. (mips_mach_extensions): Add Loongson-2E and Loongson-2F entries. binutils/ * readelf.c (get_machine_flags): Handle Loongson-2E and -2F flags. gas/ * config/tc-mips.c (mips_cpu_info_table): Add loongson2e and loongson2f entries. * doc/c-mips.texi: Document -march=loongson{2e,2f} options. gas/testsuite/ * gas/mips/mips.exp: Add loongson-2e and -2f tests. * gas/mips/loongson-2e.d: New. * gas/mips/loongson-2e.s: New. * gas/mips/loongson-2f.d: New. * gas/mips/loongson-2f.s: New. include/elf/ * mips.h (E_MIPS_MACH_LS2E): New. (E_MIPS_MACH_LS2F): New. include/opcode/ * mips.h (INSN_LOONGSON_2E): New. (INSN_LOONGSON_2F): New. (CPU_LOONGSON_2E): New. (CPU_LOONGSON_2F): New. (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags. opcodes/ * mips-dis.c (mips_arch_choices): Add Loongson-2E and -2F entries. * mips-opc.c (IL2E): New. (IL2F): New. (mips_builtin_opcodes): Add Loongson-2E and -2F instructions. Allow movz and movn for Loongson-2E and -2F. Add movnz entry. Move coprocessor encodings to the end of the table. Allow certain MIPS V .ps instructions on the Loongson-2E and -2F.	2007-11-29 12:23:44 +00:00
Mark Shinwell	569502941a	include/opcode/ * mips.h (INSN_ISA): Redefine certain values as an enumeration. Update comments. (mips_isa_table): New. (ISA_MIPS): Redefine to match enumeration. (OPCODE_IS_MEMBER): Modify to correctly test new INSN_ISA* values. opcodes/ * mips-opc.c (I3_32, I3_33, I4_32, I4_33, I5_33): New. (mips_builtin_opcodes): Use these new I* values.	2007-11-29 11:55:19 +00:00
Andreas Krebbel	5f1c91d91e	2007-11-27 Andreas Krebbel <krebbel1@de.ibm.com> * s390-opc.txt ("tcet", "tcdt", "tcxt", "tget", "tgdt", "tgxt"): Removed. ("tdcet", "tdcdt", "tdcxt", "tdget", "tdgdt", "tdgxt"): Added.	2007-11-27 15:33:28 +00:00
Andreas Krebbel	967877645e	2007-11-27 Andreas Krebbel <krebbel1@de.ibm.com> * s390-opc.txt ("tcet", "tcdt", "tcxt", "tget", "tgdt", "tgxt"): Removed. ("tdcet", "tdcdt", "tdcxt", "tdget", "tdgdt", "tdgxt"): Added. 2007-11-27 Andreas Krebbel <krebbel1@de.ibm.com> * gas/s390/zarch-z9-ec.d: ("tcet", "tcdt", "tcxt", "tget", "tgdt", "tgxt"): Removed. ("tdcet", "tdcdt", "tdcxt", "tdget", "tdgdt", "tdgxt"): Added. * gas/s390/zarch-z9-ec.s: Likewise.	2007-11-27 15:31:59 +00:00
H.J. Lu	4f8631b1d4	gas/ 2007-11-14 Tristan Gingold <gingold@adacore.com> * config/tc-ia64.c (AR_RUC): Defined. (ar): Add "ar.ruc". (specify_resource): Handle AR_RUC like AR_ITC. gas/testsuite/ 2007-11-14 H.J. Lu <hongjiu.lu@intel.com> * gas/ia64/dv-raw-err.s: Add tests for ar.ruc. * gas/ia64/dv-waw-err.s: Likewise. * gas/ia64/invalid-ar.s: Likewise. * gas/ia64/regs.s: Add tests for ar.ruc and ar44. * gas/ia64/dv-raw-err.l: Updated. * gas/ia64/dv-waw-err.l: Likewise. * gas/ia64/invalid-ar.l: Likewise. * gas/ia64/regs.d: Likewise. opcodes/ 2007-11-14 H.J. Lu <hongjiu.lu@intel.com> * ia64-ic.tbl: Updated for Itanium 9100 series. * ia64-raw.tbl: Likewise. * ia64-waw.tbl: Likewise. * ia64-asmtab.c: Regenerated. 2007-11-14 Tristan Gingold <gingold@adacore.com> * ia64-dis.c (print_insn_ia64): Handle ar.ruc. * ia64-gen.c (lookup_regindex): Likewise.	2007-11-14 22:31:54 +00:00
Nick Clifton	57d85092b1	PR gas/5228 * m68k-opc.c (m68k_opcodes): Fix coldfire msac.w instructions with parallel loads.	2007-11-07 16:37:44 +00:00
Tristan Gingold	679936aac4	* ia64-dis.c (print_insn_ia64): Generate symbolic names for cr registers instead of register number. * gas/ia64/regs.d: Expect symbolic names for cr registers due to improved disassembler.	2007-11-07 15:57:14 +00:00
Nick Clifton	92c8bd791d	* arm-dis.c (arm_opcodes): Remove superflous escapes of percent operators.	2007-11-07 14:40:40 +00:00
Peter Bergner	548b1dcfcb	* ppc-opc.c (powerpc_opcodes): Remove the dcffix and dcffix. opcodes which are not included in the "Preliminary Decimal Floating-Point Architecture" document.	2007-11-06 23:14:07 +00:00
H.J. Lu	7ce189b305	gas/ 2007-11-01 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (md_assemble): Replace no_xsuf with no_ldsuf. (match_template): Likewise. opcodes/ 2007-11-01 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Replace No_xSuf with No_ldSuf. * i386-opc.tbl: Likewise. * i386-opc.h (No_xSuf): Renamed to ... (No_ldSuf): This. (FWait): Updated.	2007-11-01 19:06:54 +00:00
H.J. Lu	ca61edf2ff	gas/ 2007-11-01 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_suffix): Check addrprefixop0 to see if the address size override prefix changes the size of the first operand. (check_byte_reg): Don't warn if byteokintel is set. (check_long_reg): Set i.suffix to QWORD_MNEM_SUFFIX if toqword is set. (check_qword_reg): Set i.suffix to LONG_MNEM_SUFFIX if todword is set. gas/testsuite/ 2007-11-01 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.d: New. * gas/i386/i386.s: Likewise. * gas/i386/i386.exp: Run i386. * gas/i386/x86_64.s: Add tests for movsx, movsbl, movsbq, movsbw, movswl, movswq, movzx, movzb, movzbl, movzbq, movzbw, movzwl and movzwq. * gas/i386/x86_64.d: Updated. opcodes/ 2007-11-01 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Add ByteOkIntel, ToDword, ToQword and AddrPrefixOp0. * i386-opc.h (ByteOkIntel): New. (ToDword): Likewise. (ToQword): Likewise. (AddrPrefixOp0): Likewise. (IsPrefix): Updated. (i386_opcode_modifier): Add byteokintel, todword, toqword and addrprefixop0. * i386-opc.tbl (cvtss2si): Add ToQword. (cvttss2si): Likewise. (cvtsd2si): Add ToDword. (cvttsd2si): Likewise. (monitor): Add AddrPrefixOp0. (invlpga): Likewise. (vmload): Likewise. (vmrun): Likewise. (vmsave): Likewise. (pextrb): Add ByteOkIntel. (pinsrb): Likewise. * i386-tbl.h: Regenerated.	2007-11-01 16:27:08 +00:00
H.J. Lu	1b0d430b05	2007-10-31 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (USE_REG_TABLE): Defined as the previous one + 1. (USE_REG_TABLE): Likewise. (USE_MOD_TABLE): Likewise. (USE_RM_TABLE): Likewise. (USE_PREFIX_TABLE): Likewise. (USE_X86_64_TABLE): Likewise. (USE_3BYTE_TABLE): Likewise.	2007-10-31 23:41:12 +00:00
H.J. Lu	75c135a8a4	2007-10-26 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (MOD_0F2B_PREFIX_0...MOD_0F2B_PREFIX_3): New. (MOD_0F51): Likewise. (MOD_0FD7): Likewise. (MOD_0FE7_PREFIX_2): Likewise. (MOD_0F382A_PREFIX_2): Likewise. (MOD_0F71_REG_2): Updated. (MOD_0FF0_PREFIX_3): Likewise. (MOD_62_32BIT): Likewise. (dis386_twobyte): Use MOD_0F51 and MOD_0FD7. (prefix_table): Use MOD_0F2B_PREFIX_0...MOD_0F2B_PREFIX_3, MOD_0FE7_PREFIX_2 and MOD_0F382A_PREFIX_2. (mod_table): Add MOD_0F2B_PREFIX_0...MOD_0F2B_PREFIX_3, MOD_0F51, MOD_0FD7 and MOD_0F382A_PREFIX_2.	2007-10-26 20:48:09 +00:00
Nick Clifton	2cc7bb5dcf	* arm-dis.c (print_insn): Check for a symtab that exists but is empty.	2007-10-26 11:27:12 +00:00
Alan Modra	79f7344f10	* po/POTFILES.in: Regenerate.	2007-10-24 04:57:04 +00:00
H.J. Lu	ad19981d72	gas/testsuite/ 2007-10-23 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/katmai.s: Remove cmpps opcode test. * gas/i386/simd.s: Add tests for cmpss and cmpsd. * gas/i386/x86-64-simd.s: Likewise. * gas/i386/katmai.d: Updated. * gas/i386/simd-intel.d: Likewise. * gas/i386/simd-suffix.d: Likewise. * gas/i386/simd.d: Likewise. * gas/i386/x86-64-simd-intel.d: Likewise. * gas/i386/x86-64-simd-suffix.d: Likewise. * gas/i386/x86-64-simd.d: Likewise. opcodes/ 2007-10-23 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_SIMD_Suffix): Renamed to ... (CMP_Fixup): This. Rewrite. (OPSIMD): Renamed to ... (CMP): This. Updated. (prefix_table): Update PREFIX_0FC2 entry.	2007-10-23 22:52:09 +00:00
H.J. Lu	92fddf8e3d	2007-10-22 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (prefix_table): Reordered by opcode. (mod_table): Likewise.	2007-10-22 19:22:01 +00:00
H.J. Lu	6a718ea22c	2007-10-19 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (prefix_table): Use XS on psrldq and pslldq.	2007-10-19 23:24:00 +00:00
Nathan Sidwell	25b07cd9c4	opcodes/ * m68k-opc.c (m68k_opcodes): Correct move sr and ccr masks for coldfire. gas/testsuite/ * gas/m68k/mcf-movsr.s: New. * gas/m68k/mcf-movsr.d: New. * gas/m68k/all.exp: Add mcf-movsr test.	2007-10-17 13:44:09 +00:00
Peter Bergner	91eb7075e3	* ppc-opc.c (powerpc_opcodes): Fix the first two operands of dquaiq. to use the TE and FRT macros.	2007-10-16 02:55:30 +00:00
Peter Bergner	8dbcd839b1	gas/ * config/tc-ppc.c (ppc_setup_opcodes): Verify instructions are sorted according to major opcode number. opcodes/ * ppc-opc.c (TE): Correct signedness. (powerpc_opcodes): Sort psq_st and psq_stu according to major opcode number.	2007-10-16 02:26:30 +00:00
H.J. Lu	d5d7db8e2f	2007-10-15 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (dis386_twobyte): Reformat. (prefix_table): Likewise. (three_byte_table): Likewise.	2007-10-15 19:13:55 +00:00
Alan Modra	65be13330d	* mcore-dis.c (print_insn_mcore): Protect "fprintf" var against macro expansion.	2007-10-15 02:01:40 +00:00
H.J. Lu	e2ec9d29b7	gas/ 2007-10-12 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (process_operands): Check the firstxmm0 field in opcode_modifier for instruction with a implicit xmm0 as the first operand. opcodes/ 2007-10-12 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (opcode_modifiers): Add FirstXmm0. * i386-opc.h (FirstXmm0): New. (IsPrefix): Updated. (i386_opcode_modifier): Add firstxmm0. * i386-opc.tbl (blendvpd): Replace RegKludge with FirstXmm0. (blendvps): Likewise. (pblendvb): Likewise. * i386-tbl.h: Regenerated.	2007-10-12 21:40:38 +00:00
H.J. Lu	88a94849aa	2007-10-12 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (prefix_table): Reformat pblendvb and blendvps.	2007-10-12 20:37:58 +00:00
H.J. Lu	630c2cc56d	Remove extra white space.	2007-10-10 22:00:24 +00:00
H.J. Lu	d55ee72f29	2007-10-10 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (v_mode): Defined as previous one + 1. (w_mode): Likewise. (d_mode): Likewise. (q_mode): Likewise. (t_mode): Likewise. (x_mode): Likewise. (m_mode): Likewise. (cond_jump_mode): Likewise. (loop_jcxz_mode): Likewise. (dq_mode): Likewise. (dqw_mode): Likewise. (f_mode): Likewise. (const_1_mode): Likewise. (stack_v_mode): Likewise. (z_mode): Likewise. (o_mode): Likewise. (dqb_mode): Likewise. (dqd_mode): Likewise. (es_reg): Likewise. (cs_reg): Likewise. (ss_reg): Likewise. (ds_reg): Likewise. (fs_reg): Likewise. (gs_reg): Likewise. (eAX_reg): Likewise. (eCX_reg): Likewise. (eDX_reg): Likewise. (eBX_reg): Likewise. (eSP_reg): Likewise. (eBP_reg): Likewise. (eSI_reg): Likewise. (eDI_reg): Likewise. (al_reg): Likewise. (cl_reg): Likewise. (dl_reg): Likewise. (bl_reg): Likewise. (ah_reg): Likewise. (ch_reg): Likewise. (dh_reg): Likewise. (bh_reg): Likewise. (ax_reg): Likewise. (cx_reg): Likewise. (dx_reg): Likewise. (bx_reg): Likewise. (sp_reg): Likewise. (bp_reg): Likewise. (si_reg): Likewise. (di_reg): Likewise. (rAX_reg): Likewise. (rCX_reg): Likewise. (rDX_reg): Likewise. (rBX_reg): Likewise. (rSP_reg): Likewise. (rBP_reg): Likewise. (rSI_reg): Likewise. (rDI_reg): Likewise. (z_mode_ax_reg): Likewise. (indir_dx_reg): Likewise. (DREX_OC1): Updated. (DREX_NO_OC0): Likewise. (DREX_MASK): Likewise. (MAX_BYTEMODE): New. Issue an error if MAX_BYTEMODE is not less than DREX_OC1.	2007-10-10 16:25:02 +00:00
H.J. Lu	8a72226ad5	gas/testsuite/ 2007-10-08 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run simd-suffix and x86-64-simd-suffix. * gas/i386/simd-suffix.d: New. * gas/i386/x86-64-simd-suffix.d: Likewise. * gas/i386/x86-64-opcode.d: Updated. * gas/i386/x86-64-simd.d: Likewise. opcodes/ 2007-10-08 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c: Updated comments for 'Y'. (putop): Don't add 'q' for 'Y' if suffix_always isn't true.	2007-10-08 19:22:01 +00:00
Maciej W. Rozycki	f409fd1e69	opcodes/: * opcodes/mips-dis.c (mips_cp0_names_r3000): New definition. (mips_cp0_names_r4000): Likewise. (mips_arch_choices): Link to the above as appropriate. gas/testsuite/: * gas/mips/cp0-names-r3000.d: New test for R3000 CP0 symbolic disassembly. * gas/mips/cp0-names-r4000.d: New test for R4000/R4400 symbolic CP0 disassembly. * mips/mips.exp: Run the new tests.	2007-10-08 16:41:35 +00:00
Nick Clifton	defeac7384	* configure.in (SHARED_DEPENDENCIES): Change non-cygwin dependency to be ../bfd/libbfd.la. * configure: Regenerate.	2007-10-08 15:40:41 +00:00
H.J. Lu	47dd174cba	gas/testsuite/ 2007-10-05 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/i386.exp: Run smx. * gas/i386/smx.d: New. * gas/i386/smx.s: Likewise. opcodes/ 2007-10-05 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (dis386_twobyte): Add getsec. * i386-gen.c (cpu_flags): Add CpuSMX. * i386-opc.h (CpuSMX): New. (CpuSSSE3): Updated. (i386_cpu_flags): Add cpusmx. * i386-opc.tbl: Add getsec. * i386-init.h: Regenerated. * i386-tbl.h: Likewise.	2007-10-05 19:04:06 +00:00
H.J. Lu	058f233b7a	2007-10-05 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (reg_table): Use "{ XX }" on "(bad)". (prefix_table): Likewise.	2007-10-05 16:28:16 +00:00
H.J. Lu	f2a421c445	gas/testsuite/ 2007-10-04 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/simd.s: Add tests for unpckhpd and unpckhps. * gas/i386/x86-64-simd.s: Likewise. * gas/i386/simd-intel.d: Updated. * gas/i386/simd.d: Likewise. * gas/i386/x86-64-simd-intel.d: Likewise. * gas/i386/x86-64-simd.d: Likewise. opcodes/ 2007-10-04 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (dis386_twobyte): Use EXx instead of EXq on unpckhpX and unpckhpX.	2007-10-04 22:02:10 +00:00
David Daney	c8ab98e0eb	opcodes/ 2007-10-04 David Daney <ddaney@avtrex.com> * mips-opc.c (mips_builtin_opcodes): Mark lwxc1 as working on FP_S registers. gas/testsuite/ 2007-10-04 David Daney <ddaney@avtrex.com> * gas/mips/odd-float.d, gas/mips/odd-float.s: New test. * gas/mips/mips.exp: Run it.	2007-10-04 21:53:06 +00:00
H.J. Lu	df26e7af07	2007-10-04 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (MOD_0F12_PREFIX_0): Use "movlps" and "movhlps" instead of "movlpX" and "movhlpX", respectively. (MOD_0F16_PREFIX_0): Use "movhps" and "movlhps" instead of "movhpX" and "movlhpX", respectively.	2007-10-04 21:02:38 +00:00
Nick Clifton	45d42143d4	* configure.in (WIN32LDFLAGS): Rename to SHARED_LDFLAGS. (WIN32LIBADD): Rename to SHARED_LIBADD (SHARED_DEPENDENCIES): New exported variable. (enable_shared): Add dependency upon libbfd.la for non-cygwin based shared library builds. * Makefile.am (libopcodes_la_DEPENDENCIES): Append SHARED_DEPENDENCIES. (libopcodes_la_LIBADD): Rename WIN32LIBADD to SHARED_LIBADD. (libopcodes_la_LDFLAGS): Rename WIN32LDFLAGS to SHARED_LDFLAGS. * configure: Regenerate. * Makefile.in: Regenerate.	2007-10-04 14:06:40 +00:00
Nick Clifton	9f39ef2bb8	PR gas/5100 * arc-opc.c (insert_offset): Fix spelling mistake in error message.	2007-10-04 13:43:16 +00:00
H.J. Lu	9b60702d0c	2007-10-03 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_REG): Set add to 0 only when needed. (OP_C): Likewise. (OP_D): Likewise. (OP_MMX): Likewise. (OP_XMM): Likewise. (OP_EM): Likewise. (OP_MXC): Likewise. (OP_EX): Likewise.	2007-10-03 19:30:44 +00:00
H.J. Lu	458fa39293	2007-10-03 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.tbl: Update SSE comments.	2007-10-03 19:03:20 +00:00
H.J. Lu	89b66d557a	2007-10-01 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (THREE_BYTE_0FBA): Renamed to ... (THREE_BYTE_0F7B): This. (dis386_twobyte): Updated. (three_byte_table): Updated comments.	2007-10-01 22:23:20 +00:00
Nick Clifton	7fac7ff4ae	Various CR16 fixes	2007-10-01 15:55:44 +00:00
H.J. Lu	4584a60d9f	2007-09-30 H.J. Lu <hongjiu.lu@intel.com> * 386-dis.c (prefix_table): Reformat comment.	2007-09-30 19:14:47 +00:00
H.J. Lu	1ceb70f8ad	2007-09-29 H.J. Lu <hongjiu.lu@intel.com> * 386-dis.c (USE_GROUPS): Renamed to ... (USE_REG_TABLE): This. (USE_OPC_EXT_TABLE): Renamed to ... (USE_MOD_TABLE): This. (USE_OPC_EXT_RM_TABLE): Renamed to ... (USE_RM_TABLE): This. (USE_XXX_TABLE): Reordered. (GRP): Renamed to ... (REG_TABLE): This. (OPC_EXT_TABLE): Renamed to ... (MOD_TABLE): This. (OPC_EXT_RM_TABLE): Renamed to ... (RM_TABLE): This. (GRP_XXX): Renamed to ... (REG_XXX): This. (PREGRP_XXX): Renamed to ... (PREFIX_XXX): This. (OPC_EXT_XXX): Renamed to ... (MOD_XXX): This. (OPC_EXT_RM_XXX): Renamed to ... (RM_XXX): This. (grps): Renamed to ... (reg_table): This (prefix_user_table): Renamed to ... (prefix_table): This (opc_ext_table): Renamed to ... (mod_table): This (opc_ext_rm_table): Renamed to ... (rm_table): This (OPC_EXT_RM_XXX): Likewise. (dis386): Updated. (dis386_twobyte): Likewise. (reg_table): Likewise. (prefix_table): Likewise. (x86_64_table): Likewise. (three_byte_table): Likewise. (mod_table): Likewise. (rm_table): Likewise. (get_valid_dis386): Likewise.	2007-09-29 14:43:44 +00:00
H.J. Lu	4e7d34a6c2	2007-09-28 H.J. Lu <hongjiu.lu@intel.com> * 386-dis.c (USE_PREFIX_USER_TABLE): Renamed to ... (USE_PREFIX_TABLE): This. (X86_64_SPECIAL): Renamed to ... (USE_X86_64_TABLE): This. (IS_3BYTE_OPCODE): Renamed to ... (USE_3BYTE_TABLE): This. (GRPXXX): Removed. (PREGRPXXX): Likewise. (X86_64_XXX): Likewise. (THREE_BYTE_XXX): Likewise. (OPC_EXT_XXX): Likewise. (OPC_EXT_RM_XXX): Likewise. (DIS386): New. (GRP): Likewise. (PREGRP): Likewise. (X86_64_TABLE): Likewise. (THREE_BYTE_TABLE): Likewise. (OPC_EXT_TABLE): Likewise. (OPC_EXT_RM_TABLE): Likewise. (GRP_XXX): Likewise. (PREGRP_XXX): Likewise. (X86_64_XXX): Likewise. (THREE_BYTE_XXX): Likewise. (OPC_EXT_XXX): Likewise. (OPC_EXT_RM_XXX): Likewise. (dis386): Updated. (dis386_twobyte): Likewise. (grps): Likewise. (prefix_user_table): Likewise. (x86_64_table): Likewise. (three_byte_table): Likewise. (opc_ext_table): Likewise. (opc_ext_rm_table): Likewise. (get_valid_dis386): Likewise.	2007-09-28 20:50:59 +00:00
H.J. Lu	6807063ec6	2007-09-27 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (dis386): Swap X86_64_27 with OPC_EXT_2. (x86_64_table): Likewise. (opc_ext_table): Likewise.	2007-09-27 21:53:28 +00:00
H.J. Lu	7c52e0e865	gas/testsuite/gas/ 2007-09-27 H.J. Lu <hongjiu.lu@intel.com> PR binutils/5072 * gas/i386/i386.exp: Run x86-64-opcode-inval and x86-64-opcode-inval-intel. * gas/i386/x86-64-opcode-inval-intel.d: New. * gas/i386/x86-64-opcode-inval.d: Likewise. * gas/i386/x86-64-opcode-inval.s: Likewise. opcodes/ 2007-09-27 H.J. Lu <hongjiu.lu@intel.com> PR binutils/5072 * i386-dis.c: Update comments on '{', '}' and '\|' to support only AT&T and Intel modes. (X86_64_4...X86_64_27): New. (dis386): Updated. Use X86_64_4...X86_64_21. (dis386_twobyte): Updated. (float_mem): Likewise. (x86_64_table): Add X86_64_4...X86_64_27. (opc_ext_table): Updated. Use X86_64_22 and X86_64_27. (putop): Updated handling of '{', '}' and '\|' to support only AT&T and Intel modes.	2007-09-27 18:31:51 +00:00
Kazu Hirata	d0fa13723f	gas/ * config/m68k-parse.h (m68k_register): Use MBO instead of MBB. (last_movec_reg): Change to MBO. * config/tc-m68k.c (fido_ctrl): Use MBO instead of MBB. (m68k_ip): Use MBO instead of MBO. (init_table): Use MBO instead of MBO. Add an entry for mbo. gas/testsuite/ * gas/m68k/fido.s: Add tests for %mbo. * gas/m68k/fido.d: Update accordingly. opcodes/ * m68k-dis.c (print_insn_arg): Use %mbo instead of %mbb.	2007-09-27 11:14:10 +00:00
Jim Wilson	7a53bcd4a8	Fix typo in last patch.	2007-09-26 18:11:04 +00:00
Nick Clifton	168411b181	* mt-asm.c (parse_imm16): Reword error message in order to allow it to be translated properly. * ia64-gen.c (print_dependency_table): Likewise. * mips-dis.c (print_insn_args): Likewise.	2007-09-26 16:07:18 +00:00
Jan Beulich	8776771175	gas/testsuite/ 2007-09-26 Jan Beulich <jbeulich@novell.com> * gas/i386/x86-64-addr32.d: Adjust expectations. opcodes/ 2007-09-26 Jan Beulich <jbeulich@novell.com> * i386-dis.c (OP_E_extended): Distinguish rip- and eip- relative addressing. Update used_prefixes based on whether any base or index register was printed.	2007-09-26 13:42:14 +00:00
Jan Beulich	9a04903eea	gas/ 2007-09-26 Jan Beulich <jbeulich@novell.com> * config/tc-i386.c (build_modrm_byte): Also check for RegEip when considering IP-relative addressing. gas/testsuite/ 2007-09-26 Jan Beulich <jbeulich@novell.com> * gas/i386/reloc64.s: Adjust for %eip-relative addressing no longer generating errors. * gas/i386/reloc64.d, gas/i386/reloc64.l: Update. * gas/i386/x86-64-addr32.s: Remove explicit addr32 prefix for %eip-realtive addressing case. opcodes/ 2007-09-26 Jan Beulich <jbeulich@novell.com> * i386-opc.h (RegEip): Define. (RegEiz): Adjust. * i386-reg.tbl: Add eip. Mark rip and eip with RegRex64. * i386-tbl.h: Re-generate.	2007-09-26 13:40:59 +00:00
H.J. Lu	4dffcebc10	gas/ 2007-09-25 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (output_insn): Use i.tm.opcode_length to check opcode length. opcodes/ 2007-09-25 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (process_i386_opcodes): Process opcode_length. * i386-opc.h (template): Add opcode_length. * 386-opc.tbl: Likewise. * i386-tbl.h: Regenerated.	2007-09-26 04:42:47 +00:00
H.J. Lu	a967d2b76a	2007-09-21 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h: Adjust whitespaces.	2007-09-21 20:51:33 +00:00
Dave Brolley	c99d3d7aef	2007-09-21 Dave Brolley <brolley@redhat.com> * mep-desc.c: Regenerated.	2007-09-21 18:58:47 +00:00
H.J. Lu	20afcfb756	gas/testsuite/ 2007-09-20 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/sib.s: Add more eiz tests. * gas/i386/x86-64-sib.s: Add more riz tests. * gas/i386/sib-intel.d: Updated. * gas/i386/sib.d: Likewise. * gas/i386/x86-64-sib-intel.d: Likewise. * gas/i386/x86-64-sib.d: Likewise. opcodes/ 2007-09-20 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_E_extended): Display eiz for [eiz*1 + offset].	2007-09-20 20:13:26 +00:00
H.J. Lu	db51cc60e2	gas/ 2007-09-20 H.J. Lu <hongjiu.lu@intel.com> PR 658 * config/tc-i386.c (SCALE1_WHEN_NO_INDEX): Removed. (set_allow_index_reg): New. (allow_index_reg): Likewise. (md_pseudo_table): Add "allow_index_reg" and "disallow_index_reg". (build_modrm_byte): Set i.sib.index to NO_INDEX_REGISTER for fake index registers. (i386_scale): Updated. (i386_index_check): Support fake index registers. (parse_real_register): Return NULL on eiz/riz if fake index registers aren't allowed. gas/testsuite/ 2007-09-20 H.J. Lu <hongjiu.lu@intel.com> PR 658 * gas/i386/i386.exp: Run sib-intel, x86-64-sib and x86-64-sib-intel. * gas/i386/nops-1-i386-i686.d: Updated. * gas/i386/nops-1-i386.d: Likewise. * gas/i386/nops-1.d: Likewise. * gas/i386/nops-2-i386.d: Likewise. * gas/i386/nops-2-merom.d: Likewise. * gas/i386/nops-2.d: Likewise. * gas/i386/nops-3-i386.d: Likewise. * gas/i386/nops-3.d : Likewise. * gas/i386/sib.d: Likewise. * gas/i386/sib.s: Use %eiz in testcases. * gas/i386/sib-intel.d: New. * gas/i386/x86-64-sib-intel.d: Likewise. * gas/i386/x86-64-sib.d: Likewise. * gas/i386/x86-64-sib.s: Likewise. ld/testsuite/ 2007-09-20 H.J. Lu <hongjiu.lu@intel.com> PR 658 * ld-i386/tlsbin.dd: Updated. * ld-i386/tlsld1.dd: Likewise. opcodes/ 2007-09-20 H.J. Lu <hongjiu.lu@intel.com> PR 658 * 386-dis.c (index64): New. (index32): Likewise. (intel_index64): Likewise. (intel_index32): Likewise. (att_index64): Likewise. (att_index32): Likewise. (print_insn): Set index64 and index32. (OP_E_extended): Use index64/index32 for index register for SIB with INDEX == 4. * i386-opc.h (RegEiz): New. (RegRiz): Likewise. * i386-reg.tbl: Add eiz and riz. * i386-tbl.h: Regenerated.	2007-09-20 17:38:38 +00:00
H.J. Lu	0f7da3979d	gas/testsuite/gas/ 2007-09-19 H.J. Lu <hongjiu.lu@intel.com> * gas/i386/intelok.s: Add tests for memory without base. * gas/i386/intelok.d: Updated. * gas/i386/intelok.e: Likewise. opcodes/ 2007-09-19 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (OP_E_extended): Always display scale for memory.	2007-09-19 17:52:21 +00:00
H.J. Lu	20e192ab8d	gas/ 2007-09-17 H.J. Lu <hongjiu.lu@intel.com> * config/tc-i386.c (baseindex): Removed. (build_modrm_byte): Check reg_num for RIP register instead of reg_type. (i386_index_check): Likewise. opcodes/ 2007-09-17 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h (RegRip): New. * i386-reg.tbl (rip): Use RegRip for reg_num. * i386-tbl.h: Regenerated.	2007-09-18 00:56:54 +00:00
Nick Clifton	7f396d02ee	Updated Spanish translation	2007-09-17 14:06:03 +00:00
H.J. Lu	c0e9c2a631	2007-09-14 H.J. Lu <hongjiu.lu@intel.com> * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate.	2007-09-14 19:28:56 +00:00
Michael Meissner	85f10a010c	Add AMD SSE5 support	2007-09-14 18:21:09 +00:00
H.J. Lu	8bb1533941	2007-09-13 H.J. Lu <hongjiu.lu@intel.com> * i386-dis.c (get_valid_dis386): Take a pointer to disassemble_info. Handle IS_3BYTE_OPCODE. (print_insn): Updated. Don't handle IS_3BYTE_OPCODE here.	2007-09-14 00:20:03 +00:00
H.J. Lu	8c6c980951	2007-09-12 H.J. Lu <hongjiu.lu@intel.com> * i386-opc.h (CpuUnused): Defined with CpuMax. (OTUnused): Defined with OTMax.	2007-09-12 18:55:31 +00:00
Jan Beulich	ae91ad40e9	gas/testsuite/ 2007-09-12 Jan Beulich <jbeulich@novell.com> * gas/i386/sse4_1.s, gas/i386/x86-64-sse4_1.s: Add two-operand forms of blendvps, blendvpd, and pblendvb. * gas/i386/sse4_1.d, gas/i386/sse4_1-intel.d, gas/i386/x86-64-sse4_1.d, gas/i386/x86-64-sse4_1-intel.d: Adjust, making last/first operand of blendvps, blendvpd, and pblendvb optional. opcodes/ 2007-09-12 Jan Beulich <jbeulich@novell.com> * i386-opc.tbl: Add two-operand forms of blendvps, blendvpd, and pblendvb. * i386-tbl.h: Regenerate.	2007-09-12 13:20:31 +00:00
H.J. Lu	8b40d5948e	2007-09-09 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (main): Remove the local variable, unused.	2007-09-09 16:02:17 +00:00
H.J. Lu	331699936d	2007-09-08 H.J. Lu <hongjiu.lu@intel.com> * Makefile.am: Run "make dep-am". * Makefile.in: Regenerate.	2007-09-09 01:34:48 +00:00
H.J. Lu	40fb982012	gas/ 2007-09-08 H.J. Lu <hongjiu.lu@intel.com> * configure.in (AC_CHECK_HEADERS): Add limits.h. * configure: Regenerated. * config.in: Likewise. * config/tc-i386.c: Include "opcodes/i386-init.h". (_i386_insn): Use i386_operand_type for types. (cpu_arch_flags): Updated to new types with bitfield. (cpu_arch_tune_flags): Likewise. (cpu_arch_isa_flags): Likewise. (cpu_arch): Likewise. (i386_align_code): Likewise. (set_code_flag): Likewise. (set_16bit_gcc_code_flag): Likewise. (set_cpu_arch): Likewise. (md_assemble): Likewise. (parse_insn): Likewise. (process_operands): Likewise. (output_branch): Likewise. (output_jump): Likewise. (parse_real_register): Likewise. (mode_from_disp_size): Likewise. (smallest_imm_type): Likewise. (pi): Likewise. (type_names): Likewise. (pt): Likewise. (pte): Likewise. (swap_2_operands): Likewise. (optimize_imm): Likewise. (optimize_disp): Likewise. (match_template): Likewise. (check_string): Likewise. (process_suffix): Likewise. (check_byte_reg): Likewise. (check_long_reg): Likewise. (check_qword_reg): Likewise. (check_word_reg): Likewise. (finalize_imm): Likewise. (build_modrm_byte): Likewise. (output_insn): Likewise. (disp_size): Likewise. (imm_size): Likewise. (output_disp): Likewise. (output_imm): Likewise. (gotrel): Likewise. (i386_immediate): Likewise. (i386_displacement): Likewise. (i386_index_check): Likewise. (i386_operand): Likewise. (parse_real_register): Likewise. (i386_intel_operand): Likewise. (intel_e09): Likewise. (intel_bracket_expr): Likewise. (intel_e11): Likewise. (cpu_arch_flags_not): New. (cpu_flags_check_x64): Likewise. (cpu_flags_all_zero): Likewise. (cpu_flags_not): Likewise. (i386_cpu_flags_biop): Likewise. (cpu_flags_biop): Likewise. (cpu_flags_match); Likewise. (acc32): New. (acc64): Likewise. (control): Likewise. (reg16_inoutportreg): Likewise. (disp16): Likewise. (disp32): Likewise. (disp32s): Likewise. (disp16_32): Likewise. (anydisp): Likewise. (baseindex): Likewise. (regxmm): Likewise. (imm8): Likewise. (imm8s): Likewise. (imm16): Likewise. (imm32): Likewise. (imm32s): Likewise. (imm64): Likewise. (imm16_32): Likewise. (imm16_32s): Likewise. (imm16_32_32s): Likewise. (operand_type): Likewise. (operand_type_check): Likewise. (operand_type_match): Likewise. (operand_type_register_match): Likewise. (update_imm): Likewise. (set_code_flag): Also update cpu_arch_flags_not. (set_16bit_gcc_code_flag): Likewise. (md_begin): Likewise. (parse_insn): Use cpu_flags_check_x64 to check 64bit support. Use cpu_flags_match to match instructions. (i386_target_format): Update cpu_arch_isa_flags and cpu_arch_tune_flags to i386_cpu_flags type with bitfield. (smallest_imm_type): Check cpu_arch_tune to tune for i486. (match_template): Don't initialize overlap0, overlap1, overlap2, overlap3 and operand_types. (process_suffix): Handle crc32 with 64bit register. (MATCH): Removed. (CONSISTENT_REGISTER_MATCH): Likewise. * config/tc-i386.h (arch_entry): Updated to i386_cpu_flags type. opcodes/ 2007-09-08 H.J. Lu <hongjiu.lu@intel.com> * configure.in (AC_CHECK_HEADERS): Add limits.h. * configure: Regenerated. * config.in: Likewise. * i386-gen.c: Include "sysdep.h" instead of <stdlib.h> and <string.h>. Use xstrerror instead of strerror. (initializer): New. (cpu_flag_init): Likewise. (bitfield): Likewise. (BITFIELD): New. (cpu_flags): Likewise. (opcode_modifiers): Likewise. (operand_types): Likewise. (compare): Likewise. (set_cpu_flags): Likewise. (output_cpu_flags): Likewise. (process_i386_cpu_flags): Likewise. (output_opcode_modifier): Likewise. (process_i386_opcode_modifier): Likewise. (output_operand_type): Likewise. (process_i386_operand_type): Likewise. (set_bitfield): Likewise. (operand_type_init): Likewise. (process_i386_initializers): Likewise. (process_i386_opcodes): Call process_i386_opcode_modifier to process opcode_modifier. Call process_i386_operand_type to process operand_types. (process_i386_registers): Call process_i386_operand_type to process reg_type. (main): Check unused bits in i386_cpu_flags and i386_operand_type. Sort cpu_flags, opcode_modifiers and operand_types. Call process_i386_initializers. * i386-init.h: New. * i386-tbl.h: Regenerated. * i386-opc.h: Include <limits.h>. (CHAR_BIT): Define as 8 if not defined. (Cpu186): Changed to position of bitfiled. (Cpu286): Likewise. (Cpu386): Likewise. (Cpu486): Likewise. (Cpu586): Likewise. (Cpu686): Likewise. (CpuP4): Likewise. (CpuK6): Likewise. (CpuK8): Likewise. (CpuMMX): Likewise. (CpuMMX2): Likewise. (CpuSSE): Likewise. (CpuSSE2): Likewise. (Cpu3dnow): Likewise. (Cpu3dnowA): Likewise. (CpuSSE3): Likewise. (CpuPadLock): Likewise. (CpuSVME): Likewise. (CpuVMX): Likewise. (CpuSSSE3): Likewise. (CpuSSE4a): Likewise. (CpuABM): Likewise. (CpuSSE4_1): Likewise. (CpuSSE4_2): Likewise. (Cpu64): Likewise. (CpuNo64): Likewise. (D): Likewise. (W): Likewise. (Modrm): Likewise. (ShortForm): Likewise. (Jump): Likewise. (JumpDword): Likewise. (JumpByte): Likewise. (JumpInterSegment): Likewise. (FloatMF): Likewise. (FloatR): Likewise. (FloatD): Likewise. (Size16): Likewise. (Size32): Likewise. (Size64): Likewise. (IgnoreSize): Likewise. (DefaultSize): Likewise. (No_bSuf): Likewise. (No_wSuf): Likewise. (No_lSuf): Likewise. (No_sSuf): Likewise. (No_qSuf): Likewise. (No_xSuf): Likewise. (FWait): Likewise. (IsString): Likewise. (RegKludge): Likewise. (IsPrefix): Likewise. (ImmExt): Likewise. (NoRex64): Likewise. (Rex64): Likewise. (Ugh): Likewise. (Reg8): Likewise. (Reg16): Likewise. (Reg32): Likewise. (Reg64): Likewise. (FloatReg): Likewise. (RegMMX): Likewise. (RegXMM): Likewise. (Imm8): Likewise. (Imm8S): Likewise. (Imm16): Likewise. (Imm32): Likewise. (Imm32S): Likewise. (Imm64): Likewise. (Imm1): Likewise. (BaseIndex): Likewise. (Disp8): Likewise. (Disp16): Likewise. (Disp32): Likewise. (Disp32S): Likewise. (Disp64): Likewise. (InOutPortReg): Likewise. (ShiftCount): Likewise. (Control): Likewise. (Debug): Likewise. (Test): Likewise. (SReg2): Likewise. (SReg3): Likewise. (Acc): Likewise. (FloatAcc): Likewise. (JumpAbsolute): Likewise. (EsSeg): Likewise. (RegMem): Likewise. (OTMax): Likewise. (Reg): Commented out. (WordReg): Likewise. (ImplicitRegister): Likewise. (Imm): Likewise. (EncImm): Likewise. (Disp): Likewise. (AnyMem): Likewise. (LLongMem): Likewise. (LongMem): Likewise. (ShortMem): Likewise. (WordMem): Likewise. (ByteMem): Likewise. (CpuMax): New (CpuLM): Likewise. (CpuNumOfUints): Likewise. (CpuNumOfBits): Likewise. (CpuUnused): Likewise. (OTNumOfUints): Likewise. (OTNumOfBits): Likewise. (OTUnused): Likewise. (i386_cpu_flags): New type. (i386_operand_type): Likewise. (i386_opcode_modifier): Likewise. (CpuSledgehammer): Removed. (CpuSSE4): Likewise. (CpuUnknownFlags): Likewise. (Reg): Likewise. (WordReg): Likewise. (ImplicitRegister): Likewise. (Imm): Likewise. (EncImm): Likewise. (Disp): Likewise. (AnyMem): Likewise. (LLongMem): Likewise. (LongMem): Likewise. (ShortMem): Likewise. (WordMem): Likewise. (ByteMem): Likewise. (template): Use i386_cpu_flags for cpu_flags, use i386_opcode_modifier for opcode_modifier, use i386_operand_type for operand_types. (reg_entry): Use i386_operand_type for reg_type. * Makefile.am (HFILES): Add i386-init.h. ($(srcdir)/i386-init.h): New rule. ($(srcdir)/i386-tbl.h): Depend on $(srcdir)/i386-init.h instead. * Makefile.in: Regenerated.	2007-09-09 01:22:57 +00:00
H.J. Lu	93b1ec2cbf	2007-09-06 H.J. Lu <hongjiu.lu@intel.com> * i386-gen.c (next_field): Updated to take a separator. (process_i386_opcodes): Updated. (process_i386_registers): Likewise.	2007-09-06 22:55:04 +00:00

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2347 Commits