MatCat.OpenSource/8sa1-binutils-gdb
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5 Commits

Author SHA1 Message Date
Andrew Waterman
858f82bf7e RISC-V: Add physical memory protection CSRs 
2017-03-27  Andrew Waterman  <andrew@sifive.com>

       * opcode/riscv-opc.h (CSR_PMPCFG0): New define.
       (CSR_PMPCFG1): Likewise.
       (CSR_PMPCFG2): Likewise.
       (CSR_PMPCFG3): Likewise.
       (CSR_PMPADDR0): Likewise.
       (CSR_PMPADDR1): Likewise.
       (CSR_PMPADDR2): Likewise.
       (CSR_PMPADDR3): Likewise.
       (CSR_PMPADDR4): Likewise.
       (CSR_PMPADDR5): Likewise.
       (CSR_PMPADDR6): Likewise.
       (CSR_PMPADDR7): Likewise.
       (CSR_PMPADDR8): Likewise.
       (CSR_PMPADDR9): Likewise.
       (CSR_PMPADDR10): Likewise.
       (CSR_PMPADDR11): Likewise.
       (CSR_PMPADDR12): Likewise.
       (CSR_PMPADDR13): Likewise.
       (CSR_PMPADDR14): Likewise.
       (CSR_PMPADDR15): Likewise.
       (pmpcfg0): Declare register.
       (pmpcfg1): Likewise.
       (pmpcfg2): Likewise.
       (pmpcfg3): Likewise.
       (pmpaddr0): Likewise.
       (pmpaddr1): Likewise.
       (pmpaddr2): Likewise.
       (pmpaddr3): Likewise.
       (pmpaddr4): Likewise.
       (pmpaddr5): Likewise.
       (pmpaddr6): Likewise.
       (pmpaddr7): Likewise.
       (pmpaddr8): Likewise.
       (pmpaddr9): Likewise.
       (pmpaddr10): Likewise.
       (pmpaddr11): Likewise.
       (pmpaddr12): Likewise.
       (pmpaddr13): Likewise.
       (pmpaddr14): Likewise.
       (pmpaddr15): Likewise.
 2017-03-31 09:35:11 -07:00
Andrew Waterman
742d14b39b Add new counter-enable CSRs 
include/ChangeLog:

2017-02-22  Andrew Waterman  <andrew@sifive.com>

       * opcode/riscv-opc.h (CSR_SCOUNTEREN): New define.
       (CSR_MCOUNTEREN): Likewise.
       (scounteren): Declare register.
       (mcounteren): Likewise.
 2017-02-24 09:24:58 -08:00
Andrew Waterman
f98d33be3a Add SFENCE.VMA instruction 
include/ChangeLog:

2017-02-14  Andrew Waterman  <andrew@sifive.com>

        * opcode/riscv-opc.h (MATCH_SFENCE_VMA): New define.
        (MASK_SFENCE_VMA): Likewise.
        (sfence_vma): Declare instruction.

opcodes/ChangeLog:

2017-02-14  Andrew Waterman  <andrew@sifive.com>

        * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
        pseudoinstructions.
 2017-02-15 10:35:00 -08:00
Kito Cheng
cc917fd93d Add support for the Q extension to the RISCV ISA. 
gas    * config/tc-riscv.c (riscv_set_arch): Whitelist the "q" ISA
        extension.
        (riscv_after_parse_args): Set FLOAT_ABI_QUAD when the Q ISA is
        enabled and no other ABI is specified.

include * opcode/riscv-opc.h: Add support for the "q" ISA extension.

opcodes * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
        extension.
        * riscv-opcodes/all-opcodes: Likewise.
 2017-01-03 17:42:01 +00:00
Nick Clifton
e23eba971d Add support for RISC-V architecture. 
bfd	* Makefile.am: Add entries for riscv32-elf and riscv64-elf.
	* config.bdf: Likewise.
	* configure.ac: Likewise.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* archures.c: Add bfd_riscv_arch.
	* reloc.c: Add riscv relocs.
	* targets.c: Add riscv_elf32_vec and riscv_elf64_vec.
	* bfd-in2.h: Regenerate.
	* libbfd.h: Regenerate.
	* elf-bfd.h: Add RISCV_ELF_DATA to enum elf_target_id.
	* elfnn-riscv.c: New file.
	* elfxx-riscv.c: New file.
	* elfxx-riscv.h: New file.

binutils* readelf.c (guess_is_rela): Add EM_RISCV.
	(get_machine_name): Likewise.
	(dump_relocations): Add support for riscv relocations.
	(get_machine_flags): Add support for riscv flags.
	(is_32bit_abs_reloc): Add R_RISCV_32.
	(is_64bit_abs_reloc): Add R_RISCV_64.
	(is_none_reloc): Add R_RISCV_NONE.
	* testsuite/binutils-all/objdump.exp (cpus_expected): Add riscv.
	Expect the debug_ranges test to fail.

gas	* Makefile.am: Add riscv files.
	* Makefile.in: Regenerate.
	* NEWS: Mention the support for this architecture.
	* configure.in: Define a default architecture.
	* configure: Regenerate.
	* configure.tgt: Add entries for riscv.
	* doc/as.texinfo: Likewise.
	* testsuite/gas/all/gas.exp: Expect the redef tests to fail.
	* testsuite/gas/elf/elf.exp: Expect the groupauto tests to fail.
	* config/tc-riscv.c: New file.
	* config/tc-riscv.h: New file.
	* doc/c-riscv.texi: New file.
	* testsuite/gas/riscv: New directory.
	* testsuite/gas/riscv/riscv.exp: New file.
	* testsuite/gas/riscv/t_insns.d: New file.
	* testsuite/gas/riscv/t_insns.s: New file.

ld	* Makefile.am: Add riscv files.
	* Makefile.in: Regenerate.
	* NEWS: Mention the support for this target.
	* configure.tgt: Add riscv entries.
	* emulparams/elf32lriscv-defs.sh: New file.
	* emulparams/elf32lriscv.sh: New file.
	* emulparams/elf64lriscv-defs.sh: New file.
	* emulparams/elf64lriscv.sh: New file.
	* emultempl/riscvelf.em: New file.

opcodes	* configure.ac: Add entry for bfd_riscv_arch.
	* configure: Regenerate.
	* disassemble.c (disassembler): Add support for riscv.
	(disassembler_usage): Likewise.
	* riscv-dis.c: New file.
	* riscv-opc.c: New file.

include	* dis-asm.h: Add prototypes for print_insn_riscv and
	print_riscv_disassembler_options.
	* elf/riscv.h: New file.
	* opcode/riscv-opc.h: New file.
	* opcode/riscv.h: New file.
 2016-11-01 16:45:57 +00:00