MatCat.OpenSource/8sa1-binutils-gdb
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446 Commits

Author SHA1 Message Date
Jeff Law
731c7b4bb8 * mn10300-opc.c (mn10300_opcodes): Remove redundant "lcc" 
opcode.
 1996-11-25 19:46:21 +00:00
Jeff Law
76783aa31c * mn10300-dis.c (disassemble): Use '$' instead of '%' for 
register prefix.
It's easier for the assembler...
 1996-11-25 18:46:06 +00:00
Jeff Law
11cd057a41 * mn10300-dis.c (disassemble): Prefix registers with '%'. 1996-11-25 18:21:08 +00:00
Jeff Law
f0e98103c5 * mn10300-dis.c (disassemble): Handle register lists. 
More disassembler stuff.
 1996-11-20 18:39:48 +00:00
Jeff Law
f039819018 * mn10300-opc.c: Fix handling of register list operand for 
"call", "ret", and "rets" instructions.
Stuff noticed while working on disasembler.
 1996-11-20 18:32:44 +00:00
Jeff Law
aa9c04cd55 * mn10300-dis.c (disassemble): Print PC-relative and memory 
addresses symbolically if possible.
        * mn10300-opc.c: Distinguish between absolute memory addresses,
        pc-relative offsets & random immediates.
More disassembler work.
 1996-11-20 18:02:31 +00:00
Jeff Law
f497f3ae7c * mn10300-dis.c (print_insn_mn10300): Fix fetch of last byte 
in 7 byte insns.
        (disassemble): Handle SPLIT and EXTENDED operands.
 1996-11-20 17:36:31 +00:00
Jeff Law
d91028d2c7 * mn10300-dis.c: Rough cut at printing some operands. 1996-11-20 00:55:22 +00:00
Jeff Law
4aa92185f8 * mn10300-dis.c: Start working on disassembler support. 
* mn10300-opc.c (mn10300_opcodes): Fix masks on several insns.
Selects opcodes & consumes bytes.  Breaks badly if given data instead of
code.  No operands yet.
 1996-11-19 23:59:27 +00:00
Jeff Law
99246e03f9 * mn10300-opc.c (mn10300_operands): Add "REGS" for a register 
list.
        (mn10300_opcodes): Use REGS for register list in "movm" instructions.
 1996-11-19 20:32:31 +00:00
Michael Meissner
b337f8691f Add3 sets the carry 1996-11-18 20:21:55 +00:00
Jeff Law
54dfaf0a65 * mn10300-opc.c (mn10300_opcodes): Demand parens around 
register argument is calls and jmp instructions.
Found trying to build libgcc2 for the mn10300 :-)
 1996-11-15 20:43:44 +00:00
Jeff Law
f2ab9a7505 * mn10300-opc.c (mn10300_opcodes): Use DN01 for putx and 
getx operand.  Fix opcode for mulqu imm,dn.
Fix bugs exposed by gas testsuite (extended instructions).
 1996-11-07 07:26:25 +00:00
Jeff Law
26433754cc * mn10300-opc.c (mn10300_operands): Hijack "bits" field 
in MN10300_OPERAND_SPLIT operands for how many bits
        appear in the basic insn word.  Add IMM32_HIGH24,
        IMM32_HIGH24_LOWSHIFT8, IMM8E_SHIFT8.
        (mn10300_opcodes): Use new operands as needed.
Support for everything in the basic instruction manual (yippie!)
 1996-11-06 21:58:21 +00:00
Jeff Law
64ce06688d * mn10300-opc.c (mn10300_operands): Add IMM32_LOWSHIFT8 
for bset, bclr, btst instructions.
        (mn10300_opcodes): Use new IMM32_LOWSHIFT8 as needed.
For btst, bclr & bset.
 1996-11-06 21:18:27 +00:00
Jeff Law
fdef41f30b * mn10300-opc.c (mn10300_operands): Remove many redundant 
operands.  Update opcode table as appropriate.
        (IMM32): Add MN10300_OPERAND_SPLIT flag.
        (mn10300_opcodes): Fix single bit error in mov imm32,dn insn.
Cleaning up a little.
Attempting to insert most 32bit operands.
And a bug found by assembler testsuite.
 1996-11-06 20:44:58 +00:00
Jeff Law
bb5e141ab4 * mn10300-opc.c (mn10300_operands): Add DN2, DM2, AN2, AM2 
operands (for indexed load/stores).  Fix bitpos for DI
        operand.  Add SN8N_SHIFT8, IMM8_SHIFT8, and D16_SHIFT for the
        few instructions that insert immediates/displacements in the
        middle of the instruction.  Add IMM8E for 8 bit immediate in
        the extended part of an instruction.
        (mn10300_operands): Use new opcodes as appropriate.
Opcode table changes so we can correctly insert everything except
32bit operands.
 1996-11-05 20:29:31 +00:00
Martin Hunt
733861650a Tue Nov 5 10:30:51 1996 Martin M. Hunt <hunt@pizza.cygnus.com> 
* d10v-opc.c (d10v_opcodes): Declare the trap instruction
 	sequential so the assembler never parallelizes it with
	other instructions.
 1996-11-05 18:34:19 +00:00
Jeff Law
e85c140a27 * mn10300-opc.c (mn10300_operands): Add DN01 and AN01 for 
a data/address register that appears in register field 0
        and register field 1.
        (mn10300_opcodes): Use DN01 and AN01 for mov/cmp imm8,DN/AN

Hacking Matsushita again.  Yippie!
 1996-11-04 19:51:31 +00:00
Ian Lance Taylor
03e9562378 Fri Nov 1 10:29:11 1996 Richard Henderson <rth@tamu.edu> 
* alpha-dis.c (print_insn_alpha): Use new NOPAL mask for
	standard disassembly.

	* alpha-opc.c (alpha_operands): Rearrange flags slot.
	(alpha_opcodes): Add new BWX, CIX, and MAX instructions.
	Recategorize PALcode instructions.
 1996-11-01 18:30:43 +00:00
Jeff Law
7d2759fc5b * v850-opc.c (v850_opcodes): Add relaxing "jbr". 1996-10-30 23:52:31 +00:00
Ian Lance Taylor
b56c3d6cee * mips-dis.c (_print_insn_mips): Don't print a trailing tab if 
there are no operand types.
 1996-10-29 21:31:22 +00:00
Jeff Law
244558e354 * v850-opc.c (D9_RELAX): Renamed from D9, all references 
changed.
        (v850_operands): Make sure D22 immediately follows D9_RELAX.
 1996-10-29 19:25:35 +00:00
Jeff Law
0f02ae6e5a * v850-opc.c (v850_opcodes): Add "jCC" instructions (aliases for 
"bCC"instructions).
Because quantum's code uses jnz, jcc, etc etc etc.
 1996-10-24 23:55:11 +00:00
Ian Lance Taylor
4f6d7c2c30 * mips-dis.c (_print_insn_mips): Use a tab between the instruction 
and the arguments.
 1996-10-24 21:21:37 +00:00
Ian Lance Taylor
de145351e8 * ppc-opc.c (PPCPWR2): Define. 
(powerpc_opcodes): Use PPCPWR2 for fsqrt, rather than duplicating
	it.
 1996-10-23 03:34:07 +00:00
Jeff Law
63dc694d29 * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode 
field for movhu instruction.
Bug found by gas testsuite.

        * v850-dis.c (disassemble): For V850_OPERAND_SIGNED operands,
        cast value to "long" not "signed long" to keep hpux10
        compiler quiet.
Found in an attempt to build the v850 on hpux10 with the HP
compiler.
 1996-10-11 22:06:47 +00:00
Jeff Law
02d4ad193b * mn10300-opc.c (mn10300_opcodes): Fix typo in opcode field 
for mov (abs16),DN.
Bug found by gas testsuite.  Matsushita.
 1996-10-10 21:42:01 +00:00
Jeff Law
ba8ed10c7e * mn10300-opc.c (FMT*): Remove definitions. 
Moved into opcode/mn10300.h
 1996-10-10 20:31:06 +00:00
Jeff Law
1e5ddd3be4 * mn10300-opc.c (mn10300_opcodes): Fix destination register 
for shift-by-register opcodes.
Bug found by testsuite.
 1996-10-10 19:08:46 +00:00
Jeff Law
36b34aa4a9 * mn10300-opc.c (mn10300_operands): Break DN, DM, AN, AM 
into [AD][MN][01] for encoding the position of the register
        in the opcode.
Matsushita.
 1996-10-10 16:28:14 +00:00
Jeff Law
344d6417bb * mn10300-opc.c (mn10300_opcodes): Add "extended" instructions, 
"putx", "getx", "mulq", "mulqu", "sat16", "sat24", "bsch".
Matsushita.
 1996-10-09 17:20:59 +00:00
Jeff Law
db22905430 * mn10300-opc.c (mn10300_operands): Remove "REGS" operand. 
Fix various typos.  Add "PAREN" operand.
        (MEM, MEM2): Define.
        (mn10300_opcodes): Surround all memory addresses with "PAREN"
        operands.  Fix several typos.
Should parse all opcodes in the instruction specification, except the
"user extension instructions".
 1996-10-08 21:09:57 +00:00
Jeff Law
06b796584d * mn10300-opc.c (mn10300_opcodes): Fix typos in yesterday's 
changes.
Matsushita.
 1996-10-08 17:56:40 +00:00
Jeff Law
5ab7bce62d * mn10300-opc.c (FMT_XX): Renumber starting at one. 
(mn10300_operands): Rough cut.  Enough to parse "mov" instructions
        at this time.
        (mn10300_opcodes): Break opcode format out into its own field.
        Update many operand fields to deal with signed vs unsigned
        issues.  Fix one or two typos in the "mov" instruction
        opcode, mask and/or operand fields.
Checkpointing today's work.  Matsushita.
 1996-10-07 22:52:18 +00:00
Ian Lance Taylor
6ba7ecd4eb Mon Oct 7 11:39:49 1996 Andreas Schwab <schwab@issan.informatik.uni-dortmund.de> 
* m68k-opc.c (plusha): Prefer encoding for m68040up, in case
	m68851 wasn't reset.
 1996-10-07 15:41:56 +00:00
Jeff Law
99777c0bfb * mn10300-opc.c (mn10300_opcodes): Add opcode & masks for 
all opcodes.  Very rough cut at operands for all opcodes.
Matsushita.
 1996-10-04 22:02:43 +00:00
Jeff Law
cd8a9026b9 * mn10300-opc.c (mn10300_opcodes): Start fleshing out the 
opcode table.
Checkpointint 10300 work.
 1996-10-04 19:20:19 +00:00
Ian Lance Taylor
6c9370db2a * Makefile.in (ALL_MACHINES): Add mn10200-dis.o, mn10200-opc.o, 
mn10300-dis.o, and mn10300-opc.o.
Also add d10v and v850 files, with appropriate sanitization.
 1996-10-03 21:17:46 +00:00
Jeff Law
ae1b99e42d Grrr. The mn10200 and mn10300 are _not_ similar enough to easily support 
with a single generic configuration.  So break them up into two different
configurations.  See the individual ChangeLogs for additional detail.
 1996-10-03 16:42:22 +00:00
Jason Molenda
42b4add910 * Makefile.in (MOSTLYCLEAN): Move config.log to distclean. 1996-10-03 06:58:15 +00:00
Jeff Law
e7c50ceffd * mn10x00-opc.c, mn10x00-dis.c: New files for Matsushita 
MN10x00 processors.
        * disassemble (ARCH_mn10x00): Define.
        (disassembler): Handle bfd_arch_mn10x00.
        * configure.in: Recognize bfd_mn10x00_arch.
        * configure: Rebuilt.
Continue stubbing out for Matsushita work.
 1996-10-03 05:31:01 +00:00
Jeff Law
072b27ea5e Add missing copyright. 1996-10-03 04:48:16 +00:00
Ian Lance Taylor
a5cb84dd6f * i386-dis.c (op_rtn): Change to be a pointer. Adjust uses 
accordingly.  Don't declare functions using op_rtn.
Remove ANSI C constructs.
 1996-10-01 14:50:19 +00:00
Ian Lance Taylor
800bda836e * mips-opc.c: Add a case for "div" and "divu" with two registers 
and a destination of $0.
PR 10654.
 1996-09-17 16:07:41 +00:00
Fred Fish
d7deed257c * mips-dis.c (print_insn_arg): Add prototype. 
(_print_insn_mips): Ditto.
 1996-09-11 04:26:58 +00:00
Ian Lance Taylor
30b1724cc8 * mips-dis.c (print_insn_arg): Print condition code registers as 
$fccN.
 1996-09-09 18:27:10 +00:00
Jeff Law
eb5c28e173 * v850-dis.c (disassemble): Make static. Provide prototype. 1996-09-03 18:05:25 +00:00
Ian Lance Taylor
44789bee66 whoops--typo 1996-09-02 16:41:29 +00:00
Ian Lance Taylor
01d34e4be3 file was really removed a long time ago 1996-09-02 16:41:28 +00:00