MatCat.OpenSource/8sa1-binutils-gdb
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

[PATCH, BINUTILS, AARCH64, 7/9] Add BTI instruction

Browse Source 
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order/bti-branch-target-identification)

The Branch Target Identification instructions (BTI) are allocated to
existing HINT space, using HINT numbers 32, 34, 36, 38, such that
bits[7:6] of the instruction identify the compatibility of the BTI
instruction to different branches.

	BTI {<targets>}

where <targets> one of the following, specifying which type of
indirection is allowed:

	j : Can be a target of any BR Xn isntruction.
	c : Can be a target of any BLR Xn and BR {X16|X17}.
	jc: Can be a target of any free branch.

A BTI instruction without any <targets> is the strictest of all and
can not be a target of nay free branch.

*** include/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* opcode/aarch64.h (AARCH64_FEATURE_BTI): New.
	(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default.
	(aarch64_opnd): Add AARCH64_OPND_BTI_TARGET.
	(HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to
	define HINT #imm values.
	(HINT_OPD_JC, HINT_OPD_NULL): Likewise.

*** opcodes/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
	(HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
	with the hint immediate.
	* aarch64-opc.c (aarch64_hint_options): New entries for
	c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
	(aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
	while checking for HINT_OPD_F_NOPRINT flag.
	* aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
	extract value.
	* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
	(aarch64_opcode_table): Add entry for BTI.
	(AARCH64_OPERANDS): Add new description for BTI targets.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

*** gas/ChangeLog ***

2018-10-09  Sudakshina Das  <sudi.das@arm.com>

	* config/tc-aarch64.c (parse_bti_operand): New.
	(process_omitted_operand): Add case for AARCH64_OPND_BTI_TARGET.
	(parse_operands): Likewise.
	* testsuite/gas/aarch64/system.d: Update for BTI.
	* testsuite/gas/aarch64/bti.s: New.
	* testsuite/gas/aarch64/bti.d: New.
	* testsuite/gas/aarch64/illegal-bti.d: New.
	* testsuite/gas/aarch64/illegal-bti.l: New.
This commit is contained in:
Sudakshina Das 2018-09-26 11:00:49 +01:00 committed by Richard Earnshaw
parent af4bcb4ce6
commit ff6054520c
17 changed files with 1413 additions and 1256 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
gas/ChangeLog
View File

@ -1,3 +1,14 @@
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_bti_operand): New.
(process_omitted_operand): Add case for AARCH64_OPND_BTI_TARGET.
(parse_operands): Likewise.
* testsuite/gas/aarch64/system.d: Update for BTI.
* testsuite/gas/aarch64/bti.s: New.
* testsuite/gas/aarch64/bti.d: New.
* testsuite/gas/aarch64/illegal-bti.d: New.
* testsuite/gas/aarch64/illegal-bti.l: New.
2018-10-09 Sudakshina Das <sudi.das@arm.com> 2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_features): New "rng" option. * config/tc-aarch64.c (aarch64_features): New "rng" option.

52
gas/config/tc-aarch64.c
View File

@ -3933,6 +3933,47 @@ parse_barrier_psb (char **str,
return 0; return 0;
} }
/* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
return 0 if successful. Otherwise return PARSE_FAIL. */
static int
parse_bti_operand (char **str,
const struct aarch64_name_value_pair ** hint_opt)
{
char *p, *q;
const struct aarch64_name_value_pair *o;
p = q = *str;
while (ISALPHA (*q))
q++;
o = hash_find_n (aarch64_hint_opt_hsh, p, q - p);
if (!o)
{
set_fatal_syntax_error
( _("unknown option to BTI"));
return PARSE_FAIL;
}
switch (o->value)
{
/* Valid BTI operands. */
case HINT_OPD_C:
case HINT_OPD_J:
case HINT_OPD_JC:
break;
default:
set_syntax_error
(_("unknown option to BTI"));
return PARSE_FAIL;
}
*str = q;
*hint_opt = o;
return 0;
}
/* Parse a system register or a PSTATE field name for an MSR/MRS instruction. /* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
Returns the encoding for the option, or PARSE_FAIL. Returns the encoding for the option, or PARSE_FAIL.
@ -5151,6 +5192,11 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode,
case AARCH64_OPND_BARRIER_ISB: case AARCH64_OPND_BARRIER_ISB:
operand->barrier = aarch64_barrier_options + default_value; operand->barrier = aarch64_barrier_options + default_value;
break;
case AARCH64_OPND_BTI_TARGET:
operand->hint_option = aarch64_hint_options + default_value;
break;
default: default:
break; break;
@ -6483,6 +6529,12 @@ sys_reg_ins:
goto failure; goto failure;
break; break;
case AARCH64_OPND_BTI_TARGET:
val = parse_bti_operand (&str, &(info->hint_option));
if (val == PARSE_FAIL)
goto failure;
break;
default: default:
as_fatal (_("unhandled operand code %d"), operands[i]); as_fatal (_("unhandled operand code %d"), operands[i]);
} }

12
gas/testsuite/gas/aarch64/bti.d Normal file
View File

@ -0,0 +1,12 @@
#as: -march=armv8.5-a
#objdump: -dr
.*: file format .*
Disassembly of section \.text:
0+ <.*>:
.*: d503241f bti
.*: d503245f bti c
.*: d503249f bti j
.*: d50324df bti jc

8
gas/testsuite/gas/aarch64/bti.s Normal file
View File

@ -0,0 +1,8 @@
// Test file for AArch64 bti.
.text
bti
bti c
bti j
bti jc

3
gas/testsuite/gas/aarch64/illegal-bti.d Normal file
View File

@ -0,0 +1,3 @@
#as: -march=armv8-a
#source: bti.s
#error_output: illegal-bti.l

5
gas/testsuite/gas/aarch64/illegal-bti.l Normal file
View File

@ -0,0 +1,5 @@
[^:]*: Assembler messages:
[^:]*:[0-9]+: Error: selected processor does not support `bti'
[^:]*:[0-9]+: Error: selected processor does not support `bti c'
[^:]*:[0-9]+: Error: selected processor does not support `bti j'
[^:]*:[0-9]+: Error: selected processor does not support `bti jc'

8
gas/testsuite/gas/aarch64/system.d
View File

@ -44,13 +44,13 @@ Disassembly of section \.text:
.*: d50323bf (hint #0x1d|autiasp) .*: d50323bf (hint #0x1d|autiasp)
.*: d50323df (hint #0x1e|autibz) .*: d50323df (hint #0x1e|autibz)
.*: d50323ff (hint #0x1f|autibsp) .*: d50323ff (hint #0x1f|autibsp)
.*: d503241f hint #0x20 .*: d503241f (hint #0x20|bti)
.*: d503243f hint #0x21 .*: d503243f hint #0x21
.*: d503245f hint #0x22 .*: d503245f (hint #0x22|bti c)
.*: d503247f hint #0x23 .*: d503247f hint #0x23
.*: d503249f hint #0x24 .*: d503249f (hint #0x24|bti j)
.*: d50324bf hint #0x25 .*: d50324bf hint #0x25
.*: d50324df hint #0x26 .*: d50324df (hint #0x26|bti jc)
.*: d50324ff hint #0x27 .*: d50324ff hint #0x27
.*: d503251f hint #0x28 .*: d503251f hint #0x28
.*: d503253f hint #0x29 .*: d503253f hint #0x29

9
include/ChangeLog
View File

@ -1,3 +1,12 @@
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_BTI): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_BTI by default.
(aarch64_opnd): Add AARCH64_OPND_BTI_TARGET.
(HINT_OPD_CSYNC, HINT_OPD_C, HINT_OPD_J): New macros to
define HINT #imm values.
(HINT_OPD_JC, HINT_OPD_NULL): Likewise.
2018-10-09 Sudakshina Das <sudi.das@arm.com> 2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_RNG): New. * opcode/aarch64.h (AARCH64_FEATURE_RNG): New.

13
include/opcode/aarch64.h
View File

@ -76,6 +76,8 @@ typedef uint32_t aarch64_insn;
#define AARCH64_FEATURE_CVADP 0x40000000000ULL #define AARCH64_FEATURE_CVADP 0x40000000000ULL
/* Random Number instructions. */ /* Random Number instructions. */
#define AARCH64_FEATURE_RNG 0x80000000000ULL #define AARCH64_FEATURE_RNG 0x80000000000ULL
/* BTI instructions. */
#define AARCH64_FEATURE_BTI 0x100000000000ULL
/* Architectures are the sum of the base and extensions. */ /* Architectures are the sum of the base and extensions. */
#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \ #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
@ -105,7 +107,8 @@ typedef uint32_t aarch64_insn;
| AARCH64_FEATURE_FRINTTS \ | AARCH64_FEATURE_FRINTTS \
| AARCH64_FEATURE_SB \ | AARCH64_FEATURE_SB \
| AARCH64_FEATURE_PREDRES \ | AARCH64_FEATURE_PREDRES \
| AARCH64_FEATURE_CVADP) | AARCH64_FEATURE_CVADP \
| AARCH64_FEATURE_BTI)
#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0) #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
@ -285,6 +288,7 @@ enum aarch64_opnd
AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */ AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
AARCH64_OPND_PRFOP, /* Prefetch operation. */ AARCH64_OPND_PRFOP, /* Prefetch operation. */
AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */ AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */ AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
@ -1090,6 +1094,13 @@ struct aarch64_inst
aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM]; aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
}; };
/* Defining the HINT #imm values for the aarch64_hint_options. */
#define HINT_OPD_CSYNC 0x11
#define HINT_OPD_C 0x22
#define HINT_OPD_J 0x24
#define HINT_OPD_JC 0x26
#define HINT_OPD_NULL 0x00
/* Diagnosis related declaration and interface. */ /* Diagnosis related declaration and interface. */

18
opcodes/ChangeLog
View File

@ -1,3 +1,21 @@
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
(HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
with the hint immediate.
* aarch64-opc.c (aarch64_hint_options): New entries for
c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
(aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
while checking for HINT_OPD_F_NOPRINT flag.
* aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
extract value.
* aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
(aarch64_opcode_table): Add entry for BTI.
(AARCH64_OPERANDS): Add new description for BTI targets.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
2018-10-09 Sudakshina Das <sudi.das@arm.com> 2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-opc.c (aarch64_sys_regs): New entries for * aarch64-opc.c (aarch64_sys_regs): New entries for

302
opcodes/aarch64-asm-2.c
View File

@ -422,165 +422,166 @@ aarch64_find_real_opcode (const aarch64_opcode *opcode)
case 1162: /* movz */ case 1162: /* movz */
value = 1162; /* --> movz. */ value = 1162; /* --> movz. */
break; break;
case 1208: /* autibsp */ case 1209: /* autibsp */
case 1207: /* autibz */ case 1208: /* autibz */
case 1206: /* autiasp */ case 1207: /* autiasp */
case 1205: /* autiaz */ case 1206: /* autiaz */
case 1204: /* pacibsp */ case 1205: /* pacibsp */
case 1203: /* pacibz */ case 1204: /* pacibz */
case 1202: /* paciasp */ case 1203: /* paciasp */
case 1201: /* paciaz */ case 1202: /* paciaz */
case 1182: /* psb */ case 1183: /* psb */
case 1181: /* esb */ case 1182: /* esb */
case 1180: /* autib1716 */ case 1181: /* autib1716 */
case 1179: /* autia1716 */ case 1180: /* autia1716 */
case 1178: /* pacib1716 */ case 1179: /* pacib1716 */
case 1177: /* pacia1716 */ case 1178: /* pacia1716 */
case 1176: /* xpaclri */ case 1177: /* xpaclri */
case 1175: /* sevl */ case 1176: /* sevl */
case 1174: /* sev */ case 1175: /* sev */
case 1173: /* wfi */ case 1174: /* wfi */
case 1172: /* wfe */ case 1173: /* wfe */
case 1171: /* yield */ case 1172: /* yield */
case 1171: /* bti */
case 1170: /* csdb */ case 1170: /* csdb */
case 1169: /* nop */ case 1169: /* nop */
case 1168: /* hint */ case 1168: /* hint */
value = 1168; /* --> hint. */ value = 1168; /* --> hint. */
break; break;
case 1186: /* pssbb */ case 1187: /* pssbb */
case 1185: /* ssbb */ case 1186: /* ssbb */
case 1184: /* dsb */ case 1185: /* dsb */
value = 1184; /* --> dsb. */ value = 1185; /* --> dsb. */
break; break;
case 1197: /* cpp */ case 1198: /* cpp */
case 1196: /* dvp */ case 1197: /* dvp */
case 1195: /* cfp */ case 1196: /* cfp */
case 1194: /* tlbi */ case 1195: /* tlbi */
case 1193: /* ic */ case 1194: /* ic */
case 1192: /* dc */ case 1193: /* dc */
case 1191: /* at */ case 1192: /* at */
case 1190: /* sys */ case 1191: /* sys */
value = 1190; /* --> sys. */ value = 1191; /* --> sys. */
break; break;
case 2006: /* bic */ case 2007: /* bic */
case 1256: /* and */ case 1257: /* and */
value = 1256; /* --> and. */ value = 1257; /* --> and. */
break; break;
case 1239: /* mov */ case 1240: /* mov */
case 1258: /* and */ case 1259: /* and */
value = 1258; /* --> and. */ value = 1259; /* --> and. */
break; break;
case 1243: /* movs */ case 1244: /* movs */
case 1259: /* ands */ case 1260: /* ands */
value = 1259; /* --> ands. */ value = 1260; /* --> ands. */
break; break;
case 2007: /* cmple */ case 2008: /* cmple */
case 1294: /* cmpge */ case 1295: /* cmpge */
value = 1294; /* --> cmpge. */ value = 1295; /* --> cmpge. */
break; break;
case 2010: /* cmplt */ case 2011: /* cmplt */
case 1297: /* cmpgt */ case 1298: /* cmpgt */
value = 1297; /* --> cmpgt. */ value = 1298; /* --> cmpgt. */
break; break;
case 2008: /* cmplo */ case 2009: /* cmplo */
case 1299: /* cmphi */ case 1300: /* cmphi */
value = 1299; /* --> cmphi. */ value = 1300; /* --> cmphi. */
break; break;
case 2009: /* cmpls */ case 2010: /* cmpls */
case 1302: /* cmphs */ case 1303: /* cmphs */
value = 1302; /* --> cmphs. */ value = 1303; /* --> cmphs. */
break; break;
case 1236: /* mov */ case 1237: /* mov */
case 1324: /* cpy */
value = 1324; /* --> cpy. */
break;
case 1238: /* mov */
case 1325: /* cpy */ case 1325: /* cpy */
value = 1325; /* --> cpy. */ value = 1325; /* --> cpy. */
break; break;
case 2017: /* fmov */ case 1239: /* mov */
case 1241: /* mov */
case 1326: /* cpy */ case 1326: /* cpy */
value = 1326; /* --> cpy. */ value = 1326; /* --> cpy. */
break; break;
case 1231: /* mov */ case 2018: /* fmov */
case 1338: /* dup */ case 1242: /* mov */
value = 1338; /* --> dup. */ case 1327: /* cpy */
value = 1327; /* --> cpy. */
break; break;
case 1233: /* mov */ case 1232: /* mov */
case 1230: /* mov */
case 1339: /* dup */ case 1339: /* dup */
value = 1339; /* --> dup. */ value = 1339; /* --> dup. */
break; break;
case 2016: /* fmov */ case 1234: /* mov */
case 1235: /* mov */ case 1231: /* mov */
case 1340: /* dup */ case 1340: /* dup */
value = 1340; /* --> dup. */ value = 1340; /* --> dup. */
break; break;
case 1234: /* mov */ case 2017: /* fmov */
case 1341: /* dupm */ case 1236: /* mov */
value = 1341; /* --> dupm. */ case 1341: /* dup */
value = 1341; /* --> dup. */
break; break;
case 2011: /* eon */ case 1235: /* mov */
case 1343: /* eor */ case 1342: /* dupm */
value = 1343; /* --> eor. */ value = 1342; /* --> dupm. */
break; break;
case 1244: /* not */ case 2012: /* eon */
case 1345: /* eor */ case 1344: /* eor */
value = 1345; /* --> eor. */ value = 1344; /* --> eor. */
break; break;
case 1245: /* nots */ case 1245: /* not */
case 1346: /* eors */ case 1346: /* eor */
value = 1346; /* --> eors. */ value = 1346; /* --> eor. */
break; break;
case 2012: /* facle */ case 1246: /* nots */
case 1351: /* facge */ case 1347: /* eors */
value = 1351; /* --> facge. */ value = 1347; /* --> eors. */
break; break;
case 2013: /* faclt */ case 2013: /* facle */
case 1352: /* facgt */ case 1352: /* facge */
value = 1352; /* --> facgt. */ value = 1352; /* --> facge. */
break; break;
case 2014: /* fcmle */ case 2014: /* faclt */
case 1365: /* fcmge */ case 1353: /* facgt */
value = 1365; /* --> fcmge. */ value = 1353; /* --> facgt. */
break; break;
case 2015: /* fcmlt */ case 2015: /* fcmle */
case 1367: /* fcmgt */ case 1366: /* fcmge */
value = 1367; /* --> fcmgt. */ value = 1366; /* --> fcmge. */
break;
case 2016: /* fcmlt */
case 1368: /* fcmgt */
value = 1368; /* --> fcmgt. */
break;
case 1229: /* fmov */
case 1374: /* fcpy */
value = 1374; /* --> fcpy. */
break; break;
case 1228: /* fmov */ case 1228: /* fmov */
case 1373: /* fcpy */ case 1397: /* fdup */
value = 1373; /* --> fcpy. */ value = 1397; /* --> fdup. */
break; break;
case 1227: /* fmov */ case 1230: /* mov */
case 1396: /* fdup */
value = 1396; /* --> fdup. */
break;
case 1229: /* mov */
case 1727: /* orr */
value = 1727; /* --> orr. */
break;
case 2018: /* orn */
case 1728: /* orr */ case 1728: /* orr */
value = 1728; /* --> orr. */ value = 1728; /* --> orr. */
break; break;
case 1232: /* mov */ case 2019: /* orn */
case 1730: /* orr */ case 1729: /* orr */
value = 1730; /* --> orr. */ value = 1729; /* --> orr. */
break; break;
case 1242: /* movs */ case 1233: /* mov */
case 1731: /* orrs */ case 1731: /* orr */
value = 1731; /* --> orrs. */ value = 1731; /* --> orr. */
break; break;
case 1237: /* mov */ case 1243: /* movs */
case 1793: /* sel */ case 1732: /* orrs */
value = 1793; /* --> sel. */ value = 1732; /* --> orrs. */
break; break;
case 1240: /* mov */ case 1238: /* mov */
case 1794: /* sel */ case 1794: /* sel */
value = 1794; /* --> sel. */ value = 1794; /* --> sel. */
break; break;
case 1241: /* mov */
case 1795: /* sel */
value = 1795; /* --> sel. */
break;
default: return NULL; default: return NULL;
} }
@ -622,7 +623,6 @@ aarch64_insert_operand (const aarch64_operand *self,
case 27: case 27:
case 28: case 28:
case 29: case 29:
case 154:
case 155: case 155:
case 156: case 156:
case 157: case 157:
@ -632,7 +632,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 161: case 161:
case 162: case 162:
case 163: case 163:
case 176: case 164:
case 177: case 177:
case 178: case 178:
case 179: case 179:
@ -641,8 +641,9 @@ aarch64_insert_operand (const aarch64_operand *self,
case 182: case 182:
case 183: case 183:
case 184: case 184:
case 188: case 185:
case 191: case 189:
case 192:
return aarch64_ins_regno (self, info, code, inst, errors); return aarch64_ins_regno (self, info, code, inst, errors);
case 13: case 13:
return aarch64_ins_reg_extended (self, info, code, inst, errors); return aarch64_ins_reg_extended (self, info, code, inst, errors);
@ -654,7 +655,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 31: case 31:
case 32: case 32:
case 33: case 33:
case 193: case 194:
return aarch64_ins_reglane (self, info, code, inst, errors); return aarch64_ins_reglane (self, info, code, inst, errors);
case 34: case 34:
return aarch64_ins_reglist (self, info, code, inst, errors); return aarch64_ins_reglist (self, info, code, inst, errors);
@ -686,9 +687,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 77: case 77:
case 78: case 78:
case 79: case 79:
case 151: case 152:
case 153: case 154:
case 168:
case 169: case 169:
case 170: case 170:
case 171: case 171:
@ -696,6 +696,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 173: case 173:
case 174: case 174:
case 175: case 175:
case 176:
return aarch64_ins_imm (self, info, code, inst, errors); return aarch64_ins_imm (self, info, code, inst, errors);
case 42: case 42:
case 43: case 43:
@ -705,10 +706,10 @@ aarch64_insert_operand (const aarch64_operand *self,
case 46: case 46:
return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors); return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
case 50: case 50:
case 142: case 143:
return aarch64_ins_fpimm (self, info, code, inst, errors); return aarch64_ins_fpimm (self, info, code, inst, errors);
case 65: case 65:
case 149: case 150:
return aarch64_ins_limm (self, info, code, inst, errors); return aarch64_ins_limm (self, info, code, inst, errors);
case 66: case 66:
return aarch64_ins_aimm (self, info, code, inst, errors); return aarch64_ins_aimm (self, info, code, inst, errors);
@ -718,10 +719,10 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_fbits (self, info, code, inst, errors); return aarch64_ins_fbits (self, info, code, inst, errors);
case 70: case 70:
case 71: case 71:
case 147: case 148:
return aarch64_ins_imm_rotate2 (self, info, code, inst, errors); return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
case 72: case 72:
case 146: case 147:
return aarch64_ins_imm_rotate1 (self, info, code, inst, errors); return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
case 73: case 73:
case 74: case 74:
@ -759,24 +760,24 @@ aarch64_insert_operand (const aarch64_operand *self,
case 99: case 99:
return aarch64_ins_prfop (self, info, code, inst, errors); return aarch64_ins_prfop (self, info, code, inst, errors);
case 100: case 100:
return aarch64_ins_hint (self, info, code, inst, errors);
case 101: case 101:
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors); return aarch64_ins_hint (self, info, code, inst, errors);
case 102: case 102:
return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
case 103: case 103:
case 104: case 104:
case 105: case 105:
return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 106: case 106:
return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors); return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
case 107: case 107:
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors); return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
case 108: case 108:
return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
case 109: case 109:
case 110: case 110:
case 111: case 111:
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 112: case 112:
return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
case 113: case 113:
case 114: case 114:
case 115: case 115:
@ -789,8 +790,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case 122: case 122:
case 123: case 123:
case 124: case 124:
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 125: case 125:
return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
case 126: case 126:
case 127: case 127:
case 128: case 128:
@ -798,48 +799,49 @@ aarch64_insert_operand (const aarch64_operand *self,
case 130: case 130:
case 131: case 131:
case 132: case 132:
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 133: case 133:
return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
case 134: case 134:
case 135: case 135:
case 136: case 136:
return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 137: case 137:
return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors); return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
case 138: case 138:
return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors); return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
case 139: case 139:
return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors); return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
case 140: case 140:
return aarch64_ins_sve_aimm (self, info, code, inst, errors); return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
case 141: case 141:
return aarch64_ins_sve_aimm (self, info, code, inst, errors);
case 142:
return aarch64_ins_sve_asimm (self, info, code, inst, errors); return aarch64_ins_sve_asimm (self, info, code, inst, errors);
case 143:
return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 144: case 144:
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors); return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
case 145: case 145:
return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
case 146:
return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors); return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
case 148: case 149:
return aarch64_ins_inv_limm (self, info, code, inst, errors); return aarch64_ins_inv_limm (self, info, code, inst, errors);
case 150: case 151:
return aarch64_ins_sve_limm_mov (self, info, code, inst, errors); return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
case 152: case 153:
return aarch64_ins_sve_scale (self, info, code, inst, errors); return aarch64_ins_sve_scale (self, info, code, inst, errors);
case 164:
case 165: case 165:
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 166: case 166:
return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
case 167: case 167:
case 168:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors); return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
case 185:
case 186: case 186:
case 187: case 187:
case 188:
return aarch64_ins_sve_quad_index (self, info, code, inst, errors); return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
case 189:
return aarch64_ins_sve_index (self, info, code, inst, errors);
case 190: case 190:
case 192: return aarch64_ins_sve_index (self, info, code, inst, errors);
case 191:
case 193:
return aarch64_ins_sve_reglist (self, info, code, inst, errors); return aarch64_ins_sve_reglist (self, info, code, inst, errors);
default: assert (0); abort (); default: assert (0); abort ();
} }

2208
opcodes/aarch64-dis-2.c
View File

File diff suppressed because it is too large Load Diff

2
opcodes/aarch64-dis.c
View File

@ -1312,7 +1312,7 @@ aarch64_ext_hint (const aarch64_operand *self ATTRIBUTE_UNUSED,
for (i = 0; aarch64_hint_options[i].name != NULL; i++) for (i = 0; aarch64_hint_options[i].name != NULL; i++)
{ {
if (hint_number == aarch64_hint_options[i].value) if (hint_number == HINT_VAL (aarch64_hint_options[i].value))
{ {
info->hint_option = &(aarch64_hint_options[i]); info->hint_option = &(aarch64_hint_options[i]);
return TRUE; return TRUE;

17
opcodes/aarch64-opc-2.c
View File

@ -125,6 +125,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the ISB option name SY or an optional 4-bit unsigned immediate"}, {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the ISB option name SY or an optional 4-bit unsigned immediate"},
{AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a prefetch operation specifier"}, {AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a prefetch operation specifier"},
{AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the PSB option name CSYNC"}, {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the PSB option name CSYNC"},
{AARCH64_OPND_CLASS_SYSTEM, "BTI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "BTI targets j/c/jc"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x16", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 16"}, {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x16", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 16"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by VL"}, {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by VL"},
{AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x2xVL", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 2*VL"}, {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x2xVL", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 2*VL"},
@ -295,17 +296,17 @@ static const unsigned op_enum_table [] =
389, 389,
411, 411,
413, 413,
1232,
1237,
1230,
1229,
1233, 1233,
1240, 1238,
1242, 1231,
1230,
1234,
1241,
1243, 1243,
1239,
1245,
1244, 1244,
1240,
1246,
1245,
129, 129,
}; };

11
opcodes/aarch64-opc.c
View File

@ -466,8 +466,13 @@ const struct aarch64_name_value_pair aarch64_barrier_options[16] =
const struct aarch64_name_value_pair aarch64_hint_options[] = const struct aarch64_name_value_pair aarch64_hint_options[] =
{ {
{ "csync", 0x11 }, /* PSB CSYNC. */ /* BTI. This is also the F_DEFAULT entry for AARCH64_OPND_BTI_TARGET. */
{ NULL, 0x0 }, { " ", HINT_ENCODE (HINT_OPD_F_NOPRINT, 0x20) },
{ "csync", HINT_OPD_CSYNC }, /* PSB CSYNC. */
{ "c", HINT_OPD_C }, /* BTI C. */
{ "j", HINT_OPD_J }, /* BTI J. */
{ "jc", HINT_OPD_JC }, /* BTI JC. */
{ NULL, HINT_OPD_NULL },
}; };
/* op -> op: load = 0 instruction = 1 store = 2 /* op -> op: load = 0 instruction = 1 store = 2
@ -3654,6 +3659,8 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
break; break;
case AARCH64_OPND_BARRIER_PSB: case AARCH64_OPND_BARRIER_PSB:
case AARCH64_OPND_BTI_TARGET:
if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0)
snprintf (buf, size, "%s", opnd->hint_option->name); snprintf (buf, size, "%s", opnd->hint_option->name);
break; break;

8
opcodes/aarch64-opc.h
View File

@ -220,6 +220,14 @@ verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
#define F_REG_WRITE (1 << 4) /* Register can only be written to but not #define F_REG_WRITE (1 << 4) /* Register can only be written to but not
read from. */ read from. */
/* HINT operand flags. */
#define HINT_OPD_F_NOPRINT (1 << 0) /* Should not be printed. */
/* Encode 7-bit HINT #imm in the lower 8 bits. Use higher bits for flags. */
#define HINT_ENCODE(flag, val) ((flag << 8) | val)
#define HINT_FLAG(val) (val >> 8)
#define HINT_VAL(val) (val & 0xff)
static inline bfd_boolean static inline bfd_boolean
operand_has_inserter (const aarch64_operand *operand) operand_has_inserter (const aarch64_operand *operand)
{ {

8
opcodes/aarch64-tbl.h
View File

@ -2169,6 +2169,8 @@ static const aarch64_feature_set aarch64_feature_sb =
AARCH64_FEATURE (AARCH64_FEATURE_SB, 0); AARCH64_FEATURE (AARCH64_FEATURE_SB, 0);
static const aarch64_feature_set aarch64_feature_predres = static const aarch64_feature_set aarch64_feature_predres =
AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0); AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0);
static const aarch64_feature_set aarch64_feature_bti =
AARCH64_FEATURE (AARCH64_FEATURE_BTI, 0);
#define CORE &aarch64_feature_v8 #define CORE &aarch64_feature_v8
@ -2202,6 +2204,7 @@ static const aarch64_feature_set aarch64_feature_predres =
#define FRINTTS &aarch64_feature_frintts #define FRINTTS &aarch64_feature_frintts
#define SB &aarch64_feature_sb #define SB &aarch64_feature_sb
#define PREDRES &aarch64_feature_predres #define PREDRES &aarch64_feature_predres
#define BTI &aarch64_feature_bti
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
@ -2263,6 +2266,8 @@ static const aarch64_feature_set aarch64_feature_predres =
{ NAME, OPCODE, MASK, CLASS, 0, SB, OPS, QUALS, FLAGS, 0, 0, NULL } { NAME, OPCODE, MASK, CLASS, 0, SB, OPS, QUALS, FLAGS, 0, 0, NULL }
#define PREDRES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ #define PREDRES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, PREDRES, OPS, QUALS, FLAGS, 0, 0, NULL } { NAME, OPCODE, MASK, CLASS, 0, PREDRES, OPS, QUALS, FLAGS, 0, 0, NULL }
#define BTI_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, 0, BTI, OPS, QUALS, FLAGS, 0, 0, NULL }
struct aarch64_opcode aarch64_opcode_table[] = struct aarch64_opcode aarch64_opcode_table[] =
{ {
@ -3510,6 +3515,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
CORE_INSN ("hint",0xd503201f, 0xfffff01f, ic_system, 0, OP1 (UIMM7), {}, F_HAS_ALIAS), CORE_INSN ("hint",0xd503201f, 0xfffff01f, ic_system, 0, OP1 (UIMM7), {}, F_HAS_ALIAS),
CORE_INSN ("nop", 0xd503201f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), CORE_INSN ("nop", 0xd503201f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
CORE_INSN ("csdb",0xd503229f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), CORE_INSN ("csdb",0xd503229f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
BTI_INSN ("bti",0xd503241f, 0xffffff3f, ic_system, OP1 (BTI_TARGET), {}, F_ALIAS | F_OPD0_OPT | F_DEFAULT (0x0)),
CORE_INSN ("yield", 0xd503203f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), CORE_INSN ("yield", 0xd503203f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
CORE_INSN ("wfe", 0xd503205f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), CORE_INSN ("wfe", 0xd503205f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
CORE_INSN ("wfi", 0xd503207f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), CORE_INSN ("wfi", 0xd503207f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
@ -4629,6 +4635,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
"a prefetch operation specifier") \ "a prefetch operation specifier") \
Y(SYSTEM, hint, "BARRIER_PSB", 0, F (), \ Y(SYSTEM, hint, "BARRIER_PSB", 0, F (), \
"the PSB option name CSYNC") \ "the PSB option name CSYNC") \
Y(SYSTEM, hint, "BTI", 0, F (), \
"BTI targets j/c/jc") \
Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x16", \ Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x16", \
4 << OPD_F_OD_LSB, F(FLD_Rn), \ 4 << OPD_F_OD_LSB, F(FLD_Rn), \
"an address with a 4-bit signed offset, multiplied by 16") \ "an address with a 4-bit signed offset, multiplied by 16") \