* ppc-dis.c (operand_value_powerpc, skip_optional_operands): New.
(print_insn_powerpc): Use the new operand_value_powerpc and skip_optional_operands functions to omit or print all optional operands as a group. * ppc-opc.c (BFF, W, XFL_L, XWRA_MASK): New. (XFL_MASK): Delete L and W bits from the mask. (mtfsfi, mtfsfi.): Replace use of BF with BFF. Relpace use of XRA_MASK with XWRA_MASK. Use W. (mtfsf, mtfsf.): Use XFL_L and W.
This commit is contained in:
Peter Bergner
parent
f891f2a91d
commit
ea192fa395
@ -1,3 +1,15 @@
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2007-05-16 Peter Bergner <bergner@vnet.ibm.com>
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* ppc-dis.c (operand_value_powerpc, skip_optional_operands): New.
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(print_insn_powerpc): Use the new operand_value_powerpc and
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skip_optional_operands functions to omit or print all optional
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operands as a group.
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* ppc-opc.c (BFF, W, XFL_L, XWRA_MASK): New.
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(XFL_MASK): Delete L and W bits from the mask.
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(mtfsfi, mtfsfi.): Replace use of BF with BFF. Relpace use of XRA_MASK
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with XWRA_MASK. Use W.
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(mtfsf, mtfsf.): Use XFL_L and W.
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2007-05-14 H.J. Lu <hongjiu.lu@intel.com>
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PR binutils/4502
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@ -127,6 +127,56 @@ print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info)
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return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER);
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}
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/* Extract the operand value from the PowerPC or POWER instruction. */
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static long
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operand_value_powerpc (const struct powerpc_operand *operand,
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unsigned long insn, int dialect)
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{
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long value;
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int invalid;
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/* Extract the value from the instruction. */
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if (operand->extract)
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value = (*operand->extract) (insn, dialect, &invalid);
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else
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{
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value = (insn >> operand->shift) & operand->bitm;
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if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
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{
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/* BITM is always some number of zeros followed by some
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number of ones, followed by some numer of zeros. */
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unsigned long top = operand->bitm;
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/* top & -top gives the rightmost 1 bit, so this
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fills in any trailing zeros. */
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top |= (top & -top) - 1;
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top &= ~(top >> 1);
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value = (value ^ top) - top;
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}
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}
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return value;
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}
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/* Determine whether the optional operand(s) should be printed. */
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static int
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skip_optional_operands (const unsigned char *opindex,
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unsigned long insn, int dialect)
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{
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const struct powerpc_operand *operand;
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for (; *opindex != 0; opindex++)
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{
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operand = &powerpc_operands[*opindex];
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if ((operand->flags & PPC_OPERAND_NEXT) != 0
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|| ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
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&& operand_value_powerpc (operand, insn, dialect) != 0))
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return 0;
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}
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return 1;
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}
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/* Print a PowerPC or POWER instruction. */
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static int
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@ -172,6 +222,7 @@ print_insn_powerpc (bfd_vma memaddr,
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int invalid;
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int need_comma;
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int need_paren;
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int skip_optional;
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table_op = PPC_OP (opcode->opcode);
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if (op < table_op)
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@ -205,6 +256,7 @@ print_insn_powerpc (bfd_vma memaddr,
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/* Now extract and print the operands. */
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need_comma = 0;
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need_paren = 0;
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skip_optional = -1;
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for (opindex = opcode->operands; *opindex != 0; opindex++)
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{
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long value;
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@ -217,32 +269,17 @@ print_insn_powerpc (bfd_vma memaddr,
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if ((operand->flags & PPC_OPERAND_FAKE) != 0)
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continue;
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/* Extract the value from the instruction. */
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if (operand->extract)
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value = (*operand->extract) (insn, dialect, &invalid);
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else
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{
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value = (insn >> operand->shift) & operand->bitm;
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if ((operand->flags & PPC_OPERAND_SIGNED) != 0)
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{
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/* BITM is always some number of zeros followed by some
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number of ones, followed by some numer of zeros. */
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unsigned long top = operand->bitm;
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/* top & -top gives the rightmost 1 bit, so this
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fills in any trailing zeros. */
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top |= (top & -top) - 1;
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top &= ~(top >> 1);
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value = (value ^ top) - top;
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}
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}
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/* If all of the optional operands have the value zero,
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then don't print any of them. */
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if (skip_optional < 0
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&& (operand->flags & PPC_OPERAND_OPTIONAL) != 0)
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skip_optional = skip_optional_operands (opindex, insn, dialect);
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/* If the operand is optional, and the value is zero, don't
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print anything. */
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if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
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&& (operand->flags & PPC_OPERAND_NEXT) == 0
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&& value == 0)
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if (skip_optional > 0)
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continue;
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value = operand_value_powerpc (operand, insn, dialect);
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if (need_comma)
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{
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(*info->fprintf_func) (info->stream, ",");
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@ -154,9 +154,13 @@ const struct powerpc_operand powerpc_operands[] =
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#define CRFD BF
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{ 0x7, 23, NULL, NULL, PPC_OPERAND_CR },
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/* The BF field in an X or XL form instruction. */
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#define BFF BF + 1
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{ 0x7, 23, NULL, NULL, 0 },
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/* An optional BF field. This is used for comparison instructions,
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in which an omitted BF field is taken as zero. */
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#define OBF BF + 1
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#define OBF BFF + 1
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{ 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },
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/* The BFA field in an X or XL form instruction. */
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@ -515,8 +519,9 @@ const struct powerpc_operand powerpc_operands[] =
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#define WS EVUIMM_8 + 1
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{ 0x7, 11, NULL, NULL, 0 },
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/* The L field in an mtmsrd or A form instruction. */
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/* The L field in an mtmsrd or A form instruction or W in an X form. */
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#define A_L WS + 1
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#define W A_L
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{ 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },
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#define RMC A_L + 1
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@ -541,6 +546,10 @@ const struct powerpc_operand powerpc_operands[] =
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/* The EH field in larx instruction. */
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#define EH SH16 + 1
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{ 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },
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/* The L field in an mtfsf or XFL form instruction. */
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#define XFL_L EH + 1
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{ 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
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};
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const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
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@ -1400,6 +1409,9 @@ extract_tbr (unsigned long insn,
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/* An X_MASK with the RA field fixed. */
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#define XRA_MASK (X_MASK | RA_MASK)
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/* An XRA_MASK with the W field clear. */
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#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))
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/* An X_MASK with the RB field fixed. */
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#define XRB_MASK (X_MASK | RB_MASK)
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@ -1454,7 +1466,7 @@ extract_tbr (unsigned long insn,
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/* An XFL form instruction. */
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#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
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#define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16))
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#define XFL_MASK XFL (0x3f, 0x3ff, 1)
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/* An X form isel instruction. */
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#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
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@ -4586,8 +4598,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "dcmpoq", X(63,130), X_MASK, POWER6, { BF, FRA, FRB } },
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{ "mtfsfi", XRC(63,134,0), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
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{ "mtfsfi.", XRC(63,134,1), XRA_MASK|(3<<21)|(1<<11), COM, { BF, U } },
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{ "mtfsfi", XRC(63,134,0), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } },
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{ "mtfsfi.", XRC(63,134,1), XWRA_MASK|(3<<21)|(1<<11), COM, { BFF, U, W } },
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{ "fnabs", XRC(63,136,0), XRA_MASK, COM, { FRT, FRB } },
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{ "fnabs.", XRC(63,136,1), XRA_MASK, COM, { FRT, FRB } },
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@ -4636,8 +4648,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
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{ "dtstsfq", X(63,674), X_MASK, POWER6, { BF, FRA, FRB } },
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{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB } },
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{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB } },
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{ "mtfsf", XFL(63,711,0), XFL_MASK, COM, { FLM, FRB, XFL_L, W } },
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{ "mtfsf.", XFL(63,711,1), XFL_MASK, COM, { FLM, FRB, XFL_L, W } },
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{ "drdpq", XRC(63,770,0), X_MASK, POWER6, { FRT, FRB } },
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{ "drdpq.", XRC(63,770,1), X_MASK, POWER6, { FRT, FRB } },
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