FT32: support for FT32B processor - part 2/2
FT32B is a new FT32 family member. This patch adds support for the compressed instructions to gdb and sim. gdb/ChangeLog: * ft32-tdep.c (ft32_fetch_instruction): New function. (ft32_analyze_prologue): Use ft32_fetch_instruction(). sim/ChangeLog: * ft32/interp.c (step_once): Add ft32 shortcode decoder.
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@ -1,3 +1,8 @@
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2017-11-01 James Bowman <james.bowman@ftdichip.com>
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* ft32-tdep.c (ft32_fetch_instruction): New function.
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(ft32_analyze_prologue): Use ft32_fetch_instruction().
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2017-10-31 Simon Marchi <simon.marchi@polymtl.ca>
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* cli/cli-script.c (execute_control_command): Rename to ...
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@ -139,6 +139,25 @@ ft32_store_return_value (struct type *type, struct regcache *regcache,
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}
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}
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/* Fetch a single 32-bit instruction from address a. If memory contains
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a compressed instruction pair, return the expanded instruction. */
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static ULONGEST
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ft32_fetch_instruction (CORE_ADDR a, int *isize,
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enum bfd_endian byte_order)
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{
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unsigned int sc[2];
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ULONGEST inst;
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CORE_ADDR a4 = a & ~3;
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inst = read_code_unsigned_integer (a4, 4, byte_order);
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*isize = ft32_decode_shortcode (a4, inst, sc) ? 2 : 4;
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if (*isize == 2)
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return sc[1 & (a >> 1)];
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else
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return inst;
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}
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/* Decode the instructions within the given address range. Decide
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when we must have reached the end of the function prologue. If a
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frame_info pointer is provided, fill in its saved_regs etc.
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@ -153,6 +172,7 @@ ft32_analyze_prologue (CORE_ADDR start_addr, CORE_ADDR end_addr,
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enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
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CORE_ADDR next_addr;
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ULONGEST inst;
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int isize = 0;
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int regnum, pushreg;
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struct bound_minimal_symbol msymbol;
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const int first_saved_reg = 13; /* The first saved register. */
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@ -186,16 +206,15 @@ ft32_analyze_prologue (CORE_ADDR start_addr, CORE_ADDR end_addr,
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return end_addr;
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cache->established = 0;
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for (next_addr = start_addr; next_addr < end_addr;)
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for (next_addr = start_addr; next_addr < end_addr; next_addr += isize)
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{
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inst = read_memory_unsigned_integer (next_addr, 4, byte_order);
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inst = ft32_fetch_instruction (next_addr, &isize, byte_order);
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if (FT32_IS_PUSH (inst))
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{
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pushreg = FT32_PUSH_REG (inst);
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cache->framesize += 4;
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cache->saved_regs[FT32_R0_REGNUM + pushreg] = cache->framesize;
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next_addr += 4;
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}
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else if (FT32_IS_CALL (inst))
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{
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@ -210,7 +229,6 @@ ft32_analyze_prologue (CORE_ADDR start_addr, CORE_ADDR end_addr,
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cache->saved_regs[FT32_R0_REGNUM + pushreg] =
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cache->framesize;
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}
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next_addr += 4;
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}
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}
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break;
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@ -229,7 +247,7 @@ ft32_analyze_prologue (CORE_ADDR start_addr, CORE_ADDR end_addr,
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/* It is a LINK? */
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if (next_addr < end_addr)
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{
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inst = read_memory_unsigned_integer (next_addr, 4, byte_order);
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inst = ft32_fetch_instruction (next_addr, &isize, byte_order);
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if (FT32_IS_LINK (inst))
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{
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cache->established = 1;
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@ -241,7 +259,7 @@ ft32_analyze_prologue (CORE_ADDR start_addr, CORE_ADDR end_addr,
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cache->saved_regs[FT32_PC_REGNUM] = cache->framesize + 4;
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cache->saved_regs[FT32_FP_REGNUM] = 0;
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cache->framesize += FT32_LINK_SIZE (inst);
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next_addr += 4;
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next_addr += isize;
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}
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}
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@ -1,3 +1,7 @@
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2017-11-01 James Bowman <james.bowman@ftdichip.com>
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* ft32/interp.c (step_once): Add ft32 shortcode decoder.
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2017-10-12 James Bowman <james.bowman@ftdichip.com>
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* ft32/interp.c (step_once): Replace FT32_FLD_K8 with K15.
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@ -340,16 +340,24 @@ step_once (SIM_DESC sd)
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uint32_t bit_len;
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uint32_t upper;
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uint32_t insnpc;
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unsigned int sc[2];
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int isize;
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if (cpu->state.cycles >= cpu->state.next_tick_cycle)
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{
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cpu->state.next_tick_cycle += 100000;
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ft32_push (sd, cpu->state.pc);
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cpu->state.pc = 12; /* interrupt 1. */
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}
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inst = ft32_read_item (sd, 2, cpu->state.pc);
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cpu->state.cycles += 1;
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if ((STATE_ARCHITECTURE (sd)->mach == bfd_mach_ft32b)
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&& ft32_decode_shortcode (cpu->state.pc, inst, sc))
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{
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if ((cpu->state.pc & 3) == 0)
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inst = sc[0];
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else
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inst = sc[1];
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isize = 2;
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}
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else
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isize = 4;
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/* Handle "call 8" (which is FT32's "break" equivalent) here. */
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if (inst == 0x00340002)
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{
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@ -390,7 +398,7 @@ step_once (SIM_DESC sd)
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upper = (inst >> 27);
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insnpc = cpu->state.pc;
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cpu->state.pc += 4;
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cpu->state.pc += isize;
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switch (upper)
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{
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case FT32_PAT_TOC:
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