x86: SYSENTER/SYSEXIT are unavailable in 64-bit mode on AMD
The disassembler change is such that in default mode we'd disassemble the insns (for there not ebing any conflicts), but when AMD64 mode was explicitly requested, we'd show them as "(bad)".
This commit is contained in:
Jan Beulich
parent
482556efed
commit
d835a58baa
@ -1,3 +1,12 @@
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2020-01-09 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/i386/x86-64-sysenter-amd.s,
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testsuite/gas/i386/x86-64-sysenter-amd.d,
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testsuite/gas/i386/x86-64-sysenter-amd.l,
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testsuite/gas/i386/x86-64-sysenter-intel.d,
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testsuite/gas/i386/x86-64-sysenter-mixed.d: New.
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* testsuite/gas/i386/i386.exp: Run new tests.
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2020-01-08 Nick Clifton <nickc@redhat.com>
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PR 25284
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@ -724,6 +724,10 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
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run_dump_test "x86-64-nops-5"
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run_dump_test "x86-64-nops-5-k8"
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run_dump_test "x86-64-nops-7"
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run_dump_test "x86-64-sysenter-intel"
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run_dump_test "x86-64-sysenter-mixed"
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run_dump_test "x86-64-sysenter-amd"
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run_list_test "x86-64-sysenter-amd"
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run_dump_test "noreg64"
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run_list_test "cvtsi2sX"
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run_dump_test "x86-64-sse4_1"
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14
gas/testsuite/gas/i386/x86-64-sysenter-amd.d
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14
gas/testsuite/gas/i386/x86-64-sysenter-amd.d
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@ -0,0 +1,14 @@
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#as: -mintel64
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#objdump: -dw -Mamd64
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#name: x86-64 sysenter (Intel64/AMD64)
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.*: +file format .*
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Disassembly of section .text:
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0+ <.text>:
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[ ]*[a-f0-9]+:[ ]+0f 34[ ]+\(bad\)[ ]*
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[ ]*[a-f0-9]+:[ ]+0f 35[ ]+\(bad\)[ ]*
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[ ]*[a-f0-9]+:[ ]+0f 34[ ]+\(bad\)[ ]*
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[ ]*[a-f0-9]+:[ ]+0f 35[ ]+\(bad\)[ ]*
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#pass
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5
gas/testsuite/gas/i386/x86-64-sysenter-amd.l
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5
gas/testsuite/gas/i386/x86-64-sysenter-amd.l
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@ -0,0 +1,5 @@
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.*: Assembler messages:
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.*:2: Error: .*
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.*:3: Error: .*
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.*:6: Error: .*
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.*:7: Error: .*
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7
gas/testsuite/gas/i386/x86-64-sysenter-amd.s
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7
gas/testsuite/gas/i386/x86-64-sysenter-amd.s
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@ -0,0 +1,7 @@
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.text
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sysenter
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sysexit
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.intel_syntax noprefix
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sysenter
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sysexit
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15
gas/testsuite/gas/i386/x86-64-sysenter-intel.d
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15
gas/testsuite/gas/i386/x86-64-sysenter-intel.d
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@ -0,0 +1,15 @@
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#as: -mintel64
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#objdump: -dw -Mintel64
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#name: x86-64 sysenter (Intel64/Intel64)
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#source: x86-64-sysenter-amd.s
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.*: +file format .*
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Disassembly of section .text:
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0+ <.text>:
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[ ]*[a-f0-9]+: 0f 34 sysenter *
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[ ]*[a-f0-9]+: 0f 35 sysexit *
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[ ]*[a-f0-9]+: 0f 34 sysenter *
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[ ]*[a-f0-9]+: 0f 35 sysexit *
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#pass
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6
gas/testsuite/gas/i386/x86-64-sysenter-mixed.d
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6
gas/testsuite/gas/i386/x86-64-sysenter-mixed.d
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@ -0,0 +1,6 @@
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#as: -mintel64
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#objdump: -dw
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#name: x86-64 sysenter (Intel64/Default)
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#source: x86-64-sysenter-amd.s
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#dump: x86-64-sysenter-intel.d
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@ -1,3 +1,14 @@
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2020-01-09 Jan Beulich <jbeulich@suse.com>
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* i386-dis.c (SEP_Fixup): New.
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(SEP): Define.
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(dis386_twobyte): Use it for sysenter/sysexit.
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(enum x86_64_isa): Change amd64 enumerator to value 1.
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(OP_J): Compare isa64 against intel64 instead of amd64.
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* i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
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forms.
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* i386-tbl.h: Re-generate.
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2020-01-08 Alan Modra <amodra@gmail.com>
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* z8k-dis.c: Include libiberty.h
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@ -107,6 +107,7 @@ static void OP_3DNowSuffix (int, int);
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static void CMP_Fixup (int, int);
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static void BadOp (void);
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static void REP_Fixup (int, int);
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static void SEP_Fixup (int, int);
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static void BND_Fixup (int, int);
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static void NOTRACK_Fixup (int, int);
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static void HLE_Fixup1 (int, int);
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@ -412,6 +413,7 @@ fetch_data (struct disassemble_info *info, bfd_byte *addr)
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#define EMCq { OP_EMC, q_mode }
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#define MXC { OP_MXC, 0 }
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#define OPSUF { OP_3DNowSuffix, 0 }
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#define SEP { SEP_Fixup, 0 }
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#define CMP { CMP_Fixup, 0 }
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#define XMM0 { XMM_Fixup, 0 }
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#define FXSAVE { FXSAVE_Fixup, 0 }
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@ -2713,8 +2715,8 @@ static const struct dis386 dis386_twobyte[] = {
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{ "rdtsc", { XX }, 0 },
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{ "rdmsr", { XX }, 0 },
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{ "rdpmc", { XX }, 0 },
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{ "sysenter", { XX }, 0 },
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{ "sysexit", { XX }, 0 },
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{ "sysenter", { SEP }, 0 },
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{ "sysexit", { SEP }, 0 },
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{ Bad_Opcode },
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{ "getsec", { XX }, 0 },
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/* 38 */
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@ -11316,7 +11318,7 @@ static char scale_char;
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enum x86_64_isa
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{
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amd64 = 0,
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amd64 = 1,
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intel64
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};
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@ -14829,12 +14831,12 @@ OP_J (int bytemode, int sizeflag)
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disp -= 0x100;
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break;
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case v_mode:
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if (isa64 == amd64)
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if (isa64 != intel64)
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case dqw_mode:
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USED_REX (REX_W);
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if ((sizeflag & DFLAG)
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|| (address_mode == mode_64bit
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&& ((isa64 != amd64 && bytemode != dqw_mode)
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&& ((isa64 == intel64 && bytemode != dqw_mode)
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|| (rex & REX_W))))
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disp = get32s ();
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else
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@ -14852,7 +14854,7 @@ OP_J (int bytemode, int sizeflag)
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& ~((bfd_vma) 0xffff));
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}
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if (address_mode != mode_64bit
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|| (isa64 == amd64 && !(rex & REX_W)))
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|| (isa64 != intel64 && !(rex & REX_W)))
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used_prefixes |= (prefixes & PREFIX_DATA);
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break;
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default:
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@ -15602,6 +15604,18 @@ REP_Fixup (int bytemode, int sizeflag)
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}
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}
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static void
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SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
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{
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if ( isa64 != amd64 )
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return;
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obufp = obuf;
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BadOp ();
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mnemonicendp = obufp;
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++codep;
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}
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/* For BND-prefixed instructions 0xF2 prefix should be displayed as
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"bnd". */
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@ -904,8 +904,10 @@ rdmsr, 0, 0xf32, None, 2, Cpu586, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldS
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cmpxchg8b, 1, 0xfc7, 0x1, 2, Cpu586, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|IsLockable|NoRex64|HLEPrefixOk, { Qword|Unspecified|BaseIndex }
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// Pentium II/Pentium Pro extensions.
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sysenter, 0, 0xf34, None, 2, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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sysexit, 0, 0xf35, None, 2, Cpu686, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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sysenter, 0, 0xf34, None, 2, Cpu686, Intel64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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sysenter, 0, 0xf34, None, 2, Cpu686|CpuNo64, AMD64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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sysexit, 0, 0xf35, None, 2, Cpu686, Intel64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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sysexit, 0, 0xf35, None, 2, Cpu686|CpuNo64, AMD64|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
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fxsave, 1, 0xfae, 0x0, 2, CpuFXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex }
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fxsave64, 1, 0xfae, 0x0, 2, CpuFXSR|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Rex64, { Unspecified|BaseIndex }
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fxrstor, 1, 0xfae, 0x1, 2, CpuFXSR, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex }
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@ -7805,7 +7805,19 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ "sysenter", 0xf34, None, 2, 0,
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{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ "sysexit", 0xf35, None, 2, 0,
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@ -7817,7 +7829,19 @@ const insn_template i386_optab[] =
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ "sysexit", 0xf35, None, 2, 0,
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{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 } },
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0 },
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{ { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0 } } } },
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{ "fxsave", 0xfae, 0x0, 2, 1,
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