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PR27684, PowerPC missing mfsprg0 and others

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PR 27684
	* ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
This commit is contained in:
Alan Modra 2021-04-05 08:17:51 +09:30
parent 97bf40d859
commit ce7d813a0f
2 changed files with 10 additions and 4 deletions
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5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2021-04-08 Alan Modra <amodra@gmail.com>
PR 27684
* ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
2021-04-08 Alan Modra <amodra@gmail.com> 2021-04-08 Alan Modra <amodra@gmail.com>
PR 27676 PR 27676

9
opcodes/ppc-opc.c
View File

@ -6975,8 +6975,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}}, {"mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, 0, {RT}},
{"mftir", XSPR(31,339,446), XSPR_MASK, POWER10, 0, {RS}}, {"mftir", XSPR(31,339,446), XSPR_MASK, POWER10, 0, {RS}},
{"mfptcr", XSPR(31,339,464), XSPR_MASK, POWER10, 0, {RS}}, {"mfptcr", XSPR(31,339,464), XSPR_MASK, POWER10, 0, {RS}},
{"mfuspgr0", XSPR(31,339,496), XSPR_MASK, POWER10, 0, {RS}}, {"mfusprg0", XSPR(31,339,496), XSPR_MASK, POWER10, 0, {RS}},
{"mfuspgr1", XSPR(31,339,497), XSPR_MASK, POWER10, 0, {RS}}, {"mfusprg1", XSPR(31,339,497), XSPR_MASK, POWER10, 0, {RS}},
{"mfurmor", XSPR(31,339,505), XSPR_MASK, POWER10, 0, {RS}}, {"mfurmor", XSPR(31,339,505), XSPR_MASK, POWER10, 0, {RS}},
{"mfusrr0", XSPR(31,339,506), XSPR_MASK, POWER10, 0, {RS}}, {"mfusrr0", XSPR(31,339,506), XSPR_MASK, POWER10, 0, {RS}},
{"mfusrr1", XSPR(31,339,507), XSPR_MASK, POWER10, 0, {RS}}, {"mfusrr1", XSPR(31,339,507), XSPR_MASK, POWER10, 0, {RS}},
@ -7147,6 +7147,7 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}}, {"mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, 0, {RT}},
{"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}}, {"mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, 0, {RT}},
{"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}}, {"mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, 0, {RT}},
{"mfpir", XSPR(31,339,1023), XSPR_MASK, POWER10, 0, {RT}},
{"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}}, {"mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, 0, {RT}},
{"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}}, {"mfspr", X(31,339), X_MASK, COM, 0, {RT, SPR}},
@ -7444,8 +7445,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}}, {"mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, 0, {RS}},
{"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}}, {"mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, 0, {RS}},
{"mtptcr", XSPR(31,467,464), XSPR_MASK, POWER10, 0, {RS}}, {"mtptcr", XSPR(31,467,464), XSPR_MASK, POWER10, 0, {RS}},
{"mtuspgr0", XSPR(31,467,496), XSPR_MASK, POWER10, 0, {RS}}, {"mtusprg0", XSPR(31,467,496), XSPR_MASK, POWER10, 0, {RS}},
{"mtuspgr1", XSPR(31,467,497), XSPR_MASK, POWER10, 0, {RS}}, {"mtusprg1", XSPR(31,467,497), XSPR_MASK, POWER10, 0, {RS}},
{"mturmor", XSPR(31,467,505), XSPR_MASK, POWER10, 0, {RS}}, {"mturmor", XSPR(31,467,505), XSPR_MASK, POWER10, 0, {RS}},
{"mtusrr0", XSPR(31,467,506), XSPR_MASK, POWER10, 0, {RS}}, {"mtusrr0", XSPR(31,467,506), XSPR_MASK, POWER10, 0, {RS}},
{"mtusrr1", XSPR(31,467,507), XSPR_MASK, POWER10, 0, {RS}}, {"mtusrr1", XSPR(31,467,507), XSPR_MASK, POWER10, 0, {RS}},