aarch64: Fix MOVPRFX markup for bf16 conversions
bfcvt converts a .S input to a .H output, so any predicated movprfx needs to operate on .S rather than .H. In common with SVE2 narrowing top operations, bfcvtnt doesn't accept movprfx. 2020-01-31 Richard Sandiford <richard.sandiford@arm.com> opcodes/ * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt. Remove C_SCAN_MOVPRFX for SVE bfcvtnt. gas/ * testsuite/gas/aarch64/sve-bfloat-movprfx.s: Use .h rather than .s for the movprfx. * testsuite/gas/aarch64/sve-bfloat-movprfx.d: Update accordingly. * testsuite/gas/aarch64/sve-movprfx_28.d, * testsuite/gas/aarch64/sve-movprfx_28.l, * testsuite/gas/aarch64/sve-movprfx_28.s: New test.
This commit is contained in:
Richard Sandiford
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fd9faca826
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c3036ed063
@ -1,3 +1,12 @@
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2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
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* testsuite/gas/aarch64/sve-bfloat-movprfx.s: Use .h rather than
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.s for the movprfx.
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* testsuite/gas/aarch64/sve-bfloat-movprfx.d: Update accordingly.
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* testsuite/gas/aarch64/sve-movprfx_28.d,
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* testsuite/gas/aarch64/sve-movprfx_28.l,
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* testsuite/gas/aarch64/sve-movprfx_28.s: New test.
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2020-01-30 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (output_disp): Tighten base_opcode check.
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@ -23,5 +23,5 @@ Disassembly of section \.text:
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*[0-9a-f]+: 64e34440 bfmlalt z0\.s, z2\.h, z3\.h\[0\]
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*[0-9a-f]+: 0420bc20 movprfx z0, z1
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*[0-9a-f]+: 658aa040 bfcvt z0\.h, p0/m, z2\.s
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*[0-9a-f]+: 04512020 movprfx z0\.h, p0/m, z1\.h
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*[0-9a-f]+: 04912020 movprfx z0\.s, p0/m, z1\.s
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*[0-9a-f]+: 658aa040 bfcvt z0\.h, p0/m, z2\.s
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@ -27,5 +27,5 @@ movprfx z0, z1
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bfcvt z0.h, p0/m, z2.s
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# Predicated movprfx + bfcvt
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movprfx z0.h, p0/m, z1.h
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movprfx z0.s, p0/m, z1.s
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bfcvt z0.h, p0/m, z2.s
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31
gas/testsuite/gas/aarch64/sve-movprfx_28.d
Normal file
31
gas/testsuite/gas/aarch64/sve-movprfx_28.d
Normal file
@ -0,0 +1,31 @@
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#source: sve-movprfx_28.s
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#warning_output: sve-movprfx_28.l
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#as: -I$srcdir/$subdir --generate-missing-build-notes=no
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#objdump: -Dr -M notes
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.* file format .*
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Disassembly of section .*:
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0+ <.*>:
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[^:]+: 04912420 movprfx z0\.s, p1/m, z1\.s
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[^:]+: 658aa440 bfcvt z0\.h, p1/m, z2\.s
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[^:]+: 04902420 movprfx z0\.s, p1/z, z1\.s
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[^:]+: 658aa440 bfcvt z0\.h, p1/m, z2\.s
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[^:]+: 04512420 movprfx z0\.h, p1/m, z1\.h
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[^:]+: 658aa440 bfcvt z0\.h, p1/m, z2\.s // note: register size not compatible with previous `movprfx' at operand 1
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[^:]+: 04502420 movprfx z0\.h, p1/z, z1\.h
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[^:]+: 658aa440 bfcvt z0\.h, p1/m, z2\.s // note: register size not compatible with previous `movprfx' at operand 1
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[^:]+: 0420bc20 movprfx z0, z1
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[^:]+: 658aa440 bfcvt z0\.h, p1/m, z2\.s
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[^:]+: 0420bc20 movprfx z0, z1
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[^:]+: 648aa440 bfcvtnt z0\.h, p1/m, z2\.s // note: SVE `movprfx' compatible instruction expected
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[^:]+: 04912420 movprfx z0\.s, p1/m, z1\.s
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[^:]+: 648aa440 bfcvtnt z0\.h, p1/m, z2\.s // note: SVE `movprfx' compatible instruction expected
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[^:]+: 04902420 movprfx z0\.s, p1/z, z1\.s
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[^:]+: 648aa440 bfcvtnt z0\.h, p1/m, z2\.s // note: SVE `movprfx' compatible instruction expected
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[^:]+: 04512420 movprfx z0\.h, p1/m, z1\.h
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[^:]+: 648aa440 bfcvtnt z0\.h, p1/m, z2\.s // note: SVE `movprfx' compatible instruction expected
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[^:]+: 04502420 movprfx z0\.h, p1/z, z1\.h
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[^:]+: 648aa440 bfcvtnt z0\.h, p1/m, z2\.s // note: SVE `movprfx' compatible instruction expected
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[^:]+: d65f03c0 ret
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8
gas/testsuite/gas/aarch64/sve-movprfx_28.l
Normal file
8
gas/testsuite/gas/aarch64/sve-movprfx_28.l
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@ -0,0 +1,8 @@
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[^:]*: Assembler messages:
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.*:15: Warning: register size not compatible with previous `movprfx' at operand 1 -- `bfcvt z0.h,p1/m,z2.s'
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.*:19: Warning: register size not compatible with previous `movprfx' at operand 1 -- `bfcvt z0.h,p1/m,z2.s'
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.*:27: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
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.*:31: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
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.*:35: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
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.*:39: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
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.*:43: Warning: SVE `movprfx' compatible instruction expected -- `bfcvtnt z0.h,p1/m,z2.s'
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45
gas/testsuite/gas/aarch64/sve-movprfx_28.s
Normal file
45
gas/testsuite/gas/aarch64/sve-movprfx_28.s
Normal file
@ -0,0 +1,45 @@
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.text
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.arch armv8-a+sve+bf16
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f:
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// OK
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movprfx z0.s, p1/m, z1.s
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bfcvt z0.h, p1/m, z2.s
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// OK
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movprfx z0.s, p1/z, z1.s
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bfcvt z0.h, p1/m, z2.s
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// Wrong size
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movprfx z0.h, p1/m, z1.h
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bfcvt z0.h, p1/m, z2.s
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// Wrong size
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movprfx z0.h, p1/z, z1.h
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bfcvt z0.h, p1/m, z2.s
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// OK
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movprfx z0, z1
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bfcvt z0.h, p1/m, z2.s
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// Not prefixable
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movprfx z0, z1
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bfcvtnt z0.h, p1/m, z2.s
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// Not prefixable
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movprfx z0.s, p1/m, z1.s
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bfcvtnt z0.h, p1/m, z2.s
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// Not prefixable
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movprfx z0.s, p1/z, z1.s
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bfcvtnt z0.h, p1/m, z2.s
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// Not prefixable
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movprfx z0.h, p1/m, z1.h
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bfcvtnt z0.h, p1/m, z2.s
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// Not prefixable
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movprfx z0.h, p1/z, z1.h
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bfcvtnt z0.h, p1/m, z2.s
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ret
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@ -1,3 +1,8 @@
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2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
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* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
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Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
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2020-01-30 Alan Modra <amodra@gmail.com>
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* m32c-ibld.c: Regenerate.
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@ -5107,8 +5107,8 @@ struct aarch64_opcode aarch64_opcode_table[] =
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BFLOAT16_SVE_INSNC ("bfdot", 0x64608000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
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BFLOAT16_SVE_INSNC ("bfdot", 0x64604000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
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BFLOAT16_SVE_INSNC ("bfmmla", 0x6460e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
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BFLOAT16_SVE_INSNC ("bfcvt", 0x658aa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX, 0),
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BFLOAT16_SVE_INSNC ("bfcvtnt", 0x648aa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX, 0),
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BFLOAT16_SVE_INSNC ("bfcvt", 0x658aa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
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BFLOAT16_SVE_INSNC ("bfcvtnt", 0x648aa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, 0, 0),
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BFLOAT16_SVE_INSNC ("bfmlalt", 0x64e08400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
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BFLOAT16_SVE_INSNC ("bfmlalb", 0x64e08000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
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BFLOAT16_SVE_INSNC ("bfmlalt", 0x64e04400, 0xffe0f400, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
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