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Replace defines with those from intl/libgettext.h to quieten gcc warnings.

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This commit is contained in:
Nick Clifton 2000-05-30 18:35:35 +00:00
parent c1a72ffdd6
commit c1485d85e0
14 changed files with 3078 additions and 3246 deletions
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6
opcodes/ChangeLog
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@ -1,3 +1,9 @@
2000-05-30 Nick Clifton <nickc@cygnus.com>
* opintl.h (gettext, dgettext, dcgettext, textdomain,
bindtextdomain): Replace defines with those from intl/libgettext.h
to quieten gcc warnings.
2000-05-26 Alan Modra <alan@linuxcare.com.au> 2000-05-26 Alan Modra <alan@linuxcare.com.au>
* Makefile.am: Update dependencies with "make dep-am" * Makefile.am: Update dependencies with "make dep-am"

319
opcodes/configure vendored
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File diff suppressed because it is too large Load Diff

2
opcodes/disassemble.c
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@ -282,7 +282,7 @@ disassembler (abfd)
void void
disassembler_usage (stream) disassembler_usage (stream)
FILE *stream ATTRIBUTE_UNUSED; FILE * stream ATTRIBUTE_UNUSED;
{ {
#ifdef ARCH_arm #ifdef ARCH_arm
print_arm_disassembler_options (stream); print_arm_disassembler_options (stream);

4
opcodes/h8300-dis.c
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@ -165,11 +165,11 @@ bfd_h8_disassemble (addr, info, mode)
if (looking_for & DBIT) if (looking_for & DBIT)
{ {
if ((looking_for & 5) != (thisnib &5)) goto fail; if ((looking_for & 5) != (thisnib & 5)) goto fail;
abs = (thisnib & 0x8) ? 2 : 1; abs = (thisnib & 0x8) ? 2 : 1;
} }
else if (looking_for & (REG | IND|INC|DEC)) else if (looking_for & (REG | IND|INC|DEC))
{ {
if (looking_for & SRC) if (looking_for & SRC)
{ {

5813
opcodes/ia64-asmtab.c
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File diff suppressed because it is too large Load Diff

7
opcodes/ia64-gen.c
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@ -800,8 +800,8 @@ irf_operand (int op, const char *field)
if (!field) if (!field)
{ {
return op == IA64_OPND_RR_R3 || op == IA64_OPND_DBR_R3 return op == IA64_OPND_RR_R3 || op == IA64_OPND_DBR_R3
|| op == IA64_OPND_IBR_R3 || op == IA64_OPND_PKR_R3 || op == IA64_OPND_IBR_R3 || op == IA64_OPND_PKR_R3
|| op == IA64_OPND_PMC_R3 || op == IA64_OPND_PMD_R3 || op == IA64_OPND_PMC_R3 || op == IA64_OPND_PMD_R3
|| op == IA64_OPND_MSR_R3 || op == IA64_OPND_CPUID_R3; || op == IA64_OPND_MSR_R3 || op == IA64_OPND_CPUID_R3;
} }
else else
@ -1710,6 +1710,7 @@ add_dis_entry (first, opcode, mask, opcodenum, ent, completer_index)
{ {
abort (); abort ();
} }
while (ent != NULL) while (ent != NULL)
{ {
ia64_insn newopcode = (opcode & (~ ent->mask)) | ent->bits; ia64_insn newopcode = (opcode & (~ ent->mask)) | ent->bits;
@ -2550,7 +2551,6 @@ insert_completer_entry (opc, tabent, order)
(*ptr)->is_terminal = 1; (*ptr)->is_terminal = 1;
(*ptr)->mask = (ia64_insn)-1; (*ptr)->mask = (ia64_insn)-1;
(*ptr)->bits = opc->opcode; (*ptr)->bits = opc->opcode;
(*ptr)->dependencies = insert_opcode_dependencies (opc, *ptr); (*ptr)->dependencies = insert_opcode_dependencies (opc, *ptr);
(*ptr)->order = order; (*ptr)->order = order;
} }
@ -2684,6 +2684,7 @@ add_opcode_entry (opc)
} }
ordered_table[otlen++] = nent; ordered_table[otlen++] = nent;
} }
insert_completer_entry (opc, *place, opcode_count++); insert_completer_entry (opc, *place, opcode_count++);
} }

2
opcodes/m10300-dis.c
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@ -1,5 +1,5 @@
/* Disassemble MN10300 instructions. /* Disassemble MN10300 instructions.
Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. Copyright (C) 1996, 1997, 1998, 2000 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by it under the terms of the GNU General Public License as published by

6
opcodes/mcore-dis.c
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@ -169,7 +169,7 @@ print_insn_mcore (memaddr, info)
if (strcmp (op->name, "bsr") == 0) if (strcmp (op->name, "bsr") == 0)
{ {
/* for bsr, we'll try to get a symbol for the target */ /* For bsr, we'll try to get a symbol for the target. */
val = memaddr + 2 + (val << 1); val = memaddr + 2 + (val << 1);
if (info->print_address_func && val != 0) if (info->print_address_func && val != 0)
@ -268,12 +268,12 @@ print_insn_mcore (memaddr, info)
break; break;
default: default:
/* if the disassembler lags the instruction set */ /* If the disassembler lags the instruction set. */
fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst); fprintf (stream, "\tundecoded operands, inst is 0x%04x", inst);
break; break;
} }
} }
/* Say how many bytes we consumed? */ /* Say how many bytes we consumed. */
return 2; return 2;
} }

72
opcodes/mips-opc.c
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@ -155,9 +155,9 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, I1 }, {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, I1 },
{"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, I2|T3 }, {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, I2|T3 },
{"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, I1 }, {"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, I1 },
{"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, I4 }, {"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, I4|M1 },
{"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 }, {"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, I2|T3 },
{"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, I4 }, {"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, I4|M1 },
{"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, I1 }, {"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, I1 },
{"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, I2|T3 }, {"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, I2|T3 },
{"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, I1 }, {"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, I1 },
@ -222,99 +222,99 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"break", "c", 0x0000000d, 0xfc00ffff, TRAP, I1 }, {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, I1 },
{"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, I1 }, {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, I1 },
{"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
{"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
{"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
{"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
{"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
{"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
{"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
{"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
{"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
{"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
{"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
{"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
{"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
{"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
{"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
{"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
{"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
{"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
{"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
{"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
{"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
{"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
{"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
{"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
{"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
{"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
{"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
{"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
{"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
{"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
{"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
{"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
{"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
{"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
{"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
{"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
{"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
{"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
{"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
{"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
{"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
{"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, {"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
{"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, {"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
{"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, {"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
{"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
{"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
{"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
{"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
{"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
{"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
{"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
{"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
{"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
{"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
{"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
{"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
{"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
{"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
{"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
{"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
{"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 }, {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I1 },
{"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4 }, {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I4|M1 },
{"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 }, {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, I1 },
{"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4 }, {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, I4|M1 },
{"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 }, {"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, I5 },
{"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|T3|M1 }, {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, I3|T3|M1 },
@ -539,8 +539,8 @@ const struct mips_opcode mips_builtin_opcodes[] = {
{"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1}, {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HI|WR_LO|WR_d|IS_M, G1},
{"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, V1 }, {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|WR_HI|WR_LO|RD_HI|RD_LO, V1 },
{"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 }, {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, I1 },
{"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1},
{"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1 }, {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, I1},
{"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 }, {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, I1 },
{"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 }, {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, I1 },
{"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 }, {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, I1 },

13
opcodes/opintl.h
View File

@ -12,19 +12,18 @@
#ifdef ENABLE_NLS #ifdef ENABLE_NLS
# include <libintl.h> # include <libintl.h>
# define _(String) dgettext (PACKAGE, String) # define _(String) gettext (String)
# ifdef gettext_noop # ifdef gettext_noop
# define N_(String) gettext_noop (String) # define N_(String) gettext_noop (String)
# else # else
# define N_(String) (String) # define N_(String) (String)
# endif # endif
#else #else
/* Stubs that do something close enough. */ # define gettext(Msgid) (Msgid)
# define textdomain(String) (String) # define dgettext(Domainname, Msgid) (Msgid)
# define gettext(String) (String) # define dcgettext(Domainname, Msgid, Category) (Msgid)
# define dgettext(Domain,Message) (Message) # define textdomain(Domainname) while (0) /* nothing */
# define dcgettext(Domain,Message,Type) (Message) # define bindtextdomain(Domainname, Dirname) while (0) /* nothing */
# define bindtextdomain(Domain,Directory) (Domain)
# define _(String) (String) # define _(String) (String)
# define N_(String) (String) # define N_(String) (String)
#endif #endif

21
opcodes/po/POTFILES.in
View File

@ -5,6 +5,7 @@ arc-dis.c
arc-opc.c arc-opc.c
arm-dis.c arm-dis.c
arm-opc.h arm-opc.h
avr-dis.c
cgen-asm.c cgen-asm.c
cgen-dis.c cgen-dis.c
cgen-opc.c cgen-opc.c
@ -12,8 +13,8 @@ d10v-dis.c
d10v-opc.c d10v-opc.c
d30v-dis.c d30v-dis.c
d30v-opc.c d30v-opc.c
dis-buf.c
disassemble.c disassemble.c
dis-buf.c
fr30-asm.c fr30-asm.c
fr30-desc.c fr30-desc.c
fr30-desc.h fr30-desc.h
@ -29,6 +30,18 @@ i370-dis.c
i370-opc.c i370-opc.c
i386-dis.c i386-dis.c
i960-dis.c i960-dis.c
ia64-asmtab.c
ia64-asmtab.h
ia64-dis.c
ia64-gen.c
ia64-opc-a.c
ia64-opc-b.c
ia64-opc.c
ia64-opc-d.c
ia64-opc-f.c
ia64-opc.h
ia64-opc-i.c
ia64-opc-m.c
m10200-dis.c m10200-dis.c
m10200-opc.c m10200-opc.c
m10300-dis.c m10300-dis.c
@ -46,9 +59,9 @@ m68k-opc.c
m88k-dis.c m88k-dis.c
mcore-dis.c mcore-dis.c
mcore-opc.h mcore-opc.h
mips16-opc.c
mips-dis.c mips-dis.c
mips-opc.c mips-opc.c
mips16-opc.c
ns32k-dis.c ns32k-dis.c
pj-dis.c pj-dis.c
pj-opc.c pj-opc.c
@ -60,6 +73,8 @@ sparc-dis.c
sparc-opc.c sparc-opc.c
sysdep.h sysdep.h
tic30-dis.c tic30-dis.c
tic54x-dis.c
tic54x-opc.c
tic80-dis.c tic80-dis.c
tic80-opc.c tic80-opc.c
v850-dis.c v850-dis.c
@ -68,5 +83,5 @@ vax-dis.c
w65-dis.c w65-dis.c
w65-opc.h w65-opc.h
z8k-dis.c z8k-dis.c
z8k-opc.h
z8kgen.c z8kgen.c
z8k-opc.h

54
opcodes/po/opcodes.pot
View File

@ -6,7 +6,7 @@
msgid "" msgid ""
msgstr "" msgstr ""
"Project-Id-Version: PACKAGE VERSION\n" "Project-Id-Version: PACKAGE VERSION\n"
"POT-Creation-Date: 2000-04-04 23:21+0930\n" "POT-Creation-Date: 2000-05-30 11:33-0700\n"
"PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n"
"Last-Translator: FULL NAME <EMAIL@ADDRESS>\n" "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n"
"Language-Team: LANGUAGE <LL@li.org>\n" "Language-Team: LANGUAGE <LL@li.org>\n"
@ -22,7 +22,7 @@ msgstr ""
msgid "jump hint unaligned" msgid "jump hint unaligned"
msgstr "" msgstr ""
#: arc-dis.c:231 #: arc-dis.c:232
msgid "*unknown*" msgid "*unknown*"
msgstr "" msgstr ""
@ -48,21 +48,21 @@ msgstr ""
msgid "branch address not on 4 byte boundary" msgid "branch address not on 4 byte boundary"
msgstr "" msgstr ""
#: arm-dis.c:470 #: arm-dis.c:476
msgid "<illegal precision>" msgid "<illegal precision>"
msgstr "" msgstr ""
#: arm-dis.c:882 #: arm-dis.c:888
#, c-format #, c-format
msgid "Unrecognised register name set: %s\n" msgid "Unrecognised register name set: %s\n"
msgstr "" msgstr ""
#: arm-dis.c:889 #: arm-dis.c:895
#, c-format #, c-format
msgid "Unrecognised disassembler option: %s\n" msgid "Unrecognised disassembler option: %s\n"
msgstr "" msgstr ""
#: arm-dis.c:1053 #: arm-dis.c:1059
msgid "" msgid ""
"\n" "\n"
"The following ARM specific disassembler options are supported for use with\n" "The following ARM specific disassembler options are supported for use with\n"
@ -83,7 +83,7 @@ msgstr ""
msgid "operand out of range (%lu not between %lu and %lu)" msgid "operand out of range (%lu not between %lu and %lu)"
msgstr "" msgstr ""
#: d30v-dis.c:305 #: d30v-dis.c:306
#, c-format #, c-format
msgid "<unknown register %d>" msgid "<unknown register %d>"
msgstr "" msgstr ""
@ -171,23 +171,23 @@ msgstr ""
msgid "Unrecognized field %d while setting vma operand.\n" msgid "Unrecognized field %d while setting vma operand.\n"
msgstr "" msgstr ""
#: h8300-dis.c:404 #: h8300-dis.c:405
#, c-format #, c-format
msgid "Hmmmm %x" msgid "Hmmmm %x"
msgstr "" msgstr ""
#: h8300-dis.c:416 #: h8300-dis.c:417
#, c-format #, c-format
msgid "Don't understand %x \n" msgid "Don't understand %x \n"
msgstr "" msgstr ""
#: h8500-dis.c:139 #: h8500-dis.c:140
#, c-format #, c-format
msgid "can't cope with insert %d\n" msgid "can't cope with insert %d\n"
msgstr "" msgstr ""
#. Couldn't understand anything #. Couldn't understand anything
#: h8500-dis.c:344 #: h8500-dis.c:345
#, c-format #, c-format
msgid "%02x\t\t*unknown*" msgid "%02x\t\t*unknown*"
msgstr "" msgstr ""
@ -202,27 +202,27 @@ msgstr ""
msgid "unknown\t0x%04lx" msgid "unknown\t0x%04lx"
msgstr "" msgstr ""
#: m10300-dis.c:680 #: m10300-dis.c:685
#, c-format #, c-format
msgid "unknown\t0x%04x" msgid "unknown\t0x%04x"
msgstr "" msgstr ""
#: m68k-dis.c:410 #: m68k-dis.c:412
#, c-format #, c-format
msgid "<internal error in opcode table: %s %s>\n" msgid "<internal error in opcode table: %s %s>\n"
msgstr "" msgstr ""
#: m68k-dis.c:988 #: m68k-dis.c:990
#, c-format #, c-format
msgid "<function code %d>" msgid "<function code %d>"
msgstr "" msgstr ""
#: m88k-dis.c:273 #: m88k-dis.c:274
#, c-format #, c-format
msgid "# <dis error: %08x>" msgid "# <dis error: %08x>"
msgstr "" msgstr ""
#: mips-dis.c:237 #: mips-dis.c:242
#, c-format #, c-format
msgid "# internal error, undefined modifier(%c)" msgid "# internal error, undefined modifier(%c)"
msgstr "" msgstr ""
@ -237,50 +237,50 @@ msgstr ""
msgid "$<undefined>" msgid "$<undefined>"
msgstr "" msgstr ""
#: ppc-opc.c:586 ppc-opc.c:617 #: ppc-opc.c:619 ppc-opc.c:650
msgid "invalid conditional option" msgid "invalid conditional option"
msgstr "" msgstr ""
#: ppc-opc.c:619 #: ppc-opc.c:652
msgid "attempt to set y bit when using + or - modifier" msgid "attempt to set y bit when using + or - modifier"
msgstr "" msgstr ""
#: ppc-opc.c:674 #: ppc-opc.c:707
msgid "ignoring least significant bits in branch offset" msgid "ignoring least significant bits in branch offset"
msgstr "" msgstr ""
#: ppc-opc.c:709 ppc-opc.c:746 #: ppc-opc.c:742 ppc-opc.c:779
msgid "illegal bitmask" msgid "illegal bitmask"
msgstr "" msgstr ""
#: ppc-opc.c:815 #: ppc-opc.c:848
msgid "value out of range" msgid "value out of range"
msgstr "" msgstr ""
#: ppc-opc.c:889 #: ppc-opc.c:922
msgid "index register in load range" msgid "index register in load range"
msgstr "" msgstr ""
#: ppc-opc.c:904 #: ppc-opc.c:937
msgid "invalid register operand when updating" msgid "invalid register operand when updating"
msgstr "" msgstr ""
#. Mark as non-valid instruction #. Mark as non-valid instruction
#: sparc-dis.c:744 #: sparc-dis.c:743
msgid "unknown" msgid "unknown"
msgstr "" msgstr ""
#: sparc-dis.c:816 #: sparc-dis.c:815
#, c-format #, c-format
msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
msgstr "" msgstr ""
#: sparc-dis.c:827 #: sparc-dis.c:826
#, c-format #, c-format
msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"
msgstr "" msgstr ""
#: sparc-dis.c:876 #: sparc-dis.c:875
#, c-format #, c-format
msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"
msgstr "" msgstr ""

2
opcodes/tic54x-dis.c
View File

@ -20,7 +20,7 @@
#include <errno.h> #include <errno.h>
#include <math.h> #include <math.h>
#include <stdlib.h> #include <stdlib.h>
#include <string.h> #include "sysdep.h"
#include "dis-asm.h" #include "dis-asm.h"
#include "opcode/tic54x.h" #include "opcode/tic54x.h"
#include "coff/tic54x.h" #include "coff/tic54x.h"

3
opcodes/tic54x-opc.c
View File

@ -17,8 +17,7 @@
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */ 02111-1307, USA. */
#include <stdio.h> #include "sysdep.h"
#include "ansidecl.h"
#include "opcode/tic54x.h" #include "opcode/tic54x.h"
/* these are the only register names not found in mmregs */ /* these are the only register names not found in mmregs */