diff --git a/gdb/ChangeLog b/gdb/ChangeLog
index ba1300d57e..f8120db4c7 100644
--- a/gdb/ChangeLog
+++ b/gdb/ChangeLog
@@ -1,3 +1,9 @@
+2019-04-17  Jim Wilson  <jimw@sifive.com>
+	    Andrew Burgess  <andrew.burgess@embecosm.com>
+
+	* riscv-tdep.c (riscv_breakpoint_kind_from_pc): Hanndle case where
+	code read might fail, assume 4-byte breakpoint in that case.
+
 2019-04-15  Leszek Swirski  <leszeks@google.com>
 
 	* amd64-tdep.c (amd64_classify_aggregate): Use cp_pass_by_reference
diff --git a/gdb/riscv-tdep.c b/gdb/riscv-tdep.c
index 6370bc268f..4fe07ef437 100644
--- a/gdb/riscv-tdep.c
+++ b/gdb/riscv-tdep.c
@@ -430,7 +430,15 @@ riscv_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
 	unaligned_p = true;
       else
 	{
-	  /* Read the opcode byte to determine the instruction length.  */
+	  /* Read the opcode byte to determine the instruction length.  If
+	     the read fails this may be because we tried to set the
+	     breakpoint at an invalid address, in this case we provide a
+	     fake result which will give a breakpoint length of 4.
+	     Hopefully when we try to actually insert the breakpoint we
+	     will see a failure then too which will be reported to the
+	     user.  */
+	  if (target_read_code (*pcptr, buf, 1) == -1)
+	    buf[0] = 0;
 	  read_code (*pcptr, buf, 1);
 	}