PR24704, Internal error building skiboot for powerpc64-linux-gnu
While the skiboot linker script bears some culpability in this PR, it's also true that the GOT indirect to GOT relative optimisation for 16-bit offsets isn't safe. At least, it isn't safe to remove the GOT entry based on distance between the GOT pointer and symbol calculated from the preliminary layout. So this patch removes that optimisation, and reduces the range allowed for 32-bit and 34-bit offsets. PR 24704 bfd/ * elf64-ppc.c (R_PPC64_GOT16_DS): Don't set has_gotrel. (ppc64_elf_edit_toc): Don't remove R_PPC64_GOT16_DS got entries. Reduce range of offsets allowed for other GOT relocs. ld/ * testsuite/ld-powerpc/elfv2exe.d: Update. * testsuite/ld-powerpc/elfv2so.d: Update.
This commit is contained in:
Alan Modra
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@ -1,3 +1,10 @@
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2019-06-23 Alan Modra <amodra@gmail.com>
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PR 24704
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* elf64-ppc.c (R_PPC64_GOT16_DS): Don't set has_gotrel.
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(ppc64_elf_edit_toc): Don't remove R_PPC64_GOT16_DS got entries.
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Reduce range of offsets allowed for other GOT relocs.
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2019-06-23 Alan Modra <amodra@gmail.com>
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PR 24689
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@ -4610,7 +4610,6 @@ ppc64_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
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sec->has_tls_reloc = 1;
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goto dogot;
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case R_PPC64_GOT16_DS:
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case R_PPC64_GOT16_HA:
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case R_PPC64_GOT16_LO_DS:
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case R_PPC64_GOT_PCREL34:
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@ -4618,6 +4617,7 @@ ppc64_elf_check_relocs (bfd *abfd, struct bfd_link_info *info,
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ppc64_elf_section_data (sec)->has_gotrel = 1;
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/* Fall through. */
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case R_PPC64_GOT16_DS:
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case R_PPC64_GOT16:
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case R_PPC64_GOT16_HI:
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case R_PPC64_GOT16_LO:
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@ -9010,10 +9010,15 @@ ppc64_elf_edit_toc (struct bfd_link_info *info)
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r_type = ELF64_R_TYPE (rel->r_info);
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switch (r_type)
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{
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/* Note that we don't delete GOT entries for
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R_PPC64_GOT16_DS since we'd need a lot more
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analysis. For starters, the preliminary layout is
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before the GOT, PLT, dynamic sections and stubs are
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laid out. Then we'd need to allow for changes in
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distance between sections caused by alignment. */
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default:
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continue;
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case R_PPC64_GOT16_DS:
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case R_PPC64_GOT16_HA:
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case R_PPC64_GOT16_LO_DS:
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sym_addend = rel->r_addend;
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@ -9039,24 +9044,18 @@ ppc64_elf_edit_toc (struct bfd_link_info *info)
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val += sym_addend;
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val += sym_sec->output_section->vma + sym_sec->output_offset;
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/* Fudge factor to allow for the fact that the preliminary layout
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isn't exact. Reduce limits by this factor. */
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#define LIMIT_ADJUST(LIMIT) ((LIMIT) - (LIMIT) / 16)
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switch (r_type)
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{
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default:
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continue;
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case R_PPC64_GOT16_DS:
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if (val - got + 0x8000 >= 0x10000)
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continue;
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if (!bfd_get_section_contents (ibfd, sec, buf,
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rel->r_offset & ~3, 4))
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goto got_error_ret;
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insn = bfd_get_32 (ibfd, buf);
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if ((insn & (0x3f << 26 | 0x3)) != 58u << 26 /* ld */)
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continue;
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break;
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case R_PPC64_GOT16_HA:
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if (val - got + 0x80008000ULL >= 0x100000000ULL)
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if (val - got + LIMIT_ADJUST (0x80008000ULL)
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>= LIMIT_ADJUST (0x100000000ULL))
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continue;
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if (!bfd_get_section_contents (ibfd, sec, buf,
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@ -9069,7 +9068,8 @@ ppc64_elf_edit_toc (struct bfd_link_info *info)
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break;
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case R_PPC64_GOT16_LO_DS:
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if (val - got + 0x80008000ULL >= 0x100000000ULL)
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if (val - got + LIMIT_ADJUST (0x80008000ULL)
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>= LIMIT_ADJUST (0x100000000ULL))
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continue;
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if (!bfd_get_section_contents (ibfd, sec, buf,
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rel->r_offset & ~3, 4))
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@ -9082,7 +9082,8 @@ ppc64_elf_edit_toc (struct bfd_link_info *info)
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case R_PPC64_GOT_PCREL34:
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pc = rel->r_offset;
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pc += sec->output_section->vma + sec->output_offset;
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if (val - pc + (1ULL << 33) >= 1ULL << 34)
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if (val - pc + LIMIT_ADJUST (1ULL << 33)
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>= LIMIT_ADJUST (1ULL << 34))
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continue;
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if (!bfd_get_section_contents (ibfd, sec, buf,
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rel->r_offset & ~3, 8))
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@ -9095,6 +9096,7 @@ ppc64_elf_edit_toc (struct bfd_link_info *info)
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continue;
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break;
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}
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#undef LIMIT_ADJUST
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if (h != NULL)
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ent = h->got.glist;
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@ -1,3 +1,9 @@
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2019-06-23 Alan Modra <amodra@gmail.com>
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PR 24704
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* testsuite/ld-powerpc/elfv2exe.d: Update.
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* testsuite/ld-powerpc/elfv2so.d: Update.
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2019-06-14 Szabolcs Nagy <szabolcs.nagy@arm.com>
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* testsuite/ld-aarch64/aarch64-elf.exp: Add emit-relocs-22 and -23.
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@ -34,7 +34,7 @@ Disassembly of section \.text:
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.*: (e8 62 80 08|08 80 62 e8) ld r3,-32760\(r2\)
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.*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_branch\.f2>
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (38 62 80 10|10 80 62 38) addi r3,r2,-32752
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.*: (38 62 80 18|18 80 62 38) addi r3,r2,-32744
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.*: (48 .. .. ..|.. .. .. 48) bl 10008888 <f3>
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.*: (60 00 00 00|00 00 00 60) nop
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.*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_branch\.f4>
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@ -9,35 +9,35 @@ Disassembly of section \.text:
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.* <.*\.plt_call\.f4>:
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.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
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.*: (e9 82 80 38|38 80 82 e9) ld r12,-32712\(r2\)
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.*: (e9 82 80 40|40 80 82 e9) ld r12,-32704\(r2\)
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (4e 80 04 20|20 04 80 4e) bctr
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\.\.\.
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.* <.*\.plt_call\.f3>:
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.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
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.*: (e9 82 80 28|28 80 82 e9) ld r12,-32728\(r2\)
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.*: (e9 82 80 30|30 80 82 e9) ld r12,-32720\(r2\)
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (4e 80 04 20|20 04 80 4e) bctr
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\.\.\.
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.* <.*\.plt_call\.f5>:
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.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
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.*: (e9 82 80 20|20 80 82 e9) ld r12,-32736\(r2\)
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.*: (e9 82 80 28|28 80 82 e9) ld r12,-32728\(r2\)
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (4e 80 04 20|20 04 80 4e) bctr
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\.\.\.
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.* <.*\.plt_call\.f1>:
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.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
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.*: (e9 82 80 40|40 80 82 e9) ld r12,-32704\(r2\)
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.*: (e9 82 80 48|48 80 82 e9) ld r12,-32696\(r2\)
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (4e 80 04 20|20 04 80 4e) bctr
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\.\.\.
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.* <.*\.plt_call\.f2>:
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.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
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.*: (e9 82 80 30|30 80 82 e9) ld r12,-32720\(r2\)
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.*: (e9 82 80 38|38 80 82 e9) ld r12,-32712\(r2\)
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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.*: (4e 80 04 20|20 04 80 4e) bctr
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\.\.\.
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@ -52,7 +52,7 @@ Disassembly of section \.text:
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.*: (e8 62 80 08|08 80 62 e8) ld r3,-32760\(r2\)
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.*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_call\.f2>
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.*: (e8 41 00 18|18 00 41 e8) ld r2,24\(r1\)
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.*: (38 62 80 48|48 80 62 38) addi r3,r2,-32696
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.*: (38 62 80 50|50 80 62 38) addi r3,r2,-32688
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.*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_call\.f3>
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.*: (e8 41 00 18|18 00 41 e8) ld r2,24\(r1\)
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.*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_call\.f4>
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