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ubsan: frv: left shift of negative value

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More non-bugs flagged by ubsan, unless you happen to be compiling for
a 1's complement host.

cpu/
	* frv.cpu (f-u12): Multiply rather than left shift signed values.
	(f-label16, f-label24): Likewise.
opcodes/
	* frv-ibld.c: Regenerate.
This commit is contained in:
Alan Modra 2020-02-01 13:08:43 +10:30
parent aa66aac47b
commit b2b1453ad4
4 changed files with 16 additions and 7 deletions
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5
cpu/ChangeLog
View File

@ -1,3 +1,8 @@
2020-02-01 Alan Modra <amodra@gmail.com>
* frv.cpu (f-u12): Multiply rather than left shift signed values.
(f-label16, f-label24): Likewise.
2020-01-30 Alan Modra <amodra@gmail.com>
* m32c.cpu (f-src32-rn-unprefixed-QI): Shift before inverting.

8
cpu/frv.cpu
View File

@ -1984,7 +1984,7 @@
(set (ifield f-u12-l) (and (ifield f-u12) #x3f))
)
(sequence () ; extract
(set (ifield f-u12) (or (sll (ifield f-u12-h) 6)
(set (ifield f-u12) (or (mul (ifield f-u12-h) 64)
(ifield f-u12-l)))
)
)
@ -2016,7 +2016,7 @@
(df f-label16 "18 bit pc relative signed offset" (PCREL-ADDR) 15 16 INT
((value pc) (sra WI (sub WI value pc) (const 2)))
((value pc) (add WI (sll WI value (const 2)) pc))
((value pc) (add WI (mul WI value (const 4)) pc))
)
(df f-labelH6 "upper 6 bits of label24" () 30 6 INT #f #f)
@ -2034,9 +2034,9 @@
; extract
(sequence ()
(set (ifield f-label24)
(add (sll (or (sll (ifield f-labelH6) (const 18))
(add (mul (or (mul (ifield f-labelH6) (sll 1 18))
(ifield f-labelL18))
(const 2))
(const 4))
pc)))
)

4
opcodes/ChangeLog
View File

@ -1,3 +1,7 @@
2020-02-01 Alan Modra <amodra@gmail.com>
* frv-ibld.c: Regenerate.
2020-01-31 Jan Beulich <jbeulich@suse.com>
* i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.

6
opcodes/frv-ibld.c
View File

@ -1090,7 +1090,7 @@ frv_cgen_extract_operand (CGEN_CPU_DESC cd,
{
long value;
length = extract_normal (cd, ex_info, insn_value, 0|(1<<CGEN_IFLD_SIGNED)|(1<<CGEN_IFLD_PCREL_ADDR), 0, 15, 16, 32, total_length, pc, & value);
value = ((((value) << (2))) + (pc));
value = ((((value) * (4))) + (pc));
fields->f_label16 = value;
}
break;
@ -1101,7 +1101,7 @@ frv_cgen_extract_operand (CGEN_CPU_DESC cd,
length = extract_normal (cd, ex_info, insn_value, 0, 0, 17, 18, 32, total_length, pc, & fields->f_labelL18);
if (length <= 0) break;
{
FLD (f_label24) = ((((((((FLD (f_labelH6)) << (18))) | (FLD (f_labelL18)))) << (2))) + (pc));
FLD (f_label24) = ((((((((FLD (f_labelH6)) * (((1) << (18))))) | (FLD (f_labelL18)))) * (4))) + (pc));
}
}
break;
@ -1156,7 +1156,7 @@ frv_cgen_extract_operand (CGEN_CPU_DESC cd,
length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 6, 32, total_length, pc, & fields->f_u12_l);
if (length <= 0) break;
{
FLD (f_u12) = ((((FLD (f_u12_h)) << (6))) | (FLD (f_u12_l)));
FLD (f_u12) = ((((FLD (f_u12_h)) * (64))) | (FLD (f_u12_l)));
}
}
break;