2005-11-02 H.J. Lu <hongjiu.lu@intel.com>
* iq2000-desc.c: Regenerated. * iq2000-desc.h: Likewise. * iq2000-dis.c: Likewise. * iq2000-opc.c: Likewise.
This commit is contained in:
H.J. Lu
parent
36b0c57df5
commit
a92e0d0a05
@ -1,3 +1,10 @@
|
||||
2005-11-02 H.J. Lu <hongjiu.lu@intel.com>
|
||||
|
||||
* iq2000-desc.c: Regenerated.
|
||||
* iq2000-desc.h: Likewise.
|
||||
* iq2000-dis.c: Likewise.
|
||||
* iq2000-opc.c: Likewise.
|
||||
|
||||
2005-11-02 Paul Brook <paul@codesourcery.com>
|
||||
|
||||
* arm-dis.c (print_insn_thumb32): Word align blx target address.
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -25,6 +25,8 @@ with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
#ifndef IQ2000_CPU_H
|
||||
#define IQ2000_CPU_H
|
||||
|
||||
#include "opcode/cgen-bitset.h"
|
||||
|
||||
#define CGEN_ARCH iq2000
|
||||
|
||||
/* Given symbol S, return iq2000_cgen_<S>. */
|
||||
@ -200,6 +202,15 @@ typedef enum cgen_ifld_attr {
|
||||
/* Number of non-boolean elements in cgen_ifld_attr. */
|
||||
#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
|
||||
|
||||
/* cgen_ifld attribute accessor macros. */
|
||||
#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset)
|
||||
#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0)
|
||||
#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0)
|
||||
#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0)
|
||||
#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0)
|
||||
#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0)
|
||||
#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0)
|
||||
|
||||
/* Enum declaration for iq2000 ifield types. */
|
||||
typedef enum ifield_type {
|
||||
IQ2000_F_NIL, IQ2000_F_ANYOF, IQ2000_F_OPCODE, IQ2000_F_RS
|
||||
@ -227,6 +238,13 @@ typedef enum cgen_hw_attr {
|
||||
/* Number of non-boolean elements in cgen_hw_attr. */
|
||||
#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
|
||||
|
||||
/* cgen_hw attribute accessor macros. */
|
||||
#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset)
|
||||
#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0)
|
||||
#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0)
|
||||
#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0)
|
||||
#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0)
|
||||
|
||||
/* Enum declaration for iq2000 hardware types. */
|
||||
typedef enum cgen_hw_type {
|
||||
HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
|
||||
@ -247,6 +265,17 @@ typedef enum cgen_operand_attr {
|
||||
/* Number of non-boolean elements in cgen_operand_attr. */
|
||||
#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
|
||||
|
||||
/* cgen_operand attribute accessor macros. */
|
||||
#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset)
|
||||
#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0)
|
||||
#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0)
|
||||
#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0)
|
||||
#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0)
|
||||
#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0)
|
||||
#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0)
|
||||
#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0)
|
||||
#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0)
|
||||
|
||||
/* Enum declaration for iq2000 operand types. */
|
||||
typedef enum cgen_operand_type {
|
||||
IQ2000_OPERAND_PC, IQ2000_OPERAND_RS, IQ2000_OPERAND_RT, IQ2000_OPERAND_RD
|
||||
@ -281,6 +310,27 @@ typedef enum cgen_insn_attr {
|
||||
/* Number of non-boolean elements in cgen_insn_attr. */
|
||||
#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
|
||||
|
||||
/* cgen_insn attribute accessor macros. */
|
||||
#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
|
||||
#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_YIELD_INSN_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_YIELD_INSN)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_LOAD_DELAY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_LOAD_DELAY)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_EVEN_REG_NUM_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_EVEN_REG_NUM)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_UNSUPPORTED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNSUPPORTED)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_USES_RD_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_RD)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_USES_RS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_RS)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_USES_RT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_RT)) != 0)
|
||||
#define CGEN_ATTR_CGEN_INSN_USES_R31_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_USES_R31)) != 0)
|
||||
|
||||
/* cgen.h uses things we just defined. */
|
||||
#include "opcode/cgen.h"
|
||||
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
THIS FILE IS MACHINE GENERATED WITH CGEN.
|
||||
- the resultant file is machine generated, cgen-dis.in isn't
|
||||
|
||||
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2005
|
||||
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005
|
||||
Free Software Foundation, Inc.
|
||||
|
||||
This file is part of the GNU Binutils and GDB, the GNU debugger.
|
||||
@ -497,7 +497,7 @@ default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
|
||||
typedef struct cpu_desc_list
|
||||
{
|
||||
struct cpu_desc_list *next;
|
||||
int isa;
|
||||
CGEN_BITSET *isa;
|
||||
int mach;
|
||||
int endian;
|
||||
CGEN_CPU_DESC cd;
|
||||
@ -509,11 +509,12 @@ print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
|
||||
static cpu_desc_list *cd_list = 0;
|
||||
cpu_desc_list *cl = 0;
|
||||
static CGEN_CPU_DESC cd = 0;
|
||||
static int prev_isa;
|
||||
static CGEN_BITSET *prev_isa;
|
||||
static int prev_mach;
|
||||
static int prev_endian;
|
||||
int length;
|
||||
int isa,mach;
|
||||
CGEN_BITSET *isa;
|
||||
int mach;
|
||||
int endian = (info->endian == BFD_ENDIAN_BIG
|
||||
? CGEN_ENDIAN_BIG
|
||||
: CGEN_ENDIAN_LITTLE);
|
||||
@ -536,25 +537,34 @@ print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
|
||||
#endif
|
||||
|
||||
#ifdef CGEN_COMPUTE_ISA
|
||||
isa = CGEN_COMPUTE_ISA (info);
|
||||
{
|
||||
static CGEN_BITSET *permanent_isa;
|
||||
|
||||
if (!permanent_isa)
|
||||
permanent_isa = cgen_bitset_create (MAX_ISAS);
|
||||
isa = permanent_isa;
|
||||
cgen_bitset_clear (isa);
|
||||
cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
|
||||
}
|
||||
#else
|
||||
isa = info->insn_sets;
|
||||
#endif
|
||||
|
||||
/* If we've switched cpu's, try to find a handle we've used before */
|
||||
if (cd
|
||||
&& (isa != prev_isa
|
||||
&& (cgen_bitset_compare (isa, prev_isa) != 0
|
||||
|| mach != prev_mach
|
||||
|| endian != prev_endian))
|
||||
{
|
||||
cd = 0;
|
||||
for (cl = cd_list; cl; cl = cl->next)
|
||||
{
|
||||
if (cl->isa == isa &&
|
||||
if (cgen_bitset_compare (cl->isa, isa) == 0 &&
|
||||
cl->mach == mach &&
|
||||
cl->endian == endian)
|
||||
{
|
||||
cd = cl->cd;
|
||||
prev_isa = cd->isas;
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -570,7 +580,7 @@ print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
|
||||
abort ();
|
||||
mach_name = arch_type->printable_name;
|
||||
|
||||
prev_isa = isa;
|
||||
prev_isa = cgen_bitset_copy (isa);
|
||||
prev_mach = mach;
|
||||
prev_endian = endian;
|
||||
cd = iq2000_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
|
||||
@ -583,7 +593,7 @@ print_insn_iq2000 (bfd_vma pc, disassemble_info *info)
|
||||
/* Save this away for future reference. */
|
||||
cl = xmalloc (sizeof (struct cpu_desc_list));
|
||||
cl->cd = cd;
|
||||
cl->isa = isa;
|
||||
cl->isa = prev_isa;
|
||||
cl->mach = mach;
|
||||
cl->endian = endian;
|
||||
cl->next = cd_list;
|
||||
|
||||
@ -2312,472 +2312,472 @@ static const CGEN_IBASE iq2000_cgen_macro_insn_table[] =
|
||||
/* nop */
|
||||
{
|
||||
-1, "nop", "nop", 32,
|
||||
{ 0|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* li $rs,$imm */
|
||||
{
|
||||
-1, "li", "li", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* move $rd,$rt */
|
||||
{
|
||||
-1, "move", "move", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* lb $rt,$lo16 */
|
||||
{
|
||||
-1, "lb-base-0", "lb", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* lbu $rt,$lo16 */
|
||||
{
|
||||
-1, "lbu-base-0", "lbu", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* lh $rt,$lo16 */
|
||||
{
|
||||
-1, "lh-base-0", "lh", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* lw $rt,$lo16 */
|
||||
{
|
||||
-1, "lw-base-0", "lw", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* add $rt,$rs,$lo16 */
|
||||
{
|
||||
-1, "m-add", "add", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* addu $rt,$rs,$lo16 */
|
||||
{
|
||||
-1, "m-addu", "addu", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* and $rt,$rs,$lo16 */
|
||||
{
|
||||
-1, "m-and", "and", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* j $rs */
|
||||
{
|
||||
-1, "m-j", "j", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* or $rt,$rs,$lo16 */
|
||||
{
|
||||
-1, "m-or", "or", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* sll $rd,$rt,$rs */
|
||||
{
|
||||
-1, "m-sll", "sll", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* slt $rt,$rs,$imm */
|
||||
{
|
||||
-1, "m-slt", "slt", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* sltu $rt,$rs,$imm */
|
||||
{
|
||||
-1, "m-sltu", "sltu", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* sra $rd,$rt,$rs */
|
||||
{
|
||||
-1, "m-sra", "sra", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* srl $rd,$rt,$rs */
|
||||
{
|
||||
-1, "m-srl", "srl", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* not $rd,$rt */
|
||||
{
|
||||
-1, "not", "not", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* subi $rt,$rs,$mlo16 */
|
||||
{
|
||||
-1, "subi", "subi", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* sub $rt,$rs,$mlo16 */
|
||||
{
|
||||
-1, "m-sub", "sub", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* subu $rt,$rs,$mlo16 */
|
||||
{
|
||||
-1, "m-subu", "subu", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* sb $rt,$lo16 */
|
||||
{
|
||||
-1, "sb-base-0", "sb", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* sh $rt,$lo16 */
|
||||
{
|
||||
-1, "sh-base-0", "sh", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* sw $rt,$lo16 */
|
||||
{
|
||||
-1, "sw-base-0", "sw", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* xor $rt,$rs,$lo16 */
|
||||
{
|
||||
-1, "m-xor", "xor", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_BASE) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } } } }
|
||||
},
|
||||
/* ldw $rt,$lo16 */
|
||||
{
|
||||
-1, "ldw-base-0", "ldw", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RS)|A(USES_RT)|A(LOAD_DELAY)|A(EVEN_REG_NUM)|A(ALIAS), { (1<<MACH_IQ2000) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RS)|A(USES_RT)|A(LOAD_DELAY)|A(EVEN_REG_NUM)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } }
|
||||
},
|
||||
/* sdw $rt,$lo16 */
|
||||
{
|
||||
-1, "sdw-base-0", "sdw", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(EVEN_REG_NUM)|A(ALIAS), { (1<<MACH_IQ2000) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(EVEN_REG_NUM)|A(ALIAS), { { { (1<<MACH_IQ2000), 0 } } } }
|
||||
},
|
||||
/* avail */
|
||||
{
|
||||
-1, "m-avail", "avail", 32,
|
||||
{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cam36 $rd,$rt,${cam-z} */
|
||||
{
|
||||
-1, "m-cam36", "cam36", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cam72 $rd,$rt,${cam-z} */
|
||||
{
|
||||
-1, "m-cam72", "cam72", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cam144 $rd,$rt,${cam-z} */
|
||||
{
|
||||
-1, "m-cam144", "cam144", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cam288 $rd,$rt,${cam-z} */
|
||||
{
|
||||
-1, "m-cam288", "cam288", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm32read $rd,$rt */
|
||||
{
|
||||
-1, "m-cm32read", "cm32read", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm64read $rd,$rt */
|
||||
{
|
||||
-1, "m-cm64read", "cm64read", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm32mlog $rs,$rt */
|
||||
{
|
||||
-1, "m-cm32mlog", "cm32mlog", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm32and $rs,$rt */
|
||||
{
|
||||
-1, "m-cm32and", "cm32and", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm32andn $rs,$rt */
|
||||
{
|
||||
-1, "m-cm32andn", "cm32andn", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm32or $rs,$rt */
|
||||
{
|
||||
-1, "m-cm32or", "cm32or", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm32ra $rs,$rt */
|
||||
{
|
||||
-1, "m-cm32ra", "cm32ra", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm32rd $rt */
|
||||
{
|
||||
-1, "m-cm32rd", "cm32rd", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm32ri $rt */
|
||||
{
|
||||
-1, "m-cm32ri", "cm32ri", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm32rs $rs,$rt */
|
||||
{
|
||||
-1, "m-cm32rs", "cm32rs", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm32sa $rs,$rt */
|
||||
{
|
||||
-1, "m-cm32sa", "cm32sa", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm32sd $rt */
|
||||
{
|
||||
-1, "m-cm32sd", "cm32sd", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm32si $rt */
|
||||
{
|
||||
-1, "m-cm32si", "cm32si", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm32ss $rs,$rt */
|
||||
{
|
||||
-1, "m-cm32ss", "cm32ss", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm32xor $rs,$rt */
|
||||
{
|
||||
-1, "m-cm32xor", "cm32xor", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm64clr $rt */
|
||||
{
|
||||
-1, "m-cm64clr", "cm64clr", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm64ra $rs,$rt */
|
||||
{
|
||||
-1, "m-cm64ra", "cm64ra", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm64rd $rt */
|
||||
{
|
||||
-1, "m-cm64rd", "cm64rd", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm64ri $rt */
|
||||
{
|
||||
-1, "m-cm64ri", "cm64ri", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm64ria2 $rs,$rt */
|
||||
{
|
||||
-1, "m-cm64ria2", "cm64ria2", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm64rs $rs,$rt */
|
||||
{
|
||||
-1, "m-cm64rs", "cm64rs", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm64sa $rs,$rt */
|
||||
{
|
||||
-1, "m-cm64sa", "cm64sa", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm64sd $rt */
|
||||
{
|
||||
-1, "m-cm64sd", "cm64sd", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm64si $rt */
|
||||
{
|
||||
-1, "m-cm64si", "cm64si", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm64sia2 $rs,$rt */
|
||||
{
|
||||
-1, "m-cm64sia2", "cm64sia2", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm64ss $rs,$rt */
|
||||
{
|
||||
-1, "m-cm64ss", "cm64ss", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm128ria2 $rs,$rt */
|
||||
{
|
||||
-1, "m-cm128ria2", "cm128ria2", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm128ria3 $rs,$rt,${cm-3z} */
|
||||
{
|
||||
-1, "m-cm128ria3", "cm128ria3", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm128ria4 $rs,$rt,${cm-4z} */
|
||||
{
|
||||
-1, "m-cm128ria4", "cm128ria4", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm128sia2 $rs,$rt */
|
||||
{
|
||||
-1, "m-cm128sia2", "cm128sia2", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm128sia3 $rs,$rt,${cm-3z} */
|
||||
{
|
||||
-1, "m-cm128sia3", "cm128sia3", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cm128sia4 $rs,$rt,${cm-4z} */
|
||||
{
|
||||
-1, "m-cm128sia4", "cm128sia4", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* cmphdr */
|
||||
{
|
||||
-1, "m-cmphdr", "cmphdr", 32,
|
||||
{ 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* dbd $rd,$rt */
|
||||
{
|
||||
-1, "m-dbd", "dbd", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* dbd $rt */
|
||||
{
|
||||
-1, "m2-dbd", "dbd", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* dpwt $rs */
|
||||
{
|
||||
-1, "m-dpwt", "dpwt", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* free $rs */
|
||||
{
|
||||
-1, "m-free", "free", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* lock $rt */
|
||||
{
|
||||
-1, "m-lock", "lock", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* pkrla $rs,$rt */
|
||||
{
|
||||
-1, "m-pkrla", "pkrla", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* pkrlac $rs,$rt */
|
||||
{
|
||||
-1, "m-pkrlac", "pkrlac", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* pkrlah $rs,$rt */
|
||||
{
|
||||
-1, "m-pkrlah", "pkrlah", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* pkrlau $rs,$rt */
|
||||
{
|
||||
-1, "m-pkrlau", "pkrlau", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* pkrli $rs,$rt,$bytecount */
|
||||
{
|
||||
-1, "m-pkrli", "pkrli", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* pkrlic $rs,$rt,$bytecount */
|
||||
{
|
||||
-1, "m-pkrlic", "pkrlic", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* pkrlih $rs,$rt,$bytecount */
|
||||
{
|
||||
-1, "m-pkrlih", "pkrlih", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* pkrliu $rs,$rt,$bytecount */
|
||||
{
|
||||
-1, "m-pkrliu", "pkrliu", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* rba $rs,$rt */
|
||||
{
|
||||
-1, "m-rba", "rba", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* rbal $rs,$rt */
|
||||
{
|
||||
-1, "m-rbal", "rbal", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* rbar $rs,$rt */
|
||||
{
|
||||
-1, "m-rbar", "rbar", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* rbi $rs,$rt,$bytecount */
|
||||
{
|
||||
-1, "m-rbi", "rbi", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* rbil $rs,$rt,$bytecount */
|
||||
{
|
||||
-1, "m-rbil", "rbil", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* rbir $rs,$rt,$bytecount */
|
||||
{
|
||||
-1, "m-rbir", "rbir", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* swwr $rs,$rt */
|
||||
{
|
||||
-1, "m-swwr", "swwr", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* swwru $rs,$rt */
|
||||
{
|
||||
-1, "m-swwru", "swwru", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* tstod $rs */
|
||||
{
|
||||
-1, "m-tstod", "tstod", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* unlk $rt */
|
||||
{
|
||||
-1, "m-unlk", "unlk", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* wba $rs,$rt */
|
||||
{
|
||||
-1, "m-wba", "wba", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* wbac $rs,$rt */
|
||||
{
|
||||
-1, "m-wbac", "wbac", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* wbau $rs,$rt */
|
||||
{
|
||||
-1, "m-wbau", "wbau", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* wbi $rs,$rt,$bytecount */
|
||||
{
|
||||
-1, "m-wbi", "wbi", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* wbic $rs,$rt,$bytecount */
|
||||
{
|
||||
-1, "m-wbic", "wbic", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
/* wbiu $rs,$rt,$bytecount */
|
||||
{
|
||||
-1, "m-wbiu", "wbiu", 32,
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { (1<<MACH_IQ10) } }
|
||||
{ 0|A(NO_DIS)|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(ALIAS), { { { (1<<MACH_IQ10), 0 } } } }
|
||||
},
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user