* config/tc-mips.c (prev_insn_reloc_type): New static variable.
(RELAX_MIPS16_ENCODE): Add dslot and jal_dslot arguments, and store them. Adjust other RELAX_MIPS16 macros. (RELAX_MIPS16_DSLOT): Define. (RELAX_MIPS16_JAL_DSLOT): Define. (append_insn): Pass new arguments to RELAX_MIPS16_ENCODE. Correct handling of whether previous instruction has a fixup. Set prev_insn_reloc_type. (mips_no_prev_insn): Clear prev_insn_reloc_type. (mips16_extended_frag): Use the right base address for a PC relative add or load. (md_convert_frag): Likewise. If a PC relative add or load is used, record the alignment for the section.
This commit is contained in:
Ian Lance Taylor
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39e5bea281
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@ -1,3 +1,19 @@
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Sat Dec 14 22:37:27 1996 Ian Lance Taylor <ian@cygnus.com>
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* config/tc-mips.c (prev_insn_reloc_type): New static variable.
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(RELAX_MIPS16_ENCODE): Add dslot and jal_dslot arguments, and
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store them. Adjust other RELAX_MIPS16 macros.
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(RELAX_MIPS16_DSLOT): Define.
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(RELAX_MIPS16_JAL_DSLOT): Define.
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(append_insn): Pass new arguments to RELAX_MIPS16_ENCODE. Correct
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handling of whether previous instruction has a fixup. Set
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prev_insn_reloc_type.
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(mips_no_prev_insn): Clear prev_insn_reloc_type.
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(mips16_extended_frag): Use the right base address for a PC
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relative add or load.
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(md_convert_frag): Likewise. If a PC relative add or load is
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used, record the alignment for the section.
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Fri Dec 13 13:00:33 1996 Ian Lance Taylor <ian@cygnus.com>
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* write.c (adjust_reloc_syms): Don't reduce a reloc against a
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@ -304,6 +304,9 @@ static struct frag *prev_insn_frag;
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/* The offset into prev_insn_frag for the previous instruction. */
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static long prev_insn_where;
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/* The reloc type for the previous instruction, if any. */
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static bfd_reloc_code_real_type prev_insn_reloc_type;
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/* The reloc for the previous instruction, if any. */
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static fixS *prev_insn_fixp;
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@ -452,30 +455,34 @@ static const int mips16_to_32_reg_map[] =
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the same time that we support the relaxation described above. We
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use the high bit of the subtype field to distinguish these cases.
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The information we store for this type of relaxation is simply the
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argument code found in the opcode file for this relocation, and
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whether the user explicitly requested a small or extended form.
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That tells us the size of the value, and how it should be stored.
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We also store whether the fragment is considered to be extended or
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not. We also store whether this is known to be a branch to a
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different section, whether we have tried to relax this frag yet,
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and whether we have ever extended a PC relative fragment because of
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a shift count. */
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#define RELAX_MIPS16_ENCODE(type, small, ext) \
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(0x80000000 \
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| ((type) & 0xff) \
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| ((small) ? 0x100 : 0) \
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| ((ext) ? 0x200 : 0))
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The information we store for this type of relaxation is the
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argument code found in the opcode file for this relocation, whether
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the user explicitly requested a small or extended form, and whether
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the relocation is in a jump or jal delay slot. That tells us the
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size of the value, and how it should be stored. We also store
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whether the fragment is considered to be extended or not. We also
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store whether this is known to be a branch to a different section,
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whether we have tried to relax this frag yet, and whether we have
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ever extended a PC relative fragment because of a shift count. */
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#define RELAX_MIPS16_ENCODE(type, small, ext, dslot, jal_dslot) \
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(0x80000000 \
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| ((type) & 0xff) \
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| ((small) ? 0x100 : 0) \
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| ((ext) ? 0x200 : 0) \
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| ((dslot) ? 0x400 : 0) \
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| ((jal_dslot) ? 0x800 : 0))
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#define RELAX_MIPS16_P(i) (((i) & 0x80000000) != 0)
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#define RELAX_MIPS16_TYPE(i) ((i) & 0xff)
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#define RELAX_MIPS16_USER_SMALL(i) (((i) & 0x100) != 0)
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#define RELAX_MIPS16_USER_EXT(i) (((i) & 0x200) != 0)
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#define RELAX_MIPS16_EXTENDED(i) (((i) & 0x400) != 0)
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#define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x400)
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#define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x400)
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#define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x800) != 0)
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#define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x800)
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#define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x800)
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#define RELAX_MIPS16_DSLOT(i) (((i) & 0x400) != 0)
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#define RELAX_MIPS16_JAL_DSLOT(i) (((i) & 0x800) != 0)
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#define RELAX_MIPS16_EXTENDED(i) (((i) & 0x1000) != 0)
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#define RELAX_MIPS16_MARK_EXTENDED(i) ((i) | 0x1000)
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#define RELAX_MIPS16_CLEAR_EXTENDED(i) ((i) &~ 0x1000)
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#define RELAX_MIPS16_LONG_BRANCH(i) (((i) & 0x2000) != 0)
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#define RELAX_MIPS16_MARK_LONG_BRANCH(i) ((i) | 0x2000)
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#define RELAX_MIPS16_CLEAR_LONG_BRANCH(i) ((i) &~ 0x2000)
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/* Prototypes for static functions. */
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@ -1384,7 +1391,11 @@ append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
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assert (mips16 && address_expr != NULL);
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f = frag_var (rs_machine_dependent, 4, 0,
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RELAX_MIPS16_ENCODE (reloc_type - BFD_RELOC_UNUSED,
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mips16_small, mips16_ext),
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mips16_small, mips16_ext,
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(prev_pinfo
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& INSN_UNCOND_BRANCH_DELAY),
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(prev_insn_reloc_type
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== BFD_RELOC_MIPS16_JMP)),
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make_expr_symbol (address_expr), (long) 0,
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(char *) NULL);
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}
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@ -1821,6 +1832,10 @@ append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
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prev_prev_insn.insn_mo = &dummy_opcode;
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prev_insn.insn_mo = &dummy_opcode;
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}
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prev_insn_fixp = NULL;
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prev_insn_reloc_type = BFD_RELOC_UNUSED;
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prev_insn_extended = 0;
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}
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else if (pinfo & INSN_COND_BRANCH_LIKELY)
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{
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@ -1832,6 +1847,9 @@ append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
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/* Update the previous insn information. */
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prev_prev_insn = *ip;
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prev_insn.insn_mo = &dummy_opcode;
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prev_insn_fixp = NULL;
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prev_insn_reloc_type = BFD_RELOC_UNUSED;
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prev_insn_extended = 0;
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}
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else
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{
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@ -1846,17 +1864,28 @@ append_insn (place, ip, address_expr, reloc_type, unmatched_hi)
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immediately; since this insn is not a branch, we know it
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is not in a delay slot. */
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prev_insn_is_delay_slot = 0;
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prev_insn_fixp = fixp;
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prev_insn_reloc_type = reloc_type;
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if (mips16)
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prev_insn_extended = (ip->use_extend
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|| reloc_type > BFD_RELOC_UNUSED);
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}
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prev_prev_insn_unreordered = prev_insn_unreordered;
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prev_insn_unreordered = 0;
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prev_insn_frag = frag_now;
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prev_insn_where = f - frag_now->fr_literal;
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prev_insn_fixp = fixp;
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if (mips16)
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prev_insn_extended = ip->use_extend || reloc_type > BFD_RELOC_UNUSED;
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prev_insn_valid = 1;
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}
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else
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{
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/* We need to record a bit of uninformation even when we are not
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reordering, in order to determine the base address for mips16
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PC relative relocs. */
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prev_insn = *ip;
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prev_insn_reloc_type = reloc_type;
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}
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/* We just output an insn, so the next one doesn't have a label. */
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insn_label = NULL;
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@ -1874,6 +1903,7 @@ mips_no_prev_insn ()
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prev_insn_is_delay_slot = 0;
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prev_insn_unreordered = 0;
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prev_insn_extended = 0;
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prev_insn_reloc_type = BFD_RELOC_UNUSED;
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prev_prev_insn_unreordered = 0;
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insn_label = NULL;
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}
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@ -9163,7 +9193,20 @@ mips16_extended_frag (fragp, sec, stretch)
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val += stretch;
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}
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addr = fragp->fr_address + fragp->fr_fix + 2;
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addr = fragp->fr_address + fragp->fr_fix;
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/* The base address rules are complicated. The base address of
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a branch is the following instruction. The base address of a
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PC relative load or add is the instruction itself, but if it
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is extended add 2, and if it is in a delay slot (in which
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case it can not be extended) use the address of the
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instruction whose delay slot it is in. */
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if (type == 'p' || type == 'q')
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addr += 2;
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else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
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addr -= 4;
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else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
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addr -= 2;
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/* If we are currently assuming that this frag should be
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extended, then the current address is two bytes higher. */
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@ -9558,11 +9601,26 @@ md_convert_frag (abfd, asec, fragp)
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{
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addressT addr;
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addr = fragp->fr_address + fragp->fr_fix + 2;
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addr = fragp->fr_address + fragp->fr_fix;
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/* The rules for the base address of a PC relative reloc are
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complicated; see mips16_extended_frag. */
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if (type == 'p' || type == 'q')
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addr += 2;
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else if (RELAX_MIPS16_JAL_DSLOT (fragp->fr_subtype))
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addr -= 4;
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else if (RELAX_MIPS16_DSLOT (fragp->fr_subtype))
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addr -= 2;
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if (ext)
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addr += 2;
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addr &= ~ (addressT) ((1 << op->shift) - 1);
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val -= addr;
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/* Make sure the section winds up with the alignment we have
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assumed. */
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if (op->shift > 0)
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record_alignment (asec, op->shift);
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}
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buf = (bfd_byte *) (fragp->fr_literal + fragp->fr_fix);
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