From a2f8e947a8457341d2d82b555ff739839cb8de1f Mon Sep 17 00:00:00 2001 From: Mike Frysinger Date: Tue, 5 Jan 2021 00:22:28 -0500 Subject: [PATCH] sim: h8300: fix test mach markers These tests all fail to assemble when targeting the h8300 or h8300h cpu variants with errors like: rotl.s:242: Warning: Opcode `rotl.b' with these operand types not available in H8/300H mode rotl.s:242: Error: invalid operands It's been this way for years and no one seems to care, so disable them for those targets since the assembler thinks it's impossible. --- sim/testsuite/sim/h8300/ChangeLog | 6 ++++++ sim/testsuite/sim/h8300/rotl.s | 2 +- sim/testsuite/sim/h8300/rotr.s | 2 +- sim/testsuite/sim/h8300/rotxl.s | 2 +- sim/testsuite/sim/h8300/rotxr.s | 2 +- sim/testsuite/sim/h8300/shal.s | 2 +- sim/testsuite/sim/h8300/shar.s | 2 +- sim/testsuite/sim/h8300/shll.s | 2 +- sim/testsuite/sim/h8300/shlr.s | 2 +- sim/testsuite/sim/h8300/tas.s | 2 +- 10 files changed, 15 insertions(+), 9 deletions(-) diff --git a/sim/testsuite/sim/h8300/ChangeLog b/sim/testsuite/sim/h8300/ChangeLog index a4e7532352..82128cc43a 100644 --- a/sim/testsuite/sim/h8300/ChangeLog +++ b/sim/testsuite/sim/h8300/ChangeLog @@ -1,3 +1,9 @@ +2021-01-05 Mike Frysinger + + * rotl.s (mach): Set to "h8300s h8sx". + * rotr.s, rotxl.s, rotxr.s, shal.s, shar.s, shll.s, shlr.s, tas.s: + Likewise. + 2021-01-05 Mike Frysinger * allinsn.exp: Rewrite file to use globs. diff --git a/sim/testsuite/sim/h8300/rotl.s b/sim/testsuite/sim/h8300/rotl.s index 088345d3df..1978c2d557 100644 --- a/sim/testsuite/sim/h8300/rotl.s +++ b/sim/testsuite/sim/h8300/rotl.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'rotl' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/rotr.s b/sim/testsuite/sim/h8300/rotr.s index 2a964c1c29..658ef821f0 100644 --- a/sim/testsuite/sim/h8300/rotr.s +++ b/sim/testsuite/sim/h8300/rotr.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'rotr' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/rotxl.s b/sim/testsuite/sim/h8300/rotxl.s index 3ae703ef80..d0ff4a3fb7 100644 --- a/sim/testsuite/sim/h8300/rotxl.s +++ b/sim/testsuite/sim/h8300/rotxl.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'rotxl' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/rotxr.s b/sim/testsuite/sim/h8300/rotxr.s index 96ec8a12b6..31a351fb23 100644 --- a/sim/testsuite/sim/h8300/rotxr.s +++ b/sim/testsuite/sim/h8300/rotxr.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'rotxr' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/shal.s b/sim/testsuite/sim/h8300/shal.s index ccea9071a8..5d930d9da6 100644 --- a/sim/testsuite/sim/h8300/shal.s +++ b/sim/testsuite/sim/h8300/shal.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'shal' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/shar.s b/sim/testsuite/sim/h8300/shar.s index 9c9166be31..6b182aa01c 100644 --- a/sim/testsuite/sim/h8300/shar.s +++ b/sim/testsuite/sim/h8300/shar.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'shar' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/shll.s b/sim/testsuite/sim/h8300/shll.s index 7fbf14d056..f21a60b81f 100644 --- a/sim/testsuite/sim/h8300/shll.s +++ b/sim/testsuite/sim/h8300/shll.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'shll' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/shlr.s b/sim/testsuite/sim/h8300/shlr.s index 42233134b4..c9f6a08bc8 100644 --- a/sim/testsuite/sim/h8300/shlr.s +++ b/sim/testsuite/sim/h8300/shlr.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'shlr' -# mach(): all +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2 diff --git a/sim/testsuite/sim/h8300/tas.s b/sim/testsuite/sim/h8300/tas.s index b8aebd80de..60bea92002 100644 --- a/sim/testsuite/sim/h8300/tas.s +++ b/sim/testsuite/sim/h8300/tas.s @@ -1,5 +1,5 @@ # Hitachi H8 testcase 'tas' -# mach(): h8300h h8300s h8sx +# mach(): h8300s h8sx # as(h8300): --defsym sim_cpu=0 # as(h8300h): --defsym sim_cpu=1 # as(h8300s): --defsym sim_cpu=2