x86: unbreak certain MPX insn operand forms
Commit 8b65b8953a ("x86: Remove the prefix byte from non-VEX/EVEX
base_opcode") dropped the mandatory prefix bytes from legacy encoded
insn templates, but failed to also adjust affected MPX-specific checks
in two places.
For the expressions to remain halfway readable, introduce local
variables to hold current_templates->start.
This commit is contained in:
Jan Beulich
parent
f596b03f55
commit
a152332d17
@ -1,3 +1,13 @@
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2021-03-23 Jan Beulich <jbeulich@suse.com>
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* config/tc-i386.c (i386_index_check): New local variable t.
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Correct MPX insn check.
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* config/tc-i386-intel.c (i386_intel_simplify_register): Correct
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MPX insn check.
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* testsuite/gas/i386/x86-64-mpx.s: Add RIP-relative cases. Test
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index scaling by other than 1.
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* testsuite/gas/i386/x86-64-mpx.d: Adjust expectations.
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2021-03-22 Martin Liska <mliska@suse.cz>
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* config/tc-i386.c (md_parse_option): Replace usage of CONST_STRNEQ with startswith.
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@ -314,9 +314,13 @@ i386_intel_simplify_register (expressionS *e)
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intel_state.base = i386_regtab + reg_num;
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else if (!intel_state.index)
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{
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const insn_template *t = current_templates->start;
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if (intel_state.in_scale
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|| current_templates->start->base_opcode == 0xf30f1b /* bndmk */
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|| (current_templates->start->base_opcode & ~1) == 0x0f1a /* bnd{ld,st}x */
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|| (t->opcode_modifier.opcodeprefix == PREFIX_0XF3
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&& t->base_opcode == 0x0f1b /* bndmk */)
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|| (t->opcode_modifier.opcodeprefix == PREFIX_NONE
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&& (t->base_opcode & ~1) == 0x0f1a /* bnd{ld,st}x */)
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|| i386_regtab[reg_num].reg_type.bitfield.baseindex)
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intel_state.index = i386_regtab + reg_num;
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else
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@ -11031,9 +11031,10 @@ i386_index_check (const char *operand_string)
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{
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const char *kind = "base/index";
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enum flag_code addr_mode = i386_addressing_mode ();
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const insn_template *t = current_templates->start;
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if (current_templates->start->opcode_modifier.isstring
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&& !current_templates->start->cpu_flags.bitfield.cpupadlock
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if (t->opcode_modifier.isstring
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&& !t->cpu_flags.bitfield.cpupadlock
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&& (current_templates->end[-1].opcode_modifier.isstring
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|| i.mem_operands))
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{
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@ -11050,7 +11051,7 @@ i386_index_check (const char *operand_string)
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kind = "string address";
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if (current_templates->start->opcode_modifier.prefixok == PrefixRep)
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if (t->opcode_modifier.prefixok == PrefixRep)
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{
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int es_op = current_templates->end[-1].opcode_modifier.isstring
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- IS_STRING_ES_OP0;
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@ -11130,9 +11131,11 @@ i386_index_check (const char *operand_string)
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goto bad_address;
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/* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
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if (current_templates->start->base_opcode == 0xf30f1b
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|| (current_templates->start->base_opcode & ~1) == 0x0f1a
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|| current_templates->start->opcode_modifier.sib == SIBMEM)
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if ((t->opcode_modifier.opcodeprefix == PREFIX_0XF3
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&& t->base_opcode == 0x0f1b)
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|| (t->opcode_modifier.opcodeprefix == PREFIX_NONE
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&& (t->base_opcode & ~1) == 0x0f1a)
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|| t->opcode_modifier.sib == SIBMEM)
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{
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/* They cannot use RIP-relative addressing. */
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if (i.base_reg && i.base_reg->reg_num == RegIP)
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@ -11142,7 +11145,8 @@ i386_index_check (const char *operand_string)
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}
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/* bndldx and bndstx ignore their scale factor. */
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if ((current_templates->start->base_opcode & ~1) == 0x0f1a
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if (t->opcode_modifier.opcodeprefix == PREFIX_NONE
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&& (t->base_opcode & ~1) == 0x0f1a
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&& i.log2_scale_factor)
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as_warn (_("register scaling is being ignored here"));
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}
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@ -14,16 +14,17 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f3 0f 1b 48 03 bndmk 0x3\(%rax\),%bnd1
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[ ]*[a-f0-9]+: f3 42 0f 1b 0c 25 03 00 00 00 bndmk 0x3\(,%r12,1\),%bnd1
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[ ]*[a-f0-9]+: f3 0f 1b 0c 08 bndmk \(%rax,%rcx,1\),%bnd1
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[ ]*[a-f0-9]+: f3 41 0f 1b 4c 03 03 bndmk 0x3\(%r11,%rax,1\),%bnd1
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[ ]*[a-f0-9]+: f3 41 0f 1b 4c 43 03 bndmk 0x3\(%r11,%rax,2\),%bnd1
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[ ]*[a-f0-9]+: f3 42 0f 1b 4c 0b 03 bndmk 0x3\(%rbx,%r9,1\),%bnd1
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[ ]*[a-f0-9]+: 66 41 0f 1a 0b bndmov \(%r11\),%bnd1
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[ ]*[a-f0-9]+: 66 0f 1a 08 bndmov \(%rax\),%bnd1
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[ ]*[a-f0-9]+: 66 0f 1a 0c 25 99 03 00 00 bndmov 0x399,%bnd1
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[ ]*[a-f0-9]+: 66 41 0f 1a 51 03 bndmov 0x3\(%r9\),%bnd2
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[ ]*[a-f0-9]+: 66 0f 1a 50 03 bndmov 0x3\(%rax\),%bnd2
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[ ]*[a-f0-9]+: 66 0f 1a 15 33 33 00 00 bndmov 0x3333\(%rip\),%bnd2 ?.*
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[ ]*[a-f0-9]+: 66 42 0f 1a 04 25 03 00 00 00 bndmov 0x3\(,%r12,1\),%bnd0
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[ ]*[a-f0-9]+: 66 0f 1a 14 10 bndmov \(%rax,%rdx,1\),%bnd2
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[ ]*[a-f0-9]+: 66 41 0f 1a 4c 03 03 bndmov 0x3\(%r11,%rax,1\),%bnd1
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[ ]*[a-f0-9]+: 66 41 0f 1a 4c 43 03 bndmov 0x3\(%r11,%rax,2\),%bnd1
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[ ]*[a-f0-9]+: 66 42 0f 1a 4c 0b 03 bndmov 0x3\(%rbx,%r9,1\),%bnd1
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[ ]*[a-f0-9]+: 66 0f 1a c2 bndmov %bnd2,%bnd0
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[ ]*[a-f0-9]+: 66 41 0f 1b 0b bndmov %bnd1,\(%r11\)
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@ -31,9 +32,10 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 66 0f 1b 0c 25 99 03 00 00 bndmov %bnd1,0x399
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[ ]*[a-f0-9]+: 66 41 0f 1b 51 03 bndmov %bnd2,0x3\(%r9\)
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[ ]*[a-f0-9]+: 66 0f 1b 50 03 bndmov %bnd2,0x3\(%rax\)
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[ ]*[a-f0-9]+: 66 0f 1b 15 33 33 00 00 bndmov %bnd2,0x3333\(%rip\) ?.*
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[ ]*[a-f0-9]+: 66 42 0f 1b 04 25 03 00 00 00 bndmov %bnd0,0x3\(,%r12,1\)
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[ ]*[a-f0-9]+: 66 0f 1b 14 10 bndmov %bnd2,\(%rax,%rdx,1\)
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[ ]*[a-f0-9]+: 66 41 0f 1b 4c 03 03 bndmov %bnd1,0x3\(%r11,%rax,1\)
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[ ]*[a-f0-9]+: 66 41 0f 1b 4c 43 03 bndmov %bnd1,0x3\(%r11,%rax,2\)
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[ ]*[a-f0-9]+: 66 42 0f 1b 4c 0b 03 bndmov %bnd1,0x3\(%rbx,%r9,1\)
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[ ]*[a-f0-9]+: 66 0f 1a d0 bndmov %bnd0,%bnd2
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[ ]*[a-f0-9]+: f3 41 0f 1a 0b bndcl \(%r11\),%bnd1
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@ -43,9 +45,10 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f3 0f 1a 0c 25 99 03 00 00 bndcl 0x399,%bnd1
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[ ]*[a-f0-9]+: f3 41 0f 1a 51 03 bndcl 0x3\(%r9\),%bnd2
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[ ]*[a-f0-9]+: f3 0f 1a 50 03 bndcl 0x3\(%rax\),%bnd2
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[ ]*[a-f0-9]+: f3 0f 1a 15 33 33 00 00 bndcl 0x3333\(%rip\),%bnd2 ?.*
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[ ]*[a-f0-9]+: f3 42 0f 1a 04 25 03 00 00 00 bndcl 0x3\(,%r12,1\),%bnd0
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[ ]*[a-f0-9]+: f3 0f 1a 14 10 bndcl \(%rax,%rdx,1\),%bnd2
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[ ]*[a-f0-9]+: f3 41 0f 1a 4c 03 03 bndcl 0x3\(%r11,%rax,1\),%bnd1
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[ ]*[a-f0-9]+: f3 41 0f 1a 4c 43 03 bndcl 0x3\(%r11,%rax,2\),%bnd1
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[ ]*[a-f0-9]+: f3 42 0f 1a 4c 0b 03 bndcl 0x3\(%rbx,%r9,1\),%bnd1
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[ ]*[a-f0-9]+: f2 41 0f 1a 0b bndcu \(%r11\),%bnd1
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[ ]*[a-f0-9]+: f2 0f 1a 08 bndcu \(%rax\),%bnd1
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@ -54,9 +57,10 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f2 0f 1a 0c 25 99 03 00 00 bndcu 0x399,%bnd1
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[ ]*[a-f0-9]+: f2 41 0f 1a 51 03 bndcu 0x3\(%r9\),%bnd2
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[ ]*[a-f0-9]+: f2 0f 1a 50 03 bndcu 0x3\(%rax\),%bnd2
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[ ]*[a-f0-9]+: f2 0f 1a 15 33 33 00 00 bndcu 0x3333\(%rip\),%bnd2 ?.*
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[ ]*[a-f0-9]+: f2 42 0f 1a 04 25 03 00 00 00 bndcu 0x3\(,%r12,1\),%bnd0
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[ ]*[a-f0-9]+: f2 0f 1a 14 10 bndcu \(%rax,%rdx,1\),%bnd2
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[ ]*[a-f0-9]+: f2 41 0f 1a 4c 03 03 bndcu 0x3\(%r11,%rax,1\),%bnd1
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[ ]*[a-f0-9]+: f2 41 0f 1a 4c 43 03 bndcu 0x3\(%r11,%rax,2\),%bnd1
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[ ]*[a-f0-9]+: f2 42 0f 1a 4c 0b 03 bndcu 0x3\(%rbx,%r9,1\),%bnd1
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[ ]*[a-f0-9]+: f2 41 0f 1b 0b bndcn \(%r11\),%bnd1
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[ ]*[a-f0-9]+: f2 0f 1b 08 bndcn \(%rax\),%bnd1
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@ -65,9 +69,10 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: f2 0f 1b 0c 25 99 03 00 00 bndcn 0x399,%bnd1
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[ ]*[a-f0-9]+: f2 41 0f 1b 51 03 bndcn 0x3\(%r9\),%bnd2
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[ ]*[a-f0-9]+: f2 0f 1b 50 03 bndcn 0x3\(%rax\),%bnd2
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[ ]*[a-f0-9]+: f2 0f 1b 15 33 33 00 00 bndcn 0x3333\(%rip\),%bnd2 ?.*
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[ ]*[a-f0-9]+: f2 42 0f 1b 04 25 03 00 00 00 bndcn 0x3\(,%r12,1\),%bnd0
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[ ]*[a-f0-9]+: f2 0f 1b 14 10 bndcn \(%rax,%rdx,1\),%bnd2
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[ ]*[a-f0-9]+: f2 41 0f 1b 4c 03 03 bndcn 0x3\(%r11,%rax,1\),%bnd1
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[ ]*[a-f0-9]+: f2 41 0f 1b 4c 43 03 bndcn 0x3\(%r11,%rax,2\),%bnd1
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[ ]*[a-f0-9]+: f2 42 0f 1b 4c 0b 03 bndcn 0x3\(%rbx,%r9,1\),%bnd1
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[ ]*[a-f0-9]+: 0f 1b 44 18 03 bndstx %bnd0,0x3\(%rax,%rbx,1\)
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[ ]*[a-f0-9]+: 0f 1b 54 13 03 bndstx %bnd2,0x3\(%rbx,%rdx,1\)
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@ -85,11 +90,11 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 0f 1a 14 1d 03 00 00 00 bndldx 0x3\(,%rbx,1\),%bnd2
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[ ]*[a-f0-9]+: 42 0f 1a 14 25 03 00 00 00 bndldx 0x3\(,%r12,1\),%bnd2
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[ ]*[a-f0-9]+: 0f 1a 0a bndldx \(%rdx\),%bnd1
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[ ]*[a-f0-9]+: f2 e8 25 02 00 00 bnd call 416 <foo>
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[ ]*[a-f0-9]+: f2 e8 25 02 00 00 bnd call [0-9a-f]+ <foo>
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[ ]*[a-f0-9]+: f2 ff 10 bnd call \*\(%rax\)
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[ ]*[a-f0-9]+: f2 41 ff 13 bnd call \*\(%r11\)
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[ ]*[a-f0-9]+: f2 0f 84 17 02 00 00 bnd je 416 <foo>
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[ ]*[a-f0-9]+: f2 e9 11 02 00 00 bnd jmp 416 <foo>
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[ ]*[a-f0-9]+: f2 0f 84 17 02 00 00 bnd je [0-9a-f]+ <foo>
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[ ]*[a-f0-9]+: f2 e9 11 02 00 00 bnd jmp [0-9a-f]+ <foo>
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[ ]*[a-f0-9]+: f2 ff 21 bnd jmp \*\(%rcx\)
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[ ]*[a-f0-9]+: f2 41 ff 24 24 bnd jmp \*\(%r12\)
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[ ]*[a-f0-9]+: f2 c3 bnd ret *
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@ -171,11 +176,11 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 0f 1a 14 1d 03 00 00 00 bndldx 0x3\(,%rbx,1\),%bnd2
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[ ]*[a-f0-9]+: 42 0f 1a 14 25 03 00 00 00 bndldx 0x3\(,%r12,1\),%bnd2
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[ ]*[a-f0-9]+: 0f 1a 0a bndldx \(%rdx\),%bnd1
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[ ]*[a-f0-9]+: f2 e8 16 00 00 00 bnd call 416 <foo>
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[ ]*[a-f0-9]+: f2 e8 16 00 00 00 bnd call [0-9a-f]+ <foo>
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[ ]*[a-f0-9]+: f2 ff d0 bnd call \*%rax
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[ ]*[a-f0-9]+: f2 41 ff d3 bnd call \*%r11
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[ ]*[a-f0-9]+: f2 74 0c bnd je 416 <foo>
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[ ]*[a-f0-9]+: f2 eb 09 bnd jmp 416 <foo>
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[ ]*[a-f0-9]+: f2 74 0c bnd je [0-9a-f]+ <foo>
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[ ]*[a-f0-9]+: f2 eb 09 bnd jmp [0-9a-f]+ <foo>
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[ ]*[a-f0-9]+: f2 ff e1 bnd jmp \*%rcx
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[ ]*[a-f0-9]+: f2 41 ff e4 bnd jmp \*%r12
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[ ]*[a-f0-9]+: f2 c3 bnd ret *
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@ -10,7 +10,7 @@ start:
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bndmk 0x3(%rax), %bnd1
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bndmk 0x3(,%r12,1), %bnd1
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bndmk (%rax,%rcx), %bnd1
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bndmk 0x3(%r11,%rax,1), %bnd1
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bndmk 0x3(%r11,%rax,2), %bnd1
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bndmk 0x3(%rbx,%r9,1), %bnd1
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### bndmov
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@ -19,9 +19,10 @@ start:
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bndmov (0x399), %bnd1
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bndmov 0x3(%r9), %bnd2
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bndmov 0x3(%rax), %bnd2
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bndmov 0x3333(%rip), %bnd2
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bndmov 0x3(,%r12,1), %bnd0
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bndmov (%rax,%rdx), %bnd2
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bndmov 0x3(%r11,%rax,1), %bnd1
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bndmov 0x3(%r11,%rax,2), %bnd1
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bndmov 0x3(%rbx,%r9,1), %bnd1
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bndmov %bnd2, %bnd0
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@ -30,9 +31,10 @@ start:
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bndmov %bnd1, (0x399)
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bndmov %bnd2, 0x3(%r9)
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bndmov %bnd2, 0x3(%rax)
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bndmov %bnd2, 0x3333(%rip)
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bndmov %bnd0, 0x3(,%r12,1)
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bndmov %bnd2, (%rax,%rdx)
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bndmov %bnd1, 0x3(%r11,%rax,1)
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bndmov %bnd1, 0x3(%r11,%rax,2)
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bndmov %bnd1, 0x3(%rbx,%r9,1)
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bndmov %bnd0, %bnd2
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@ -44,9 +46,10 @@ start:
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bndcl (0x399), %bnd1
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bndcl 0x3(%r9), %bnd2
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bndcl 0x3(%rax), %bnd2
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bndcl 0x3333(%rip), %bnd2
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bndcl 0x3(,%r12,1), %bnd0
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bndcl (%rax,%rdx), %bnd2
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bndcl 0x3(%r11,%rax,1), %bnd1
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bndcl 0x3(%r11,%rax,2), %bnd1
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bndcl 0x3(%rbx,%r9,1), %bnd1
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### bndcu
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@ -57,9 +60,10 @@ start:
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bndcu (0x399), %bnd1
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bndcu 0x3(%r9), %bnd2
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bndcu 0x3(%rax), %bnd2
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bndcu 0x3333(%rip), %bnd2
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bndcu 0x3(,%r12,1), %bnd0
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bndcu (%rax,%rdx), %bnd2
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bndcu 0x3(%r11,%rax,1), %bnd1
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bndcu 0x3(%r11,%rax,2), %bnd1
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bndcu 0x3(%rbx,%r9,1), %bnd1
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### bndcn
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@ -70,9 +74,10 @@ start:
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bndcn (0x399), %bnd1
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bndcn 0x3(%r9), %bnd2
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bndcn 0x3(%rax), %bnd2
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bndcn 0x3333(%rip), %bnd2
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bndcn 0x3(,%r12,1), %bnd0
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bndcn (%rax,%rdx), %bnd2
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bndcn 0x3(%r11,%rax,1), %bnd1
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bndcn 0x3(%r11,%rax,2), %bnd1
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bndcn 0x3(%rbx,%r9,1), %bnd1
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### bndstx
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