MatCat.OpenSource/8sa1-binutils-gdb
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Initialise value to zero to avoid a compile time warning.

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This commit is contained in:
Nick Clifton 2005-04-04 10:09:52 +00:00
parent ec74bb7502
commit 9494d73902
6 changed files with 21 additions and 14 deletions
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8
opcodes/ChangeLog
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@ -1,3 +1,11 @@
2005-04-04 Nick Clifton <nickc@redhat.com>
* fr30-asm.c: Regenerate.
* frv-asm.c: Regenerate.
* iq2000-asm.c: Regenerate.
* m32r-asm.c: Regenerate.
* openrisc-asm.c: Regenerate.
2005-04-01 Jan Beulich <jbeulich@novell.com> 2005-04-01 Jan Beulich <jbeulich@novell.com>
* i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any * i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any

4
opcodes/fr30-asm.c
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@ -269,14 +269,14 @@ fr30_cgen_parse_operand (cd, opindex, strp, fields)
break; break;
case FR30_OPERAND_LABEL12 : case FR30_OPERAND_LABEL12 :
{ {
bfd_vma value; bfd_vma value = 0;
errmsg = cgen_parse_address (cd, strp, FR30_OPERAND_LABEL12, 0, NULL, & value); errmsg = cgen_parse_address (cd, strp, FR30_OPERAND_LABEL12, 0, NULL, & value);
fields->f_rel12 = value; fields->f_rel12 = value;
} }
break; break;
case FR30_OPERAND_LABEL9 : case FR30_OPERAND_LABEL9 :
{ {
bfd_vma value; bfd_vma value = 0;
errmsg = cgen_parse_address (cd, strp, FR30_OPERAND_LABEL9, 0, NULL, & value); errmsg = cgen_parse_address (cd, strp, FR30_OPERAND_LABEL9, 0, NULL, & value);
fields->f_rel9 = value; fields->f_rel9 = value;
} }

4
opcodes/frv-asm.c
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@ -1229,14 +1229,14 @@ frv_cgen_parse_operand (cd, opindex, strp, fields)
break; break;
case FRV_OPERAND_LABEL16 : case FRV_OPERAND_LABEL16 :
{ {
bfd_vma value; bfd_vma value = 0;
errmsg = cgen_parse_address (cd, strp, FRV_OPERAND_LABEL16, 0, NULL, & value); errmsg = cgen_parse_address (cd, strp, FRV_OPERAND_LABEL16, 0, NULL, & value);
fields->f_label16 = value; fields->f_label16 = value;
} }
break; break;
case FRV_OPERAND_LABEL24 : case FRV_OPERAND_LABEL24 :
{ {
bfd_vma value; bfd_vma value = 0;
errmsg = parse_call_label (cd, strp, FRV_OPERAND_LABEL24, 0, NULL, & value); errmsg = parse_call_label (cd, strp, FRV_OPERAND_LABEL24, 0, NULL, & value);
fields->f_label24 = value; fields->f_label24 = value;
} }

7
opcodes/iq2000-asm.c
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@ -358,7 +358,7 @@ iq2000_cgen_parse_operand (cd, opindex, strp, fields)
break; break;
case IQ2000_OPERAND_BASEOFF : case IQ2000_OPERAND_BASEOFF :
{ {
bfd_vma value; bfd_vma value = 0;
errmsg = cgen_parse_address (cd, strp, IQ2000_OPERAND_BASEOFF, 0, NULL, & value); errmsg = cgen_parse_address (cd, strp, IQ2000_OPERAND_BASEOFF, 0, NULL, & value);
fields->f_imm = value; fields->f_imm = value;
} }
@ -401,7 +401,7 @@ iq2000_cgen_parse_operand (cd, opindex, strp, fields)
break; break;
case IQ2000_OPERAND_JMPTARG : case IQ2000_OPERAND_JMPTARG :
{ {
bfd_vma value; bfd_vma value = 0;
errmsg = cgen_parse_address (cd, strp, IQ2000_OPERAND_JMPTARG, 0, NULL, & value); errmsg = cgen_parse_address (cd, strp, IQ2000_OPERAND_JMPTARG, 0, NULL, & value);
fields->f_jtarg = value; fields->f_jtarg = value;
} }
@ -409,7 +409,6 @@ iq2000_cgen_parse_operand (cd, opindex, strp, fields)
case IQ2000_OPERAND_JMPTARGQ10 : case IQ2000_OPERAND_JMPTARGQ10 :
{ {
bfd_vma value = 0; bfd_vma value = 0;
errmsg = parse_jtargq10 (cd, strp, IQ2000_OPERAND_JMPTARGQ10, 0, NULL, & value); errmsg = parse_jtargq10 (cd, strp, IQ2000_OPERAND_JMPTARGQ10, 0, NULL, & value);
fields->f_jtargq10 = value; fields->f_jtargq10 = value;
} }
@ -434,7 +433,7 @@ iq2000_cgen_parse_operand (cd, opindex, strp, fields)
break; break;
case IQ2000_OPERAND_OFFSET : case IQ2000_OPERAND_OFFSET :
{ {
bfd_vma value; bfd_vma value = 0;
errmsg = cgen_parse_address (cd, strp, IQ2000_OPERAND_OFFSET, 0, NULL, & value); errmsg = cgen_parse_address (cd, strp, IQ2000_OPERAND_OFFSET, 0, NULL, & value);
fields->f_offset = value; fields->f_offset = value;
} }

8
opcodes/m32r-asm.c
View File

@ -255,21 +255,21 @@ m32r_cgen_parse_operand (cd, opindex, strp, fields)
break; break;
case M32R_OPERAND_DISP16 : case M32R_OPERAND_DISP16 :
{ {
bfd_vma value; bfd_vma value = 0;
errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_DISP16, 0, NULL, & value); errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_DISP16, 0, NULL, & value);
fields->f_disp16 = value; fields->f_disp16 = value;
} }
break; break;
case M32R_OPERAND_DISP24 : case M32R_OPERAND_DISP24 :
{ {
bfd_vma value; bfd_vma value = 0;
errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_DISP24, 0, NULL, & value); errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_DISP24, 0, NULL, & value);
fields->f_disp24 = value; fields->f_disp24 = value;
} }
break; break;
case M32R_OPERAND_DISP8 : case M32R_OPERAND_DISP8 :
{ {
bfd_vma value; bfd_vma value = 0;
errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_DISP8, 0, NULL, & value); errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_DISP8, 0, NULL, & value);
fields->f_disp8 = value; fields->f_disp8 = value;
} }
@ -312,7 +312,7 @@ m32r_cgen_parse_operand (cd, opindex, strp, fields)
break; break;
case M32R_OPERAND_UIMM24 : case M32R_OPERAND_UIMM24 :
{ {
bfd_vma value; bfd_vma value = 0;
errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_UIMM24, 0, NULL, & value); errmsg = cgen_parse_address (cd, strp, M32R_OPERAND_UIMM24, 0, NULL, & value);
fields->f_uimm24 = value; fields->f_uimm24 = value;
} }

4
opcodes/openrisc-asm.c
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@ -201,14 +201,14 @@ openrisc_cgen_parse_operand (cd, opindex, strp, fields)
{ {
case OPENRISC_OPERAND_ABS_26 : case OPENRISC_OPERAND_ABS_26 :
{ {
bfd_vma value; bfd_vma value = 0;
errmsg = cgen_parse_address (cd, strp, OPENRISC_OPERAND_ABS_26, 0, NULL, & value); errmsg = cgen_parse_address (cd, strp, OPENRISC_OPERAND_ABS_26, 0, NULL, & value);
fields->f_abs26 = value; fields->f_abs26 = value;
} }
break; break;
case OPENRISC_OPERAND_DISP_26 : case OPENRISC_OPERAND_DISP_26 :
{ {
bfd_vma value; bfd_vma value = 0;
errmsg = cgen_parse_address (cd, strp, OPENRISC_OPERAND_DISP_26, 0, NULL, & value); errmsg = cgen_parse_address (cd, strp, OPENRISC_OPERAND_DISP_26, 0, NULL, & value);
fields->f_disp26 = value; fields->f_disp26 = value;
} }