x86-64: Zero-extend lower 32 bits displacement to 64 bits
Since the addr32 (0x67) prefix zero-extends the lower 32 bits address to 64 bits, change disassembler to zero-extend the lower 32 bits displacement to 64 bits when there is no base nor index registers. gas/ PR gas/26237 * testsuite/gas/i386/addr32.s: Add tests for 32-bit wrapped around address. * testsuite/gas/i386/x86-64-addr32.s: Likewise. * testsuite/gas/i386/addr32.d: Updated. * testsuite/gas/i386/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/x86-64-addr32.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32-intel.d: Likewise. * testsuite/gas/i386/ilp32/x86-64-addr32.d: Likewise. opcodes/ PR gas/26237 * i386-dis.c (OP_E_memory): Without base nor index registers, 32-bit displacement to 64 bits.
This commit is contained in:
H.J. Lu
parent
f63dcaf808
commit
8e58ef803c
@ -1,3 +1,15 @@
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2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/26237
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* testsuite/gas/i386/addr32.s: Add tests for 32-bit wrapped around
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address.
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* testsuite/gas/i386/x86-64-addr32.s: Likewise.
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* testsuite/gas/i386/addr32.d: Updated.
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* testsuite/gas/i386/x86-64-addr32-intel.d: Likewise.
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* testsuite/gas/i386/x86-64-addr32.d: Likewise.
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* testsuite/gas/i386/ilp32/x86-64-addr32-intel.d: Likewise.
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* testsuite/gas/i386/ilp32/x86-64-addr32.d: Likewise.
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2020-07-14 Jan Beulich <jbeulich@suse.com>
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* testsuite/gas/i386/intel.s: Use dr<N> instead of db<N>.
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@ -13,4 +13,10 @@ Disassembly of section .text:
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[ ]*19:[ ]+67 a3 98 08 60 00[ ]+addr32[ ]+mov[ ]+%ax,0x600898
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[ ]*1f:[ ]+67 66 a3 98 08 60 00[ ]+addr32[ ]+mov[ ]+%eax,0x600898
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[ ]*26:[ ]+67 66 c7 04 24 01 00 00 00[ ]+movl[ ]+\$0x1,\(%esp\)
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[ ]*2f:[ ]+67 66 a1 ef cd ab 89[ ]+addr32[ ]+mov[ ]+0x89abcdef,%eax
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[ ]*36:[ ]+67 66 8b 1d ef cd ab 89[ ]+addr32[ ]+mov[ ]+0x89abcdef,%ebx
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[ ]*3e:[ ]+67 66 b8 ef cd ab 89[ ]+addr32[ ]+mov[ ]+\$0x89abcdef,%eax
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[ ]*45:[ ]+67 66 bb ef cd ab 89[ ]+addr32[ ]+mov[ ]+\$0x89abcdef,%ebx
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[ ]*4c:[ ]+67 66 a3 ef cd ab 89[ ]+addr32[ ]+mov[ ]+%eax,0x89abcdef
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[ ]*53:[ ]+67 66 89 1d ef cd ab 89[ ]+addr32[ ]+mov[ ]+%ebx,0x89abcdef
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#pass
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@ -7,3 +7,9 @@
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addr32 mov %ax,0x600898
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addr32 mov %eax,0x600898
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addr32 movl $0x1,(%esp)
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addr32 mov 0x89abcdef,%eax
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addr32 mov 0x89abcdef,%ebx
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addr32 mov $0x89abcdef,%eax
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addr32 mov $0x89abcdef,%ebx
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addr32 mov %eax,0x89abcdef
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addr32 mov %ebx,0x89abcdef
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@ -2,28 +2,4 @@
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#objdump: -drwMintel
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#source: ../x86-64-addr32.s
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#name: x86-64 (ILP32) 32-bit addressing (Intel mode)
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.*: +file format .*
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Disassembly of section .text:
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0+ <.text>:
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[ ]*[a-f0-9]+: 67 48 8d 80 00 00 00 00[ ]+lea[ ]+rax,\[eax\+0x0\].*
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[ ]*[a-f0-9]+: 67 49 8d 80 00 00 00 00[ ]+lea[ ]+rax,\[r8d\+0x0\].*
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[ ]*[a-f0-9]+: 67 48 8d 05 00 00 00 00[ ]+lea[ ]+rax,\[eip\+0x0\].*
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[ ]*[a-f0-9]+: 67 48 8d 04 25 00 00 00 00 lea[ ]+rax,\[eiz\*1\+0x0\].*
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[ ]*[a-f0-9]+: 67 a0 98 08 60 00 addr32 mov al,ds:0x600898
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[ ]*[a-f0-9]+: 67 66 a1 98 08 60 00 addr32 mov ax,ds:0x600898
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[ ]*[a-f0-9]+: 67 a1 98 08 60 00 addr32 mov eax,ds:0x600898
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[ ]*[a-f0-9]+: 67 48 a1 98 08 60 00 addr32 mov rax,ds:0x600898
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[ ]*[a-f0-9]+: 67 48 a1 98 08 80 00 addr32 mov rax,ds:0x800898
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 98 08 80 00 mov[ ]+rbx,QWORD PTR \[eiz\*1\+0x800898\]
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[ ]*[a-f0-9]+: 67 a2 98 08 60 00 addr32 mov ds:0x600898,al
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[ ]*[a-f0-9]+: 67 66 a3 98 08 60 00 addr32 mov ds:0x600898,ax
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[ ]*[a-f0-9]+: 67 a3 98 08 60 00 addr32 mov ds:0x600898,eax
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[ ]*[a-f0-9]+: 67 48 a3 98 08 60 00 addr32 mov ds:0x600898,rax
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[ ]*[a-f0-9]+: 67 48 a3 98 08 80 00 addr32 mov ds:0x800898,rax
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[ ]*[a-f0-9]+: 67 48 89 1c 25 98 08 80 00 mov[ ]+QWORD PTR \[eiz\*1\+0x800898\],rbx
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[ ]*[a-f0-9]+: 67 89 04 25 11 22 33 ff mov[ ]+DWORD PTR \[eiz\*1-0xccddef\],eax
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[ ]*[a-f0-9]+: 67 89 04 65 11 22 33 ff mov[ ]+DWORD PTR \[eiz\*2-0xccddef\],eax
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#pass
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#dump: ../x86-64-addr32-intel.d
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@ -2,28 +2,4 @@
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#as: -J
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#objdump: -drw
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#name: x86-64 (ILP32) 32-bit addressing
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.*: +file format .*
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Disassembly of section .text:
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0+ <.text>:
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[ ]*[a-f0-9]+: 67 48 8d 80 00 00 00 00[ ]+lea[ ]+0x0\(%eax\),%rax.*
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[ ]*[a-f0-9]+: 67 49 8d 80 00 00 00 00[ ]+lea[ ]+0x0\(%r8d\),%rax.*
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[ ]*[a-f0-9]+: 67 48 8d 05 00 00 00 00[ ]+lea[ ]+0x0\(%eip\),%rax.*
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[ ]*[a-f0-9]+: 67 48 8d 04 25 00 00 00 00[ ]+lea[ ]+0x0\(,%eiz,1\),%rax.*
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[ ]*[a-f0-9]+: 67 a0 98 08 60 00 addr32 mov 0x600898,%al
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[ ]*[a-f0-9]+: 67 66 a1 98 08 60 00 addr32 mov 0x600898,%ax
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[ ]*[a-f0-9]+: 67 a1 98 08 60 00 addr32 mov 0x600898,%eax
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[ ]*[a-f0-9]+: 67 48 a1 98 08 60 00 addr32 mov 0x600898,%rax
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[ ]*[a-f0-9]+: 67 48 a1 98 08 80 00 addr32 mov 0x800898,%rax
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 98 08 80 00 mov[ ]+0x800898\(,%eiz,1\),%rbx
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[ ]*[a-f0-9]+: 67 a2 98 08 60 00 addr32 mov %al,0x600898
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[ ]*[a-f0-9]+: 67 66 a3 98 08 60 00 addr32 mov %ax,0x600898
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[ ]*[a-f0-9]+: 67 a3 98 08 60 00 addr32 mov %eax,0x600898
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[ ]*[a-f0-9]+: 67 48 a3 98 08 60 00 addr32 mov %rax,0x600898
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[ ]*[a-f0-9]+: 67 48 a3 98 08 80 00 addr32 mov %rax,0x800898
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[ ]*[a-f0-9]+: 67 48 89 1c 25 98 08 80 00 mov[ ]+%rbx,0x800898\(,%eiz,1\)
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[ ]*[a-f0-9]+: 67 89 04 25 11 22 33 ff mov[ ]+%eax,-0xccddef\(,%eiz,1\)
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[ ]*[a-f0-9]+: 67 89 04 65 11 22 33 ff mov[ ]+%eax,-0xccddef\(,%eiz,2\)
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#pass
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#dump: ../x86-64-addr32.d
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@ -18,12 +18,18 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 67 48 a1 98 08 60 00 addr32 mov rax,ds:0x600898
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[ ]*[a-f0-9]+: 67 48 a1 98 08 80 00 addr32 mov rax,ds:0x800898
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 98 08 80 00 mov[ ]+rbx,QWORD PTR \[eiz\*1\+0x800898\]
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[ ]*[a-f0-9]+: 67 48 a1 ef cd ab 89 addr32 mov rax,ds:0x89abcdef
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 ef cd ab 89 mov[ ]+rbx,QWORD PTR \[eiz\*1\+0x89abcdef\]
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[ ]*[a-f0-9]+: 67 48 b8 ef cd ab 89 00 00 00 00 addr32 movabs rax,0x89abcdef
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[ ]*[a-f0-9]+: 67 48 bb ef cd ab 89 00 00 00 00 addr32 movabs rbx,0x89abcdef
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[ ]*[a-f0-9]+: 67 a2 98 08 60 00 addr32 mov ds:0x600898,al
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[ ]*[a-f0-9]+: 67 66 a3 98 08 60 00 addr32 mov ds:0x600898,ax
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[ ]*[a-f0-9]+: 67 a3 98 08 60 00 addr32 mov ds:0x600898,eax
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[ ]*[a-f0-9]+: 67 48 a3 98 08 60 00 addr32 mov ds:0x600898,rax
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[ ]*[a-f0-9]+: 67 48 a3 98 08 80 00 addr32 mov ds:0x800898,rax
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[ ]*[a-f0-9]+: 67 48 89 1c 25 98 08 80 00 mov[ ]+QWORD PTR \[eiz\*1\+0x800898\],rbx
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[ ]*[a-f0-9]+: 67 89 04 25 11 22 33 ff mov[ ]+DWORD PTR \[eiz\*1-0xccddef\],eax
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[ ]*[a-f0-9]+: 67 89 04 65 11 22 33 ff mov[ ]+DWORD PTR \[eiz\*2-0xccddef\],eax
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[ ]*[a-f0-9]+: 67 48 a3 ef cd ab 89 addr32 mov ds:0x89abcdef,rax
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[ ]*[a-f0-9]+: 67 48 89 1c 25 ef cd ab 89 mov[ ]+QWORD PTR \[eiz\*1\+0x89abcdef\],rbx
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[ ]*[a-f0-9]+: 67 89 04 25 11 22 33 ff mov[ ]+DWORD PTR \[eiz\*1\+0xff332211\],eax
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[ ]*[a-f0-9]+: 67 89 04 65 11 22 33 ff mov[ ]+DWORD PTR \[eiz\*2\+0xff332211\],eax
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#pass
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@ -17,12 +17,18 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+: 67 48 a1 98 08 60 00 addr32 mov 0x600898,%rax
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[ ]*[a-f0-9]+: 67 48 a1 98 08 80 00 addr32 mov 0x800898,%rax
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 98 08 80 00 mov[ ]+0x800898\(,%eiz,1\),%rbx
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[ ]*[a-f0-9]+: 67 48 a1 ef cd ab 89 addr32 mov 0x89abcdef,%rax
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[ ]*[a-f0-9]+: 67 48 8b 1c 25 ef cd ab 89 mov[ ]+0x89abcdef\(,%eiz,1\),%rbx
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[ ]*[a-f0-9]+: 67 48 b8 ef cd ab 89 00 00 00 00 addr32 movabs \$0x89abcdef,%rax
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[ ]*[a-f0-9]+: 67 48 bb ef cd ab 89 00 00 00 00 addr32 movabs \$0x89abcdef,%rbx
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[ ]*[a-f0-9]+: 67 a2 98 08 60 00 addr32 mov %al,0x600898
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[ ]*[a-f0-9]+: 67 66 a3 98 08 60 00 addr32 mov %ax,0x600898
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[ ]*[a-f0-9]+: 67 a3 98 08 60 00 addr32 mov %eax,0x600898
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[ ]*[a-f0-9]+: 67 48 a3 98 08 60 00 addr32 mov %rax,0x600898
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[ ]*[a-f0-9]+: 67 48 a3 98 08 80 00 addr32 mov %rax,0x800898
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[ ]*[a-f0-9]+: 67 48 89 1c 25 98 08 80 00 mov[ ]+%rbx,0x800898\(,%eiz,1\)
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[ ]*[a-f0-9]+: 67 89 04 25 11 22 33 ff mov[ ]+%eax,-0xccddef\(,%eiz,1\)
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[ ]*[a-f0-9]+: 67 89 04 65 11 22 33 ff mov[ ]+%eax,-0xccddef\(,%eiz,2\)
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[ ]*[a-f0-9]+: 67 48 a3 ef cd ab 89 addr32 mov %rax,0x89abcdef
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[ ]*[a-f0-9]+: 67 48 89 1c 25 ef cd ab 89 mov[ ]+%rbx,0x89abcdef\(,%eiz,1\)
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[ ]*[a-f0-9]+: 67 89 04 25 11 22 33 ff mov[ ]+%eax,0xff332211\(,%eiz,1\)
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[ ]*[a-f0-9]+: 67 89 04 65 11 22 33 ff mov[ ]+%eax,0xff332211\(,%eiz,2\)
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#pass
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@ -10,11 +10,17 @@
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addr32 mov 0x600898,%rax
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addr32 mov 0x800898,%rax
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addr32 mov 0x800898,%rbx
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addr32 mov 0x89abcdef,%rax
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addr32 mov 0x89abcdef,%rbx
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addr32 mov $0x89abcdef,%rax
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addr32 mov $0x89abcdef,%rbx
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addr32 mov %al,0x600898
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addr32 mov %ax,0x600898
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addr32 mov %eax,0x600898
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addr32 mov %rax,0x600898
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addr32 mov %rax,0x800898
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addr32 mov %rbx,0x800898
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addr32 mov %rax,0x89abcdef
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addr32 mov %rbx,0x89abcdef
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mov %eax, -0xccddef(,%eiz,)
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mov %eax, -0xccddef(,%eiz,2)
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@ -1,3 +1,9 @@
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2020-07-14 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/26237
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* i386-dis.c (OP_E_memory): Without base nor index registers,
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32-bit displacement to 64 bits.
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2020-07-14 Claudiu Zissulescu <claziss@gmail.com>
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* arc-dis.c (print_insn_arc): Detect and emit a warning when a
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@ -11877,8 +11877,13 @@ OP_E_memory (int bytemode, int sizeflag)
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{
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if (address_mode == mode_64bit)
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{
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/* Display eiz instead of addr32. */
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needindex = addr32flag;
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if (addr32flag)
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{
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/* Without base nor index registers, zero-extend the
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lower 32-bit displacement to 64 bits. */
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disp = (unsigned int) disp;
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needindex = 1;
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}
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needaddr32 = 1;
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}
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else
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