x86-64: limit breakage from gcc movdir64b et al workaround
This is only a partial fix for PR/gas 27419, in that it limits the bad behavior of accepting mismatched operands to just x32 mode. The full fix would be to revert commits27f134698aandb3a3496f83, and to address the issue in gcc instead.
This commit is contained in:
Jan Beulich
parent
5a4037661b
commit
829f3fe1f0
@ -1,3 +1,25 @@
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2021-03-25 Jan Beulich <jbeulich@suse.com>
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PR/gas 27419
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* config/tc-i386.c (process_suffix): Restrict (%rip) -> (%eip)
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conversion to x32 mode.
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* testsuite/gas/i386/ilp32/enqcmd.s,
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testsuite/gas/i386/ilp32/enqcmd.d,
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testsuite/gas/i386/ilp32/movdir.s,
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testsuite/gas/i386/ilp32/movdir.d: New.
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* testsuite/gas/i386/x86-64-enqcmd.s,
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testsuite/gas/i386/x86-64-movdir.s: Drop mismatched operand
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cases.
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* testsuite/gas/i386/x86-64-enqcmd-inval.s: Add (%rip) and
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(%eip) cases.
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* testsuite/gas/i386/x86-64-movdir64b-reg.s Add (%eip) case.
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* testsuite/gas/i386/x86-64-enqcmd.d,
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testsuite/gas/i386/x86-64-enqcmd-intel.d,
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testsuite/gas/i386/x86-64-enqcmd-inval.l,
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testsuite/gas/i386/x86-64-movdir.d,
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testsuite/gas/i386/x86-64-movdir-intel.d,
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testsuite/gas/i386/x86-64-movdir64b-reg.l: Adjust expectations.
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2021-03-25 Alan Modra <amodra@gmail.com>
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PR 27647
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@ -7169,7 +7169,7 @@ process_suffix (void)
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/* Check the register operand for the address size prefix if
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the memory operand has no real registers, like symbol, DISP
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or symbol(%rip). */
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or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
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if (i.mem_operands == 1
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&& i.reg_operands == 1
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&& i.operands == 2
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@ -7178,9 +7178,14 @@ process_suffix (void)
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? i.op[1].regs->reg_type.bitfield.word
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: i.op[1].regs->reg_type.bitfield.dword)
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&& ((i.base_reg == NULL && i.index_reg == NULL)
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|| (i.base_reg
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#if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
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|| (x86_elf_abi == X86_64_X32_ABI
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&& i.base_reg
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&& i.base_reg->reg_num == RegIP
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&& i.base_reg->reg_type.bitfield.qword))
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#else
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|| 0)
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#endif
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&& !add_prefix (ADDR_PREFIX_OPCODE))
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return 0;
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38
gas/testsuite/gas/i386/ilp32/enqcmd.d
Normal file
38
gas/testsuite/gas/i386/ilp32/enqcmd.d
Normal file
@ -0,0 +1,38 @@
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#objdump: -dw
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#name: ilp32 ENQCMD[S] insns
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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+[a-f0-9]+: f2 0f 38 f8 01 enqcmd \(%rcx\),%rax
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+[a-f0-9]+: 67 f2 0f 38 f8 01 enqcmd \(%ecx\),%eax
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+[a-f0-9]+: f3 0f 38 f8 01 enqcmds \(%rcx\),%rax
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+[a-f0-9]+: 67 f3 0f 38 f8 01 enqcmds \(%ecx\),%eax
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+[a-f0-9]+: f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%rip\),%rcx #.*
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+[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%eip\),%ecx #.*
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+[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%eip\),%ecx #.*
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+[a-f0-9]+: f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%rip\),%rcx #.*
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+[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%eip\),%ecx #.*
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+[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%eip\),%ecx #.*
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+[a-f0-9]+: 67 f2 0f 38 f8 0c 25 00 00 00 00 enqcmd 0x0\(,%eiz,1\),%ecx
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+[a-f0-9]+: 67 f2 0f 38 f8 0c 25 78 56 34 12 enqcmd 0x12345678\(,%eiz,1\),%ecx
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+[a-f0-9]+: 67 f3 0f 38 f8 0c 25 00 00 00 00 enqcmds 0x0\(,%eiz,1\),%ecx
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+[a-f0-9]+: 67 f3 0f 38 f8 0c 25 78 56 34 12 enqcmds 0x12345678\(,%eiz,1\),%ecx
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+[a-f0-9]+: f2 0f 38 f8 01 enqcmd \(%rcx\),%rax
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+[a-f0-9]+: 67 f2 0f 38 f8 01 enqcmd \(%ecx\),%eax
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+[a-f0-9]+: f3 0f 38 f8 01 enqcmds \(%rcx\),%rax
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+[a-f0-9]+: 67 f3 0f 38 f8 01 enqcmds \(%ecx\),%eax
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+[a-f0-9]+: f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%rip\),%rcx #.*
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+[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%eip\),%ecx #.*
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+[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%eip\),%ecx #.*
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+[a-f0-9]+: f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%rip\),%rcx #.*
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+[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%eip\),%ecx #.*
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+[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%eip\),%ecx #.*
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+[a-f0-9]+: 67 f2 0f 38 f8 0c 25 00 00 00 00 enqcmd 0x0\(,%eiz,1\),%ecx
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+[a-f0-9]+: 67 f2 0f 38 f8 0c 25 78 56 34 12 enqcmd 0x12345678\(,%eiz,1\),%ecx
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+[a-f0-9]+: 67 f3 0f 38 f8 0c 25 00 00 00 00 enqcmds 0x0\(,%eiz,1\),%ecx
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+[a-f0-9]+: 67 f3 0f 38 f8 0c 25 78 56 34 12 enqcmds 0x12345678\(,%eiz,1\),%ecx
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#pass
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35
gas/testsuite/gas/i386/ilp32/enqcmd.s
Normal file
35
gas/testsuite/gas/i386/ilp32/enqcmd.s
Normal file
@ -0,0 +1,35 @@
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# Check ENQCMD[S] 64-bit instructions in x32 mode
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.allow_index_reg
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.text
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_start:
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enqcmd (%rcx),%rax
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enqcmd (%ecx),%eax
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enqcmds (%rcx),%rax
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enqcmds (%ecx),%eax
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enqcmd foo(%rip),%rcx
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enqcmd foo(%rip),%ecx
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enqcmd foo(%eip),%ecx
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enqcmds foo(%rip),%rcx
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enqcmds foo(%rip),%ecx
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enqcmds foo(%eip),%ecx
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enqcmd foo, %ecx
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enqcmd 0x12345678, %ecx
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enqcmds foo, %ecx
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enqcmds 0x12345678, %ecx
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.intel_syntax noprefix
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enqcmd rax,[rcx]
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enqcmd eax,[ecx]
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enqcmds rax,[rcx]
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enqcmds eax,[ecx]
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enqcmd rcx,[rip+foo]
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enqcmd ecx,[rip+foo]
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enqcmd ecx,[eip+foo]
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enqcmds rcx,[rip+foo]
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enqcmds ecx,[rip+foo]
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enqcmds ecx,[eip+foo]
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enqcmd ecx,ds:foo
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enqcmd ecx,ds:0x12345678
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enqcmds ecx,ds:foo
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enqcmds ecx,ds:0x12345678
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29
gas/testsuite/gas/i386/ilp32/movdir.d
Normal file
29
gas/testsuite/gas/i386/ilp32/movdir.d
Normal file
@ -0,0 +1,29 @@
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#objdump: -dw
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#name: ilp32 MOVDIR[I,64B] insns
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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+[a-f0-9]+: 48 0f 38 f9 01 movdiri %rax,\(%rcx\)
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+[a-f0-9]+: 66 0f 38 f8 01 movdir64b \(%rcx\),%rax
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+[a-f0-9]+: 67 66 0f 38 f8 01 movdir64b \(%ecx\),%eax
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+[a-f0-9]+: 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%rip\),%rcx #.*
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+[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%eip\),%ecx #.*
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+[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%eip\),%ecx #.*
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+[a-f0-9]+: 67 66 0f 38 f8 0c 25 00 00 00 00 movdir64b 0x0\(,%eiz,1\),%ecx
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+[a-f0-9]+: 67 66 0f 38 f8 0c 25 78 56 34 12 movdir64b 0x12345678\(,%eiz,1\),%ecx
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+[a-f0-9]+: 0f 38 f9 01 movdiri %eax,\(%rcx\)
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+[a-f0-9]+: 48 0f 38 f9 01 movdiri %rax,\(%rcx\)
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+[a-f0-9]+: 0f 38 f9 01 movdiri %eax,\(%rcx\)
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+[a-f0-9]+: 48 0f 38 f9 01 movdiri %rax,\(%rcx\)
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+[a-f0-9]+: 66 0f 38 f8 01 movdir64b \(%rcx\),%rax
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+[a-f0-9]+: 67 66 0f 38 f8 01 movdir64b \(%ecx\),%eax
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+[a-f0-9]+: 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%rip\),%rcx #.*
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+[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%eip\),%ecx #.*
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+[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%eip\),%ecx #.*
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+[a-f0-9]+: 67 66 0f 38 f8 0c 25 00 00 00 00 movdir64b 0x0\(,%eiz,1\),%ecx
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+[a-f0-9]+: 67 66 0f 38 f8 0c 25 78 56 34 12 movdir64b 0x12345678\(,%eiz,1\),%ecx
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#pass
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26
gas/testsuite/gas/i386/ilp32/movdir.s
Normal file
26
gas/testsuite/gas/i386/ilp32/movdir.s
Normal file
@ -0,0 +1,26 @@
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# Check MOVDIR[I,64B] 64-bit instructions in x32 mode
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.allow_index_reg
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.text
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_start:
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movdiri %rax, (%rcx)
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movdir64b (%rcx),%rax
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movdir64b (%ecx),%eax
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movdir64b foo(%rip),%rcx
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movdir64b foo(%rip),%ecx
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movdir64b foo(%eip),%ecx
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movdir64b foo, %ecx
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movdir64b 0x12345678, %ecx
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.intel_syntax noprefix
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movdiri [rcx],eax
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movdiri [rcx],rax
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movdiri dword ptr [rcx],eax
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movdiri qword ptr [rcx],rax
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movdir64b rax,[rcx]
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movdir64b eax,[ecx]
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movdir64b rcx,[rip+foo]
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movdir64b ecx,[rip+foo]
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movdir64b ecx,[eip+foo]
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movdir64b ecx,ds:foo
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movdir64b ecx,ds:0x12345678
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@ -1,4 +1,3 @@
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#as:
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#objdump: -dw -Mintel
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#name: x86_64 ENQCMD[S] insns (Intel disassembly)
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#source: x86-64-enqcmd.s
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@ -15,10 +14,8 @@ Disassembly of section \.text:
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+[a-f0-9]+: 67 f3 0f 38 f8 01 enqcmds eax,\[ecx\]
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+[a-f0-9]+: f2 0f 38 f8 0d 00 00 00 00 enqcmd rcx,\[rip\+0x0\] #.*
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+[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd ecx,\[eip\+0x0\] #.*
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+[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd ecx,\[eip\+0x0\] #.*
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+[a-f0-9]+: f3 0f 38 f8 0d 00 00 00 00 enqcmds rcx,\[rip\+0x0\] #.*
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+[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds ecx,\[eip\+0x0\] #.*
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+[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds ecx,\[eip\+0x0\] #.*
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+[a-f0-9]+: 67 f2 0f 38 f8 0c 25 00 00 00 00 enqcmd ecx,\[eiz\*1\+0x0\]
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+[a-f0-9]+: 67 f2 0f 38 f8 0c 25 78 56 34 12 enqcmd ecx,\[eiz\*1\+0x12345678\]
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+[a-f0-9]+: 67 f3 0f 38 f8 0c 25 00 00 00 00 enqcmds ecx,\[eiz\*1\+0x0\]
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@ -29,10 +26,8 @@ Disassembly of section \.text:
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+[a-f0-9]+: 67 f3 0f 38 f8 01 enqcmds eax,\[ecx\]
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+[a-f0-9]+: f2 0f 38 f8 0d 00 00 00 00 enqcmd rcx,\[rip\+0x0\] #.*
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+[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd ecx,\[eip\+0x0\] #.*
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+[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd ecx,\[eip\+0x0\] #.*
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+[a-f0-9]+: f3 0f 38 f8 0d 00 00 00 00 enqcmds rcx,\[rip\+0x0\] #.*
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+[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds ecx,\[eip\+0x0\] #.*
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+[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds ecx,\[eip\+0x0\] #.*
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+[a-f0-9]+: 67 f2 0f 38 f8 0c 25 00 00 00 00 enqcmd ecx,\[eiz\*1\+0x0\]
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+[a-f0-9]+: 67 f2 0f 38 f8 0c 25 78 56 34 12 enqcmd ecx,\[eiz\*1\+0x12345678\]
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+[a-f0-9]+: 67 f3 0f 38 f8 0c 25 00 00 00 00 enqcmds ecx,\[eiz\*1\+0x0\]
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@ -1,9 +1,13 @@
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.* Assembler messages:
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.*6: Error: invalid register operand size for `enqcmd'
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.*7: Error: invalid register operand size for `enqcmd'
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.*8: Error: invalid register operand size for `enqcmds'
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.*9: Error: invalid register operand size for `enqcmds'
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.*12: Error: invalid register operand size for `enqcmd'
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.*13: Error: invalid register operand size for `enqcmd'
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.*14: Error: invalid register operand size for `enqcmds'
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.*15: Error: invalid register operand size for `enqcmds'
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.*8: Error: invalid register operand size for `enqcmd'
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.*9: Error: invalid register operand size for `enqcmd'
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.*10: Error: invalid register operand size for `enqcmds'
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.*11: Error: invalid register operand size for `enqcmds'
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.*12: Error: invalid register operand size for `enqcmds'
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.*13: Error: invalid register operand size for `enqcmds'
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.*16: Error: invalid register operand size for `enqcmd'
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.*17: Error: invalid register operand size for `enqcmd'
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.*18: Error: invalid register operand size for `enqcmds'
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.*19: Error: invalid register operand size for `enqcmds'
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@ -1,12 +1,16 @@
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# Check error for ENQCMD[S] 32-bit instructions
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# Check error for ENQCMD[S] 64-bit instructions
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.allow_index_reg
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.text
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_start:
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enqcmd (%esi),%rax
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enqcmd (%eip),%rax
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enqcmd (%rsi),%eax
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enqcmd (%rip),%eax
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enqcmds (%esi),%rax
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enqcmds (%eip),%rax
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enqcmds (%rsi),%eax
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enqcmds (%rip),%eax
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.intel_syntax noprefix
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enqcmd rax,[esi]
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@ -1,7 +1,5 @@
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#as:
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#objdump: -dw
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#name: x86_64 ENQCMD[S] insns
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#source: x86-64-enqcmd.s
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.*: +file format .*
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@ -15,10 +13,8 @@ Disassembly of section \.text:
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+[a-f0-9]+: 67 f3 0f 38 f8 01 enqcmds \(%ecx\),%eax
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+[a-f0-9]+: f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%rip\),%rcx #.*
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+[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%eip\),%ecx #.*
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+[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%eip\),%ecx #.*
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+[a-f0-9]+: f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%rip\),%rcx #.*
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+[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%eip\),%ecx #.*
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+[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%eip\),%ecx #.*
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+[a-f0-9]+: 67 f2 0f 38 f8 0c 25 00 00 00 00 enqcmd 0x0\(,%eiz,1\),%ecx
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+[a-f0-9]+: 67 f2 0f 38 f8 0c 25 78 56 34 12 enqcmd 0x12345678\(,%eiz,1\),%ecx
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+[a-f0-9]+: 67 f3 0f 38 f8 0c 25 00 00 00 00 enqcmds 0x0\(,%eiz,1\),%ecx
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@ -29,10 +25,8 @@ Disassembly of section \.text:
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+[a-f0-9]+: 67 f3 0f 38 f8 01 enqcmds \(%ecx\),%eax
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+[a-f0-9]+: f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%rip\),%rcx #.*
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+[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%eip\),%ecx #.*
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+[a-f0-9]+: 67 f2 0f 38 f8 0d 00 00 00 00 enqcmd 0x0\(%eip\),%ecx #.*
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+[a-f0-9]+: f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%rip\),%rcx #.*
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+[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%eip\),%ecx #.*
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+[a-f0-9]+: 67 f3 0f 38 f8 0d 00 00 00 00 enqcmds 0x0\(%eip\),%ecx #.*
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+[a-f0-9]+: 67 f2 0f 38 f8 0c 25 00 00 00 00 enqcmd 0x0\(,%eiz,1\),%ecx
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+[a-f0-9]+: 67 f2 0f 38 f8 0c 25 78 56 34 12 enqcmd 0x12345678\(,%eiz,1\),%ecx
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+[a-f0-9]+: 67 f3 0f 38 f8 0c 25 00 00 00 00 enqcmds 0x0\(,%eiz,1\),%ecx
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@ -8,10 +8,8 @@ _start:
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enqcmds (%rcx),%rax
|
||||
enqcmds (%ecx),%eax
|
||||
enqcmd foo(%rip),%rcx
|
||||
enqcmd foo(%rip),%ecx
|
||||
enqcmd foo(%eip),%ecx
|
||||
enqcmds foo(%rip),%rcx
|
||||
enqcmds foo(%rip),%ecx
|
||||
enqcmds foo(%eip),%ecx
|
||||
enqcmd foo, %ecx
|
||||
enqcmd 0x12345678, %ecx
|
||||
@ -24,10 +22,8 @@ _start:
|
||||
enqcmds rax,[rcx]
|
||||
enqcmds eax,[ecx]
|
||||
enqcmd rcx,[rip+foo]
|
||||
enqcmd ecx,[rip+foo]
|
||||
enqcmd ecx,[eip+foo]
|
||||
enqcmds rcx,[rip+foo]
|
||||
enqcmds ecx,[rip+foo]
|
||||
enqcmds ecx,[eip+foo]
|
||||
enqcmd ecx,ds:foo
|
||||
enqcmd ecx,ds:0x12345678
|
||||
|
||||
@ -1,4 +1,3 @@
|
||||
#as:
|
||||
#objdump: -dw -Mintel
|
||||
#name: x86_64 MOVDIR[I,64B] insns (Intel disassembly)
|
||||
#source: x86-64-movdir.s
|
||||
@ -14,7 +13,6 @@ Disassembly of section \.text:
|
||||
+[a-f0-9]+: 67 66 0f 38 f8 01 movdir64b eax,\[ecx\]
|
||||
+[a-f0-9]+: 66 0f 38 f8 0d 00 00 00 00 movdir64b rcx,\[rip\+0x0\] #.*
|
||||
+[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b ecx,\[eip\+0x0\] #.*
|
||||
+[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b ecx,\[eip\+0x0\] #.*
|
||||
+[a-f0-9]+: 67 66 0f 38 f8 0c 25 00 00 00 00 movdir64b ecx,\[eiz\*1\+0x0\]
|
||||
+[a-f0-9]+: 67 66 0f 38 f8 0c 25 78 56 34 12 movdir64b ecx,\[eiz\*1\+0x12345678\]
|
||||
+[a-f0-9]+: 0f 38 f9 01 movdiri DWORD PTR \[rcx\],eax
|
||||
@ -25,7 +23,6 @@ Disassembly of section \.text:
|
||||
+[a-f0-9]+: 67 66 0f 38 f8 01 movdir64b eax,\[ecx\]
|
||||
+[a-f0-9]+: 66 0f 38 f8 0d 00 00 00 00 movdir64b rcx,\[rip\+0x0\] #.*
|
||||
+[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b ecx,\[eip\+0x0\] #.*
|
||||
+[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b ecx,\[eip\+0x0\] #.*
|
||||
+[a-f0-9]+: 67 66 0f 38 f8 0c 25 00 00 00 00 movdir64b ecx,\[eiz\*1\+0x0\]
|
||||
+[a-f0-9]+: 67 66 0f 38 f8 0c 25 78 56 34 12 movdir64b ecx,\[eiz\*1\+0x12345678\]
|
||||
#pass
|
||||
|
||||
@ -1,7 +1,5 @@
|
||||
#as:
|
||||
#objdump: -dw
|
||||
#name: x86_64 MOVDIR[I,64B] insns
|
||||
#source: x86-64-movdir.s
|
||||
|
||||
.*: +file format .*
|
||||
|
||||
@ -14,7 +12,6 @@ Disassembly of section \.text:
|
||||
+[a-f0-9]+: 67 66 0f 38 f8 01 movdir64b \(%ecx\),%eax
|
||||
+[a-f0-9]+: 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%rip\),%rcx #.*
|
||||
+[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%eip\),%ecx #.*
|
||||
+[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%eip\),%ecx #.*
|
||||
+[a-f0-9]+: 67 66 0f 38 f8 0c 25 00 00 00 00 movdir64b 0x0\(,%eiz,1\),%ecx
|
||||
+[a-f0-9]+: 67 66 0f 38 f8 0c 25 78 56 34 12 movdir64b 0x12345678\(,%eiz,1\),%ecx
|
||||
+[a-f0-9]+: 0f 38 f9 01 movdiri %eax,\(%rcx\)
|
||||
@ -25,7 +22,6 @@ Disassembly of section \.text:
|
||||
+[a-f0-9]+: 67 66 0f 38 f8 01 movdir64b \(%ecx\),%eax
|
||||
+[a-f0-9]+: 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%rip\),%rcx #.*
|
||||
+[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%eip\),%ecx #.*
|
||||
+[a-f0-9]+: 67 66 0f 38 f8 0d 00 00 00 00 movdir64b 0x0\(%eip\),%ecx #.*
|
||||
+[a-f0-9]+: 67 66 0f 38 f8 0c 25 00 00 00 00 movdir64b 0x0\(,%eiz,1\),%ecx
|
||||
+[a-f0-9]+: 67 66 0f 38 f8 0c 25 78 56 34 12 movdir64b 0x12345678\(,%eiz,1\),%ecx
|
||||
#pass
|
||||
|
||||
@ -7,7 +7,6 @@ _start:
|
||||
movdir64b (%rcx),%rax
|
||||
movdir64b (%ecx),%eax
|
||||
movdir64b foo(%rip),%rcx
|
||||
movdir64b foo(%rip),%ecx
|
||||
movdir64b foo(%eip),%ecx
|
||||
movdir64b foo, %ecx
|
||||
movdir64b 0x12345678, %ecx
|
||||
@ -20,7 +19,6 @@ _start:
|
||||
movdir64b rax,[rcx]
|
||||
movdir64b eax,[ecx]
|
||||
movdir64b rcx,[rip+foo]
|
||||
movdir64b ecx,[rip+foo]
|
||||
movdir64b ecx,[eip+foo]
|
||||
movdir64b ecx,ds:foo
|
||||
movdir64b ecx,ds:0x12345678
|
||||
|
||||
@ -1,5 +1,7 @@
|
||||
.*: Assembler messages:
|
||||
.*:6: Error: invalid register operand size for `movdir64b'
|
||||
.*:7: Error: invalid register operand size for `movdir64b'
|
||||
.*:10: Error: invalid register operand size for `movdir64b'
|
||||
.*:11: Error: invalid register operand size for `movdir64b'
|
||||
.*:8: Error: invalid register operand size for `movdir64b'
|
||||
.*:9: Error: invalid register operand size for `movdir64b'
|
||||
.*:12: Error: invalid register operand size for `movdir64b'
|
||||
.*:13: Error: invalid register operand size for `movdir64b'
|
||||
|
||||
@ -4,7 +4,9 @@
|
||||
.text
|
||||
_start:
|
||||
movdir64b (%esi),%rax
|
||||
movdir64b (%eip),%rax
|
||||
movdir64b (%rsi),%eax
|
||||
movdir64b (%rip),%eax
|
||||
|
||||
.intel_syntax noprefix
|
||||
movdir64b rax,[esi]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user