[PATCH 37/57][Arm][OBJDUMP] Add framework for MVE instructions
opcodes/ChangeLog: 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> Michael Collison <michael.collison@arm.com> * arm-dis.c (enum mve_instructions): New enum. (enum mve_unpredictable): Likewise. (enum mve_undefined): Likewise. (struct mopcode32): New struct. (is_mve_okay_in_it): New function. (is_mve_architecture): Likewise. (arm_decode_field): Likewise. (arm_decode_field_multiple): Likewise. (is_mve_encoding_conflict): Likewise. (is_mve_undefined): Likewise. (is_mve_unpredictable): Likewise. (print_mve_undefined): Likewise. (print_mve_unpredictable): Likewise. (print_insn_coprocessor_1): Use arm_decode_field_multiple. (print_insn_mve): New function. (print_insn_thumb32): Handle MVE architecture. (select_arm_features): Force thumb for Armv8.1-m Mainline.
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Andre Vieira
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@ -1,3 +1,24 @@
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2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
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Michael Collison <michael.collison@arm.com>
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* arm-dis.c (enum mve_instructions): New enum.
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(enum mve_unpredictable): Likewise.
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(enum mve_undefined): Likewise.
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(struct mopcode32): New struct.
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(is_mve_okay_in_it): New function.
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(is_mve_architecture): Likewise.
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(arm_decode_field): Likewise.
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(arm_decode_field_multiple): Likewise.
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(is_mve_encoding_conflict): Likewise.
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(is_mve_undefined): Likewise.
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(is_mve_unpredictable): Likewise.
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(print_mve_undefined): Likewise.
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(print_mve_unpredictable): Likewise.
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(print_insn_coprocessor_1): Use arm_decode_field_multiple.
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(print_insn_mve): New function.
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(print_insn_thumb32): Handle MVE architecture.
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(select_arm_features): Force thumb for Armv8.1-m Mainline.
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2019-05-10 Nick Clifton <nickc@redhat.com>
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PR 24538
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@ -67,6 +67,23 @@ struct arm_private_data
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bfd_vma last_mapping_addr;
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};
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enum mve_instructions
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{
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MVE_NONE
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};
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enum mve_unpredictable
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{
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UNPRED_IT_BLOCK, /* Unpredictable because mve insn in it block.
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*/
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UNPRED_NONE /* No unpredictable behavior. */
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};
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enum mve_undefined
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{
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UNDEF_NONE /* no undefined behavior. */
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};
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struct opcode32
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{
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arm_feature_set arch; /* Architecture defining this insn. */
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@ -75,6 +92,18 @@ struct opcode32
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const char * assembler; /* How to disassemble this insn. */
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};
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/* MVE opcodes. */
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struct mopcode32
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{
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arm_feature_set arch; /* Architecture defining this insn. */
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enum mve_instructions mve_op; /* Specific mve instruction for faster
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decoding. */
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unsigned long value; /* If arch is 0 then value is a sentinel. */
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unsigned long mask; /* Recognise insn if (op & mask) == value. */
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const char * assembler; /* How to disassemble this insn. */
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};
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enum isa {
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ANY,
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T32,
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@ -1746,6 +1775,18 @@ static const struct opcode32 neon_opcodes[] =
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{ARM_FEATURE_CORE_LOW (0), 0 ,0, 0}
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};
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/* mve opcode table. */
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/* print_insn_mve recognizes the following format control codes:
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%% %
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*/
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static const struct mopcode32 mve_opcodes[] =
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{
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};
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/* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
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ordered: they must be searched linearly from the top to obtain a correct
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match. */
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@ -3439,6 +3480,105 @@ arm_decode_shift (long given, fprintf_ftype func, void *stream,
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}
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}
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/* Return TRUE if the MATCHED_INSN can be inside an IT block. */
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static bfd_boolean
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is_mve_okay_in_it (enum mve_instructions matched_insn)
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{
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return FALSE;
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}
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static bfd_boolean
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is_mve_architecture (struct disassemble_info *info)
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{
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struct arm_private_data *private_data = info->private_data;
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arm_feature_set allowed_arches = private_data->features;
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arm_feature_set arm_ext_v8_1m_main
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= ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN);
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if (ARM_CPU_HAS_FEATURE (arm_ext_v8_1m_main, allowed_arches)
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&& !ARM_CPU_IS_ANY (allowed_arches))
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return TRUE;
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else
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return FALSE;
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}
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/* Decode a bitfield from opcode GIVEN, with starting bitfield = START
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and ending bitfield = END. END must be greater than START. */
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static unsigned long
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arm_decode_field (unsigned long given, unsigned int start, unsigned int end)
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{
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int bits = end - start;
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if (bits < 0)
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abort ();
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return ((given >> start) & ((2ul << bits) - 1));
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}
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/* Decode a bitfield from opcode GIVEN, with multiple bitfields:
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START:END and START2:END2. END/END2 must be greater than
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START/START2. */
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static unsigned long
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arm_decode_field_multiple (unsigned long given, unsigned int start,
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unsigned int end, unsigned int start2,
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unsigned int end2)
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{
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int bits = end - start;
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int bits2 = end2 - start2;
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unsigned long value = 0;
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int width = 0;
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if (bits2 < 0)
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abort ();
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value = arm_decode_field (given, start, end);
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width += bits + 1;
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value |= ((given >> start2) & ((2ul << bits2) - 1)) << width;
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return value;
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}
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/* Return TRUE if the GIVEN encoding should not be decoded as MATCHED_INSN.
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This helps us decode instructions that change mnemonic depending on specific
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operand values/encodings. */
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static bfd_boolean
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is_mve_encoding_conflict (unsigned long given,
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enum mve_instructions matched_insn)
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{
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return FALSE;
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}
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/* Return FALSE if GIVEN is not an undefined encoding for MATCHED_INSN.
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Otherwise, return TRUE and set UNDEFINED_CODE to give a reason as to why
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this encoding is undefined. */
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static bfd_boolean
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is_mve_undefined (unsigned long given, enum mve_instructions matched_insn,
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enum mve_undefined *undefined_code)
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{
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*undefined_code = UNDEF_NONE;
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return FALSE;
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}
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/* Return FALSE if GIVEN is not an unpredictable encoding for MATCHED_INSN.
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Otherwise, return TRUE and set UNPREDICTABLE_CODE to give a reason as to
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why this encoding is unpredictable. */
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static bfd_boolean
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is_mve_unpredictable (unsigned long given, enum mve_instructions matched_insn,
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enum mve_unpredictable *unpredictable_code)
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{
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*unpredictable_code = UNPRED_NONE;
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return FALSE;
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}
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#define W_BIT 21
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#define I_BIT 22
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#define U_BIT 23
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@ -3449,6 +3589,43 @@ arm_decode_shift (long given, fprintf_ftype func, void *stream,
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#define NEGATIVE_BIT_SET ((given & (1 << U_BIT)) == 0)
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#define PRE_BIT_SET (given & (1 << P_BIT))
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static void
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print_mve_undefined (struct disassemble_info *info,
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enum mve_undefined undefined_code)
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{
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void *stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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func (stream, "\t\tundefined instruction: ");
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switch (undefined_code)
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{
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case UNDEF_NONE:
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break;
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}
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}
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static void
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print_mve_unpredictable (struct disassemble_info *info,
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enum mve_unpredictable unpredict_code)
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{
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void *stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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func (stream, "%s: ", UNPREDICTABLE_INSTRUCTION);
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switch (unpredict_code)
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{
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case UNPRED_IT_BLOCK:
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func (stream, "mve instruction in it block");
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break;
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case UNPRED_NONE:
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break;
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}
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}
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/* Print one coprocessor instruction on INFO->STREAM.
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Return TRUE if the instuction matched, FALSE if this is not a
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recognised coprocessor instruction. */
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@ -3726,7 +3903,8 @@ print_insn_coprocessor (bfd_vma pc,
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case 'J':
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{
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int regno = ((given >> 19) & 0x8) | ((given >> 13) & 0x7);
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unsigned long regno
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= arm_decode_field_multiple (given, 13, 15, 22, 22);
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switch (regno)
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{
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@ -3749,7 +3927,7 @@ print_insn_coprocessor (bfd_vma pc,
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func (stream, "FPCXTS");
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break;
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default:
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func (stream, "<invalid reg %d>", regno);
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func (stream, "<invalid reg %lu>", regno);
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break;
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}
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}
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@ -4743,6 +4921,75 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb)
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return FALSE;
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}
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/* Print one mve instruction on INFO->STREAM.
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Return TRUE if the instuction matched, FALSE if this is not a
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recognised mve instruction. */
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static bfd_boolean
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print_insn_mve (struct disassemble_info *info, long given)
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{
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const struct mopcode32 *insn;
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void *stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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for (insn = mve_opcodes; insn->assembler; insn++)
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{
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if (((given & insn->mask) == insn->value)
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&& !is_mve_encoding_conflict (given, insn->mve_op))
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{
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signed long value_in_comment = 0;
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bfd_boolean is_unpredictable = FALSE;
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bfd_boolean is_undefined = FALSE;
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const char *c;
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enum mve_unpredictable unpredictable_cond = UNPRED_NONE;
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enum mve_undefined undefined_cond = UNDEF_NONE;
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/* Most vector mve instruction are illegal in a it block.
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There are a few exceptions; check for them. */
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if (ifthen_state && !is_mve_okay_in_it (insn->mve_op))
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{
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is_unpredictable = TRUE;
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unpredictable_cond = UNPRED_IT_BLOCK;
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}
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else if (is_mve_unpredictable (given, insn->mve_op,
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&unpredictable_cond))
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is_unpredictable = TRUE;
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if (is_mve_undefined (given, insn->mve_op, &undefined_cond))
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is_undefined = TRUE;
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for (c = insn->assembler; *c; c++)
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{
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if (*c == '%')
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{
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switch (*++c)
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{
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case '%':
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func (stream, "%%");
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break;
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}
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}
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else
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func (stream, "%c", *c);
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}
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if (value_in_comment > 32 || value_in_comment < -16)
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func (stream, "\t; 0x%lx", value_in_comment);
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if (is_unpredictable)
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print_mve_unpredictable (info, unpredictable_cond);
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if (is_undefined)
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print_mve_undefined (info, undefined_cond);
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return TRUE;
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}
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}
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return FALSE;
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}
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/* Return the name of a v7A special register. */
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static const char *
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@ -5653,11 +5900,15 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given)
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const struct opcode32 *insn;
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void *stream = info->stream;
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fprintf_ftype func = info->fprintf_func;
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bfd_boolean is_mve = is_mve_architecture (info);
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if (print_insn_coprocessor (pc, info, given, TRUE))
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return;
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if (print_insn_neon (info, given, TRUE))
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if ((is_mve == FALSE) && print_insn_neon (info, given, TRUE))
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return;
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if (is_mve && print_insn_mve (info, given))
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return;
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for (insn = thumb32_opcodes; insn->assembler; insn++)
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@ -6764,7 +7015,10 @@ select_arm_features (unsigned long mach,
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case bfd_mach_arm_8R: ARM_SET_FEATURES (ARM_ARCH_V8R); break;
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case bfd_mach_arm_8M_BASE: ARM_SET_FEATURES (ARM_ARCH_V8M_BASE); break;
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case bfd_mach_arm_8M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8M_MAIN); break;
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case bfd_mach_arm_8_1M_MAIN: ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN); break;
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case bfd_mach_arm_8_1M_MAIN:
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ARM_SET_FEATURES (ARM_ARCH_V8_1M_MAIN);
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force_thumb = 1;
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break;
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/* If the machine type is unknown allow all architecture types and all
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extensions. */
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case bfd_mach_arm_unknown: ARM_SET_FEATURES (ARM_FEATURE_ALL); break;
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