Add support for ARM v6 instructions.
* Makefile.in (SIM_EXTRA_CFLAGS): Add -lm. * armdefs.h (ARMdval, ARMfval): New types. (ARM_VFP_reg): New union. (struct ARMul_State): Add VFP_Reg and FPSCR fields. (VFP_fval, VFP_uword, VFP_sword, VFP_dval, VFP_dword): Accessor macros for the new VFP_Reg field. * armemu.c (handle_v6_insn): Add code to handle MOVW, MOVT, QADD16, QASX, QSAX, QSUB16, QADD8, QSUB8, UADD16, USUB16, UADD8, USUB8, SEL, REV, REV16, RBIT, BFC, BFI, SBFX and UBFX instructions. (handle_VFP_move): New function. (ARMul_Emulate16): Add checks for newly supported v6 instructions. Add support for VMRS, VMOV and MRC instructions. (Multiply64): Allow nRdHi == nRm and/or nRdLo == nRm when operating in v6 mode. * armemu.h (t_resolved): Define. * armsupp.c: Include math.h. (handle_VFP_xfer): New function. Handles VMOV, VSTM, VSTR, VPUSH, VSTM, VLDM and VPOP instructions. (ARMul_LDC): Test for co-processor 10 or 11 and pass call to the new handle_VFP_xfer function. (ARMul_STC): Likewise. (handle_VFP_op): New function. Handles VMLA, VMLS, VNMLA, VNMLS, VNMUL, VMUL, VADD, VSUB, VDIV, VMOV, VABS, VNEG, VSQRT, VCMP, VCMPE and VCVT instructions. (ARMul_CDP): Test for co-processor 10 or 11 and pass call to the new handle_VFP_op function. * thumbemu.c (tBIT, tBITS, ntBIT, ntBITS): New macros. (test_cond): New function. Tests a condition and returns non-zero if the condition has been met. (handle_IT_block): New function. (in_IT_block): New function. (IT_block_allow): New function. (ThumbExpandImm): New function. (handle_T2_insn): New function. Handles T2 thumb instructions. (handle_v6_thumb_insn): Add next_instr and pc parameters. (ARMul_ThumbDecode): Add support for IT blocks. Add support for v6 instructions. * wrapper.c (sim_create_inferior): Detect a thumb address and call SETT appropriately.
This commit is contained in:
Nick Clifton
parent
ee0c0c503d
commit
73cb0348b2
@ -1,3 +1,46 @@
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2015-06-28 Nick Clifton <nickc@redhat.com>
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* Makefile.in (SIM_EXTRA_CFLAGS): Add -lm.
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* armdefs.h (ARMdval, ARMfval): New types.
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(ARM_VFP_reg): New union.
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(struct ARMul_State): Add VFP_Reg and FPSCR fields.
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(VFP_fval, VFP_uword, VFP_sword, VFP_dval, VFP_dword): Accessor
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macros for the new VFP_Reg field.
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* armemu.c (handle_v6_insn): Add code to handle MOVW, MOVT,
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QADD16, QASX, QSAX, QSUB16, QADD8, QSUB8, UADD16, USUB16, UADD8,
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USUB8, SEL, REV, REV16, RBIT, BFC, BFI, SBFX and UBFX
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instructions.
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(handle_VFP_move): New function.
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(ARMul_Emulate16): Add checks for newly supported v6
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instructions. Add support for VMRS, VMOV and MRC instructions.
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(Multiply64): Allow nRdHi == nRm and/or nRdLo == nRm when
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operating in v6 mode.
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* armemu.h (t_resolved): Define.
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* armsupp.c: Include math.h.
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(handle_VFP_xfer): New function. Handles VMOV, VSTM, VSTR, VPUSH,
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VSTM, VLDM and VPOP instructions.
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(ARMul_LDC): Test for co-processor 10 or 11 and pass call to the
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new handle_VFP_xfer function.
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(ARMul_STC): Likewise.
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(handle_VFP_op): New function. Handles VMLA, VMLS, VNMLA, VNMLS,
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VNMUL, VMUL, VADD, VSUB, VDIV, VMOV, VABS, VNEG, VSQRT, VCMP,
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VCMPE and VCVT instructions.
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(ARMul_CDP): Test for co-processor 10 or 11 and pass call to the
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new handle_VFP_op function.
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* thumbemu.c (tBIT, tBITS, ntBIT, ntBITS): New macros.
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(test_cond): New function. Tests a condition and returns non-zero
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if the condition has been met.
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(handle_IT_block): New function.
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(in_IT_block): New function.
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(IT_block_allow): New function.
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(ThumbExpandImm): New function.
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(handle_T2_insn): New function. Handles T2 thumb instructions.
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(handle_v6_thumb_insn): Add next_instr and pc parameters.
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(ARMul_ThumbDecode): Add support for IT blocks. Add support for
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v6 instructions.
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* wrapper.c (sim_create_inferior): Detect a thumb address and call
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SETT appropriately.
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2015-06-23 Mike Frysinger <vapier@gentoo.org>
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* configure: Regenerate.
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@ -17,7 +17,7 @@
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## COMMON_PRE_CONFIG_FRAG
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SIM_EXTRA_CFLAGS = -DMODET
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SIM_EXTRA_CFLAGS = -DMODET -lm
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SIM_OBJS = \
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wrapper.o \
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@ -49,6 +49,25 @@ typedef unsigned ARMul_CPReads (ARMul_State * state, unsigned reg,
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typedef unsigned ARMul_CPWrites (ARMul_State * state, unsigned reg,
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ARMword value);
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typedef double ARMdval; /* FIXME: Must be a 64-bit floating point type. */
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typedef float ARMfval; /* FIXME: Must be a 32-bit floating point type. */
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typedef union
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{
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ARMword uword[2];
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ARMsword sword[2];
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ARMfval fval[2];
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ARMdword dword;
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ARMdval dval;
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} ARM_VFP_reg;
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#define VFP_fval(N) (state->VFP_Reg[(N)>> 1].fval[(N) & 1])
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#define VFP_uword(N) (state->VFP_Reg[(N)>> 1].uword[(N) & 1])
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#define VFP_sword(N) (state->VFP_Reg[(N)>> 1].sword[(N) & 1])
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#define VFP_dval(N) (state->VFP_Reg[(N)].dval)
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#define VFP_dword(N) (state->VFP_Reg[(N)].dword)
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struct ARMul_State
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{
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ARMword Emulate; /* to start and stop emulation */
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@ -138,6 +157,9 @@ struct ARMul_State
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unsigned is_iWMMXt; /* Are we emulating an iWMMXt co-processor ? */
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unsigned is_ep9312; /* Are we emulating a Cirrus Maverick co-processor ? */
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unsigned verbose; /* Print various messages like the banner */
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ARM_VFP_reg VFP_Reg[32]; /* Advanced SIMD registers. */
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ARMword FPSCR; /* Floating Point Status Register. */
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};
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#define ResetPin NresetSig
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990
sim/arm/armemu.c
990
sim/arm/armemu.c
File diff suppressed because it is too large
Load Diff
@ -462,6 +462,8 @@ typedef enum
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}
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tdstate;
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#define t_resolved t_branch
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/* Macros to scrutinize instructions. The dummy do loop is to keep the compiler
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happy when the statement is used in an otherwise empty else statement. */
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#define UNDEF_Test do { ; } while (0)
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@ -840,8 +840,7 @@ ARMul_OSHandleSWI (ARMul_State * state, ARMword number)
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break;
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case 17: /* Utime. */
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state->Reg[0] = (ARMword) sim_callback->time (sim_callback,
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(long *) state->Reg[1]);
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state->Reg[0] = state->Reg[1] = (ARMword) sim_callback->time (sim_callback, NULL);
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OSptr->ErrorNo = sim_callback->get_errno (sim_callback);
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break;
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@ -1,22 +1,23 @@
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/* armsupp.c -- ARMulator support code: ARM6 Instruction Emulator.
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Copyright (C) 1994 Advanced RISC Machines Ltd.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>. */
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#include "armdefs.h"
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#include "armemu.h"
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#include "ansidecl.h"
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#include <math.h>
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/* Definitions for the support routines. */
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@ -173,7 +174,7 @@ void
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ARMul_SetSPSR (ARMul_State * state, ARMword mode, ARMword value)
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{
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ARMword bank = ModeToBank (mode & MODEBITS);
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if (BANK_CAN_ACCESS_SPSR (bank))
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state->Spsr[bank] = value;
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}
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@ -208,12 +209,12 @@ ARMul_CPSRAltered (ARMul_State * state)
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state->Cpsr &= (CCBITS | INTBITS | R15MODEBITS);
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oldmode = state->Mode;
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if (state->Mode != (state->Cpsr & MODEBITS))
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{
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state->Mode =
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ARMul_SwitchMode (state, state->Mode, state->Cpsr & MODEBITS);
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state->NtransSig = (state->Mode & 3) ? HIGH : LOW;
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}
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state->Cpsr &= ~MODEBITS;
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@ -291,10 +292,10 @@ ARMul_SwitchMode (ARMul_State * state, ARMword oldmode, ARMword newmode)
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unsigned i;
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ARMword oldbank;
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ARMword newbank;
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oldbank = ModeToBank (oldmode);
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newbank = state->Bank = ModeToBank (newmode);
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/* Do we really need to do it? */
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if (oldbank != newbank)
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{
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@ -323,7 +324,7 @@ ARMul_SwitchMode (ARMul_State * state, ARMword oldmode, ARMword newmode)
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default:
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abort ();
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}
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/* Restore the new registers. */
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switch (newbank)
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{
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@ -350,7 +351,7 @@ ARMul_SwitchMode (ARMul_State * state, ARMword oldmode, ARMword newmode)
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abort ();
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}
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}
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return newmode;
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}
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@ -466,6 +467,422 @@ ARMul_SubOverflow (ARMul_State * state, ARMword a, ARMword b, ARMword result)
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ASSIGNV (SubOverflow (a, b, result));
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}
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static void
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handle_VFP_xfer (ARMul_State * state, ARMword instr)
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{
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if (TOPBITS (28) == NV)
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{
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fprintf (stderr, "SIM: UNDEFINED VFP instruction\n");
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return;
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}
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if (BITS (25, 27) != 0x6)
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{
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fprintf (stderr, "SIM: ISE: VFP handler called incorrectly\n");
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return;
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}
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switch (BITS (20, 24))
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{
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case 0x04:
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case 0x05:
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{
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/* VMOV double precision to/from two ARM registers. */
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int vm = BITS (0, 3);
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int rt1 = BITS (12, 15);
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int rt2 = BITS (16, 19);
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/* FIXME: UNPREDICTABLE if rt1 == 15 or rt2 == 15. */
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if (BIT (20))
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{
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/* Transfer to ARM. */
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/* FIXME: UPPREDICTABLE if rt1 == rt2. */
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state->Reg[rt1] = VFP_dword (vm) & 0xffffffff;
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state->Reg[rt2] = VFP_dword (vm) >> 32;
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}
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else
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{
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VFP_dword (vm) = state->Reg[rt2];
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VFP_dword (vm) <<= 32;
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VFP_dword (vm) |= (state->Reg[rt1] & 0xffffffff);
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}
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return;
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}
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case 0x08:
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case 0x0A:
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case 0x0C:
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case 0x0E:
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{
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/* VSTM with PUW=011 or PUW=010. */
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int n = BITS (16, 19);
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int imm8 = BITS (0, 7);
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ARMword address = state->Reg[n];
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if (BIT (21))
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state->Reg[n] = address + (imm8 << 2);
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if (BIT (8))
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{
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int src = (BIT (22) << 4) | BITS (12, 15);
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imm8 >>= 1;
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while (imm8--)
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{
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if (state->bigendSig)
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{
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ARMul_StoreWordN (state, address, VFP_dword (src) >> 32);
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ARMul_StoreWordN (state, address + 4, VFP_dword (src));
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}
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else
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{
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ARMul_StoreWordN (state, address, VFP_dword (src));
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ARMul_StoreWordN (state, address + 4, VFP_dword (src) >> 32);
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}
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address += 8;
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src += 1;
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}
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}
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else
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{
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int src = (BITS (12, 15) << 1) | BIT (22);
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while (imm8--)
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{
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ARMul_StoreWordN (state, address, VFP_uword (src));
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address += 4;
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src += 1;
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}
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}
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}
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return;
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case 0x10:
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case 0x14:
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case 0x18:
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case 0x1C:
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{
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/* VSTR */
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ARMword imm32 = BITS (0, 7) << 2;
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int base = state->Reg[LHSReg];
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ARMword address;
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int dest;
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if (LHSReg == 15)
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base = (base + 3) & ~3;
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address = base + (BIT (23) ? imm32 : - imm32);
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if (CPNum == 10)
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{
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dest = (DESTReg << 1) + BIT (22);
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ARMul_StoreWordN (state, address, VFP_uword (dest));
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}
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else
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{
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dest = (BIT (22) << 4) + DESTReg;
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if (state->bigendSig)
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{
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ARMul_StoreWordN (state, address, VFP_dword (dest) >> 32);
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ARMul_StoreWordN (state, address + 4, VFP_dword (dest));
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}
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else
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{
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ARMul_StoreWordN (state, address, VFP_dword (dest));
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ARMul_StoreWordN (state, address + 4, VFP_dword (dest) >> 32);
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}
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}
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}
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return;
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case 0x12:
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case 0x16:
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if (BITS (16, 19) == 13)
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{
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/* VPUSH */
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ARMword address = state->Reg[13] - (BITS (0, 7) << 2);
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state->Reg[13] = address;
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if (BIT (8))
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{
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int dreg = (BIT (22) << 4) | BITS (12, 15);
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int num = BITS (0, 7) >> 1;
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while (num--)
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{
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if (state->bigendSig)
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{
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ARMul_StoreWordN (state, address, VFP_dword (dreg) >> 32);
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ARMul_StoreWordN (state, address + 4, VFP_dword (dreg));
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}
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else
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{
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ARMul_StoreWordN (state, address, VFP_dword (dreg));
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ARMul_StoreWordN (state, address + 4, VFP_dword (dreg) >> 32);
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}
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address += 8;
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dreg += 1;
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}
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||||
}
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else
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{
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int sreg = (BITS (12, 15) << 1) | BIT (22);
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int num = BITS (0, 7);
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||||
while (num--)
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{
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ARMul_StoreWordN (state, address, VFP_uword (sreg));
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address += 4;
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sreg += 1;
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||||
}
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||||
}
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||||
}
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else if (BITS (9, 11) != 0x5)
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break;
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||||
else
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||||
{
|
||||
/* VSTM PUW=101 */
|
||||
int n = BITS (16, 19);
|
||||
int imm8 = BITS (0, 7);
|
||||
ARMword address = state->Reg[n] - (imm8 << 2);
|
||||
state->Reg[n] = address;
|
||||
|
||||
if (BIT (8))
|
||||
{
|
||||
int src = (BIT (22) << 4) | BITS (12, 15);
|
||||
|
||||
imm8 >>= 1;
|
||||
while (imm8--)
|
||||
{
|
||||
if (state->bigendSig)
|
||||
{
|
||||
ARMul_StoreWordN (state, address, VFP_dword (src) >> 32);
|
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ARMul_StoreWordN (state, address + 4, VFP_dword (src));
|
||||
}
|
||||
else
|
||||
{
|
||||
ARMul_StoreWordN (state, address, VFP_dword (src));
|
||||
ARMul_StoreWordN (state, address + 4, VFP_dword (src) >> 32);
|
||||
}
|
||||
address += 8;
|
||||
src += 1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
int src = (BITS (12, 15) << 1) | BIT (22);
|
||||
|
||||
while (imm8--)
|
||||
{
|
||||
ARMul_StoreWordN (state, address, VFP_uword (src));
|
||||
address += 4;
|
||||
src += 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
return;
|
||||
|
||||
case 0x13:
|
||||
case 0x17:
|
||||
/* VLDM PUW=101 */
|
||||
case 0x09:
|
||||
case 0x0D:
|
||||
/* VLDM PUW=010 */
|
||||
{
|
||||
int n = BITS (16, 19);
|
||||
int imm8 = BITS (0, 7);
|
||||
|
||||
ARMword address = state->Reg[n];
|
||||
if (BIT (23) == 0)
|
||||
address -= imm8 << 2;
|
||||
if (BIT (21))
|
||||
state->Reg[n] = BIT (23) ? address + (imm8 << 2) : address;
|
||||
|
||||
if (BIT (8))
|
||||
{
|
||||
int dest = (BIT (22) << 4) | BITS (12, 15);
|
||||
imm8 >>= 1;
|
||||
while (imm8--)
|
||||
{
|
||||
if (state->bigendSig)
|
||||
{
|
||||
VFP_dword (dest) = ARMul_LoadWordN (state, address);
|
||||
VFP_dword (dest) <<= 32;
|
||||
VFP_dword (dest) |= ARMul_LoadWordN (state, address + 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
VFP_dword (dest) = ARMul_LoadWordN (state, address + 4);
|
||||
VFP_dword (dest) <<= 32;
|
||||
VFP_dword (dest) |= ARMul_LoadWordN (state, address);
|
||||
}
|
||||
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VLDM: D%d = %g\n", dest, VFP_dval (dest));
|
||||
|
||||
address += 8;
|
||||
dest += 1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
int dest = (BITS (12, 15) << 1) | BIT (22);
|
||||
|
||||
while (imm8--)
|
||||
{
|
||||
VFP_uword (dest) = ARMul_LoadWordN (state, address);
|
||||
address += 4;
|
||||
dest += 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
return;
|
||||
|
||||
case 0x0B:
|
||||
case 0x0F:
|
||||
if (BITS (16, 19) == 13)
|
||||
{
|
||||
/* VPOP */
|
||||
ARMword address = state->Reg[13];
|
||||
state->Reg[13] = address + (BITS (0, 7) << 2);
|
||||
|
||||
if (BIT (8))
|
||||
{
|
||||
int dest = (BIT (22) << 4) | BITS (12, 15);
|
||||
int num = BITS (0, 7) >> 1;
|
||||
|
||||
while (num--)
|
||||
{
|
||||
if (state->bigendSig)
|
||||
{
|
||||
VFP_dword (dest) = ARMul_LoadWordN (state, address);
|
||||
VFP_dword (dest) <<= 32;
|
||||
VFP_dword (dest) |= ARMul_LoadWordN (state, address + 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
VFP_dword (dest) = ARMul_LoadWordN (state, address + 4);
|
||||
VFP_dword (dest) <<= 32;
|
||||
VFP_dword (dest) |= ARMul_LoadWordN (state, address);
|
||||
}
|
||||
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VPOP: D%d = %g\n", dest, VFP_dval (dest));
|
||||
|
||||
address += 8;
|
||||
dest += 1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
int sreg = (BITS (12, 15) << 1) | BIT (22);
|
||||
int num = BITS (0, 7);
|
||||
|
||||
while (num--)
|
||||
{
|
||||
VFP_uword (sreg) = ARMul_LoadWordN (state, address);
|
||||
address += 4;
|
||||
sreg += 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (BITS (9, 11) != 0x5)
|
||||
break;
|
||||
else
|
||||
{
|
||||
/* VLDM PUW=011 */
|
||||
int n = BITS (16, 19);
|
||||
int imm8 = BITS (0, 7);
|
||||
ARMword address = state->Reg[n];
|
||||
state->Reg[n] += imm8 << 2;
|
||||
|
||||
if (BIT (8))
|
||||
{
|
||||
int dest = (BIT (22) << 4) | BITS (12, 15);
|
||||
|
||||
imm8 >>= 1;
|
||||
while (imm8--)
|
||||
{
|
||||
if (state->bigendSig)
|
||||
{
|
||||
VFP_dword (dest) = ARMul_LoadWordN (state, address);
|
||||
VFP_dword (dest) <<= 32;
|
||||
VFP_dword (dest) |= ARMul_LoadWordN (state, address + 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
VFP_dword (dest) = ARMul_LoadWordN (state, address + 4);
|
||||
VFP_dword (dest) <<= 32;
|
||||
VFP_dword (dest) |= ARMul_LoadWordN (state, address);
|
||||
}
|
||||
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VLDM: D%d = %g\n", dest, VFP_dval (dest));
|
||||
|
||||
address += 8;
|
||||
dest += 1;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
int dest = (BITS (12, 15) << 1) | BIT (22);
|
||||
while (imm8--)
|
||||
{
|
||||
VFP_uword (dest) = ARMul_LoadWordN (state, address);
|
||||
address += 4;
|
||||
dest += 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
return;
|
||||
|
||||
case 0x11:
|
||||
case 0x15:
|
||||
case 0x19:
|
||||
case 0x1D:
|
||||
{
|
||||
/* VLDR */
|
||||
ARMword imm32 = BITS (0, 7) << 2;
|
||||
int base = state->Reg[LHSReg];
|
||||
ARMword address;
|
||||
int dest;
|
||||
|
||||
if (LHSReg == 15)
|
||||
base = (base + 3) & ~3;
|
||||
|
||||
address = base + (BIT (23) ? imm32 : - imm32);
|
||||
|
||||
if (CPNum == 10)
|
||||
{
|
||||
dest = (DESTReg << 1) + BIT (22);
|
||||
|
||||
VFP_uword (dest) = ARMul_LoadWordN (state, address);
|
||||
}
|
||||
else
|
||||
{
|
||||
dest = (BIT (22) << 4) + DESTReg;
|
||||
|
||||
if (state->bigendSig)
|
||||
{
|
||||
VFP_dword (dest) = ARMul_LoadWordN (state, address);
|
||||
VFP_dword (dest) <<= 32;
|
||||
VFP_dword (dest) |= ARMul_LoadWordN (state, address + 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
VFP_dword (dest) = ARMul_LoadWordN (state, address + 4);
|
||||
VFP_dword (dest) <<= 32;
|
||||
VFP_dword (dest) |= ARMul_LoadWordN (state, address);
|
||||
}
|
||||
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VLDR: D%d = %g\n", dest, VFP_dval (dest));
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
fprintf (stderr, "SIM: VFP: Unimplemented: %0x\n", BITS (20, 24));
|
||||
}
|
||||
|
||||
/* This function does the work of generating the addresses used in an
|
||||
LDC instruction. The code here is always post-indexed, it's up to the
|
||||
caller to get the input address correct and to handle base register
|
||||
@ -477,6 +894,12 @@ ARMul_LDC (ARMul_State * state, ARMword instr, ARMword address)
|
||||
unsigned cpab;
|
||||
ARMword data;
|
||||
|
||||
if (CPNum == 10 || CPNum == 11)
|
||||
{
|
||||
handle_VFP_xfer (state, instr);
|
||||
return;
|
||||
}
|
||||
|
||||
UNDEF_LSCPCBaseWb;
|
||||
|
||||
if (! CP_ACCESS_ALLOWED (state, CPNum))
|
||||
@ -537,6 +960,12 @@ ARMul_STC (ARMul_State * state, ARMword instr, ARMword address)
|
||||
unsigned cpab;
|
||||
ARMword data;
|
||||
|
||||
if (CPNum == 10 || CPNum == 11)
|
||||
{
|
||||
handle_VFP_xfer (state, instr);
|
||||
return;
|
||||
}
|
||||
|
||||
UNDEF_LSCPCBaseWb;
|
||||
|
||||
if (! CP_ACCESS_ALLOWED (state, CPNum))
|
||||
@ -666,6 +1095,454 @@ ARMul_MRC (ARMul_State * state, ARMword instr)
|
||||
return result;
|
||||
}
|
||||
|
||||
static void
|
||||
handle_VFP_op (ARMul_State * state, ARMword instr)
|
||||
{
|
||||
int dest;
|
||||
int srcN;
|
||||
int srcM;
|
||||
|
||||
if (BITS (9, 11) != 0x5 || BIT (4) != 0)
|
||||
{
|
||||
fprintf (stderr, "SIM: VFP: Unimplemented: Float op: %08x\n", BITS (0,31));
|
||||
return;
|
||||
}
|
||||
|
||||
if (BIT (8))
|
||||
{
|
||||
dest = BITS(12,15) + (BIT (22) << 4);
|
||||
srcN = LHSReg + (BIT (7) << 4);
|
||||
srcM = BITS (0,3) + (BIT (5) << 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
dest = (BITS(12,15) << 1) + BIT (22);
|
||||
srcN = (LHSReg << 1) + BIT (7);
|
||||
srcM = (BITS (0,3) << 1) + BIT (5);
|
||||
}
|
||||
|
||||
switch (BITS (20, 27))
|
||||
{
|
||||
case 0xE0:
|
||||
case 0xE4:
|
||||
/* VMLA VMLS */
|
||||
if (BIT (8))
|
||||
{
|
||||
ARMdval val = VFP_dval (srcN) * VFP_dval (srcM);
|
||||
|
||||
if (BIT (6))
|
||||
{
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VMLS: %g = %g - %g * %g\n",
|
||||
VFP_dval (dest) - val,
|
||||
VFP_dval (dest), VFP_dval (srcN), VFP_dval (srcM));
|
||||
VFP_dval (dest) -= val;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VMLA: %g = %g + %g * %g\n",
|
||||
VFP_dval (dest) + val,
|
||||
VFP_dval (dest), VFP_dval (srcN), VFP_dval (srcM));
|
||||
VFP_dval (dest) += val;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
ARMfval val = VFP_fval (srcN) * VFP_fval (srcM);
|
||||
|
||||
if (BIT (6))
|
||||
{
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VMLS: %g = %g - %g * %g\n",
|
||||
VFP_fval (dest) - val,
|
||||
VFP_fval (dest), VFP_fval (srcN), VFP_fval (srcM));
|
||||
VFP_fval (dest) -= val;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VMLA: %g = %g + %g * %g\n",
|
||||
VFP_fval (dest) + val,
|
||||
VFP_fval (dest), VFP_fval (srcN), VFP_fval (srcM));
|
||||
VFP_fval (dest) += val;
|
||||
}
|
||||
}
|
||||
return;
|
||||
|
||||
case 0xE1:
|
||||
case 0xE5:
|
||||
if (BIT (8))
|
||||
{
|
||||
ARMdval product = VFP_dval (srcN) * VFP_dval (srcM);
|
||||
|
||||
if (BIT (6))
|
||||
{
|
||||
/* VNMLA */
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VNMLA: %g = -(%g + (%g * %g))\n",
|
||||
-(VFP_dval (dest) + product),
|
||||
VFP_dval (dest), VFP_dval (srcN), VFP_dval (srcM));
|
||||
VFP_dval (dest) = -(product + VFP_dval (dest));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* VNMLS */
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VNMLS: %g = -(%g + (%g * %g))\n",
|
||||
-(VFP_dval (dest) + product),
|
||||
VFP_dval (dest), VFP_dval (srcN), VFP_dval (srcM));
|
||||
VFP_dval (dest) = product - VFP_dval (dest);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
ARMfval product = VFP_fval (srcN) * VFP_fval (srcM);
|
||||
|
||||
if (BIT (6))
|
||||
/* VNMLA */
|
||||
VFP_fval (dest) = -(product + VFP_fval (dest));
|
||||
else
|
||||
/* VNMLS */
|
||||
VFP_fval (dest) = product - VFP_fval (dest);
|
||||
}
|
||||
return;
|
||||
|
||||
case 0xE2:
|
||||
case 0xE6:
|
||||
if (BIT (8))
|
||||
{
|
||||
ARMdval product = VFP_dval (srcN) * VFP_dval (srcM);
|
||||
|
||||
if (BIT (6))
|
||||
{
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VMUL: %g = %g * %g\n",
|
||||
- product, VFP_dval (srcN), VFP_dval (srcM));
|
||||
/* VNMUL */
|
||||
VFP_dval (dest) = - product;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VMUL: %g = %g * %g\n",
|
||||
product, VFP_dval (srcN), VFP_dval (srcM));
|
||||
/* VMUL */
|
||||
VFP_dval (dest) = product;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
ARMfval product = VFP_fval (srcN) * VFP_fval (srcM);
|
||||
|
||||
if (BIT (6))
|
||||
{
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VNMUL: %g = %g * %g\n",
|
||||
- product, VFP_fval (srcN), VFP_fval (srcM));
|
||||
|
||||
VFP_fval (dest) = - product;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VMUL: %g = %g * %g\n",
|
||||
product, VFP_fval (srcN), VFP_fval (srcM));
|
||||
|
||||
VFP_fval (dest) = product;
|
||||
}
|
||||
}
|
||||
return;
|
||||
|
||||
case 0xE3:
|
||||
case 0xE7:
|
||||
if (BIT (6) == 0)
|
||||
{
|
||||
/* VADD */
|
||||
if (BIT(8))
|
||||
{
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VADD %g = %g + %g\n",
|
||||
VFP_dval (srcN) + VFP_dval (srcM),
|
||||
VFP_dval (srcN),
|
||||
VFP_dval (srcM));
|
||||
VFP_dval (dest) = VFP_dval (srcN) + VFP_dval (srcM);
|
||||
}
|
||||
else
|
||||
VFP_fval (dest) = VFP_fval (srcN) + VFP_fval (srcM);
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
/* VSUB */
|
||||
if (BIT(8))
|
||||
{
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VSUB %g = %g - %g\n",
|
||||
VFP_dval (srcN) - VFP_dval (srcM),
|
||||
VFP_dval (srcN),
|
||||
VFP_dval (srcM));
|
||||
VFP_dval (dest) = VFP_dval (srcN) - VFP_dval (srcM);
|
||||
}
|
||||
else
|
||||
VFP_fval (dest) = VFP_fval (srcN) - VFP_fval (srcM);
|
||||
}
|
||||
return;
|
||||
|
||||
case 0xE8:
|
||||
case 0xEC:
|
||||
if (BIT (6) == 1)
|
||||
break;
|
||||
|
||||
/* VDIV */
|
||||
if (BIT (8))
|
||||
{
|
||||
ARMdval res = VFP_dval (srcN) / VFP_dval (srcM);
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VDIV (64bit): %g = %g / %g\n",
|
||||
res, VFP_dval (srcN), VFP_dval (srcM));
|
||||
VFP_dval (dest) = res;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VDIV: %g = %g / %g\n",
|
||||
VFP_fval (srcN) / VFP_fval (srcM),
|
||||
VFP_fval (srcN), VFP_fval (srcM));
|
||||
|
||||
VFP_fval (dest) = VFP_fval (srcN) / VFP_fval (srcM);
|
||||
}
|
||||
return;
|
||||
|
||||
case 0xEB:
|
||||
case 0xEF:
|
||||
if (BIT (6) != 1)
|
||||
break;
|
||||
|
||||
switch (BITS (16, 19))
|
||||
{
|
||||
case 0x0:
|
||||
if (BIT (7) == 0)
|
||||
{
|
||||
if (BIT (8))
|
||||
{
|
||||
/* VMOV.F64 <Dd>, <Dm>. */
|
||||
VFP_dval (dest) = VFP_dval (srcM);
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VMOV d%d, d%d: %g\n", dest, srcM, VFP_dval (srcM));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* VMOV.F32 <Sd>, <Sm>. */
|
||||
VFP_fval (dest) = VFP_fval (srcM);
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VMOV s%d, s%d: %g\n", dest, srcM, VFP_fval (srcM));
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* VABS */
|
||||
if (BIT (8))
|
||||
{
|
||||
ARMdval src = VFP_dval (srcM);
|
||||
|
||||
VFP_dval (dest) = fabs (src);
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VABS (%g) = %g\n", src, VFP_dval (dest));
|
||||
}
|
||||
else
|
||||
{
|
||||
ARMfval src = VFP_fval (srcM);
|
||||
|
||||
VFP_fval (dest) = fabsf (src);
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VABS (%g) = %g\n", src, VFP_fval (dest));
|
||||
}
|
||||
}
|
||||
return;
|
||||
|
||||
case 0x1:
|
||||
if (BIT (7) == 0)
|
||||
{
|
||||
/* VNEG */
|
||||
if (BIT (8))
|
||||
VFP_dval (dest) = - VFP_dval (srcM);
|
||||
else
|
||||
VFP_fval (dest) = - VFP_fval (srcM);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* VSQRT */
|
||||
if (BIT (8))
|
||||
{
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: %g = root(%g)\n",
|
||||
sqrt (VFP_dval (srcM)), VFP_dval (srcM));
|
||||
|
||||
VFP_dval (dest) = sqrt (VFP_dval (srcM));
|
||||
}
|
||||
else
|
||||
{
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: %g = root(%g)\n",
|
||||
sqrtf (VFP_fval (srcM)), VFP_fval (srcM));
|
||||
|
||||
VFP_fval (dest) = sqrtf (VFP_fval (srcM));
|
||||
}
|
||||
}
|
||||
return;
|
||||
|
||||
case 0x4:
|
||||
case 0x5:
|
||||
/* VCMP, VCMPE */
|
||||
if (BIT(8))
|
||||
{
|
||||
ARMdval res = VFP_dval (dest);
|
||||
|
||||
if (BIT (16) == 0)
|
||||
{
|
||||
ARMdval src = VFP_dval (srcM);
|
||||
|
||||
if (isinf (res) && isinf (src))
|
||||
{
|
||||
if (res > 0.0 && src > 0.0)
|
||||
res = 0.0;
|
||||
else if (res < 0.0 && src < 0.0)
|
||||
res = 0.0;
|
||||
/* else leave res alone. */
|
||||
}
|
||||
else
|
||||
res -= src;
|
||||
}
|
||||
|
||||
/* FIXME: Add handling of signalling NaNs and the E bit. */
|
||||
|
||||
state->FPSCR &= 0x0FFFFFFF;
|
||||
if (res < 0.0)
|
||||
state->FPSCR |= NBIT;
|
||||
else
|
||||
state->FPSCR |= CBIT;
|
||||
if (res == 0.0)
|
||||
state->FPSCR |= ZBIT;
|
||||
if (isnan (res))
|
||||
state->FPSCR |= VBIT;
|
||||
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VCMP (64bit) %g vs %g res %g, flags: %c%c%c%c\n",
|
||||
VFP_dval (dest), BIT (16) ? 0.0 : VFP_dval (srcM), res,
|
||||
state->FPSCR & NBIT ? 'N' : '-',
|
||||
state->FPSCR & ZBIT ? 'Z' : '-',
|
||||
state->FPSCR & CBIT ? 'C' : '-',
|
||||
state->FPSCR & VBIT ? 'V' : '-');
|
||||
}
|
||||
else
|
||||
{
|
||||
ARMfval res = VFP_fval (dest);
|
||||
|
||||
if (BIT (16) == 0)
|
||||
{
|
||||
ARMfval src = VFP_fval (srcM);
|
||||
|
||||
if (isinf (res) && isinf (src))
|
||||
{
|
||||
if (res > 0.0 && src > 0.0)
|
||||
res = 0.0;
|
||||
else if (res < 0.0 && src < 0.0)
|
||||
res = 0.0;
|
||||
/* else leave res alone. */
|
||||
}
|
||||
else
|
||||
res -= src;
|
||||
}
|
||||
|
||||
/* FIXME: Add handling of signalling NaNs and the E bit. */
|
||||
|
||||
state->FPSCR &= 0x0FFFFFFF;
|
||||
if (res < 0.0)
|
||||
state->FPSCR |= NBIT;
|
||||
else
|
||||
state->FPSCR |= CBIT;
|
||||
if (res == 0.0)
|
||||
state->FPSCR |= ZBIT;
|
||||
if (isnan (res))
|
||||
state->FPSCR |= VBIT;
|
||||
|
||||
if (trace)
|
||||
fprintf (stderr, " VFP: VCMP (32bit) %g vs %g res %g, flags: %c%c%c%c\n",
|
||||
VFP_fval (dest), BIT (16) ? 0.0 : VFP_fval (srcM), res,
|
||||
state->FPSCR & NBIT ? 'N' : '-',
|
||||
state->FPSCR & ZBIT ? 'Z' : '-',
|
||||
state->FPSCR & CBIT ? 'C' : '-',
|
||||
state->FPSCR & VBIT ? 'V' : '-');
|
||||
}
|
||||
return;
|
||||
|
||||
case 0x7:
|
||||
if (BIT (8))
|
||||
{
|
||||
dest = (DESTReg << 1) + BIT (22);
|
||||
VFP_fval (dest) = VFP_dval (srcM);
|
||||
}
|
||||
else
|
||||
{
|
||||
dest = DESTReg + (BIT (22) << 4);
|
||||
VFP_dval (dest) = VFP_fval (srcM);
|
||||
}
|
||||
return;
|
||||
|
||||
case 0x8:
|
||||
case 0xC:
|
||||
case 0xD:
|
||||
/* VCVT integer <-> FP */
|
||||
if (BIT (18))
|
||||
{
|
||||
/* To integer. */
|
||||
if (BIT (8))
|
||||
{
|
||||
dest = (BITS(12,15) << 1) + BIT (22);
|
||||
if (BIT (16))
|
||||
VFP_sword (dest) = VFP_dval (srcM);
|
||||
else
|
||||
VFP_uword (dest) = VFP_dval (srcM);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (BIT (16))
|
||||
VFP_sword (dest) = VFP_fval (srcM);
|
||||
else
|
||||
VFP_uword (dest) = VFP_fval (srcM);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* From integer. */
|
||||
if (BIT (8))
|
||||
{
|
||||
srcM = (BITS (0,3) << 1) + BIT (5);
|
||||
if (BIT (7))
|
||||
VFP_dval (dest) = VFP_sword (srcM);
|
||||
else
|
||||
VFP_dval (dest) = VFP_uword (srcM);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (BIT (7))
|
||||
VFP_fval (dest) = VFP_sword (srcM);
|
||||
else
|
||||
VFP_fval (dest) = VFP_uword (srcM);
|
||||
}
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
fprintf (stderr, "SIM: VFP: Unimplemented: Float op3: %03x\n", BITS (16,27));
|
||||
return;
|
||||
}
|
||||
|
||||
fprintf (stderr, "SIM: VFP: Unimplemented: Float op2: %02x\n", BITS (20, 27));
|
||||
return;
|
||||
}
|
||||
|
||||
/* This function does the Busy-Waiting for an CDP instruction. */
|
||||
|
||||
void
|
||||
@ -673,6 +1550,12 @@ ARMul_CDP (ARMul_State * state, ARMword instr)
|
||||
{
|
||||
unsigned cpab;
|
||||
|
||||
if (CPNum == 10 || CPNum == 11)
|
||||
{
|
||||
handle_VFP_op (state, instr);
|
||||
return;
|
||||
}
|
||||
|
||||
if (! CP_ACCESS_ALLOWED (state, CPNum))
|
||||
{
|
||||
ARMul_UndefInstr (state, instr);
|
||||
|
||||
2028
sim/arm/thumbemu.c
2028
sim/arm/thumbemu.c
File diff suppressed because it is too large
Load Diff
@ -257,6 +257,11 @@ sim_create_inferior (SIM_DESC sd ATTRIBUTE_UNUSED,
|
||||
mach = 0;
|
||||
}
|
||||
|
||||
#ifdef MODET
|
||||
if (abfd != NULL && (bfd_get_start_address (abfd) & 1))
|
||||
SETT;
|
||||
#endif
|
||||
|
||||
switch (mach)
|
||||
{
|
||||
default:
|
||||
@ -341,17 +346,6 @@ sim_create_inferior (SIM_DESC sd ATTRIBUTE_UNUSED,
|
||||
break;
|
||||
}
|
||||
|
||||
if ( mach != bfd_mach_arm_3
|
||||
&& mach != bfd_mach_arm_3M
|
||||
&& mach != bfd_mach_arm_2
|
||||
&& mach != bfd_mach_arm_2a)
|
||||
{
|
||||
/* Reset mode to ARM. A gdb user may rerun a program that had entered
|
||||
THUMB mode from the start and cause the ARM-mode startup code to be
|
||||
executed in THUMB mode. */
|
||||
ARMul_SetCPSR (state, SVC32MODE);
|
||||
}
|
||||
|
||||
memset (& info, 0, sizeof (info));
|
||||
INIT_DISASSEMBLE_INFO (info, stdout, op_printf);
|
||||
info.read_memory_func = sim_dis_read;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user