Add to the AArch64 GAS the missing support for hexadecimal-format
floating-point literal in the FMOV instruction. gas/ * config/tc-aarch64.c (aarch64_imm_float_p): Rename 'e' to 'pattern'; add comment. (aarch64_double_precision_fmovable): New function. (parse_aarch64_imm_float): Add parameter 'dp_p'; call the new function; handle hexadecimal representation of IEEE754 encoding. (parse_operands): Update the call to parse_aarch64_imm_float. gas/testsuite/ * gas/aarch64/diagnostic.s: Add test. * gas/aarch64/diagnostic.l: Update. * gas/aarch64/illegal.s: Add test. * gas/aarch64/illegal.l: Update. * gas/aarch64/fpmov.s: New file. * gas/aarch64/fpmov.d: New file.
This commit is contained in:
Yufeng Zhang
parent
334ad4a8e4
commit
62b0d0d5f3
@ -1,3 +1,12 @@
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2013-03-05 Yufeng Zhang <yufeng.zhang@arm.com>
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* config/tc-aarch64.c (aarch64_imm_float_p): Rename 'e' to 'pattern';
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add comment.
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(aarch64_double_precision_fmovable): New function.
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(parse_aarch64_imm_float): Add parameter 'dp_p'; call the new
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function; handle hexadecimal representation of IEEE754 encoding.
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(parse_operands): Update the call to parse_aarch64_imm_float.
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2013-02-28 H.J. Lu <hongjiu.lu@intel.com>
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* config/tc-i386.c (_i386_insn): Replace have_hle with hle_prefix.
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@ -1989,49 +1989,140 @@ encode_imm_float_bits (uint32_t imm)
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| ((imm >> (31 - 7)) & 0x80); /* b[31] -> b[7] */
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}
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/* Return TRUE if IMM is a valid floating-point immediate; return FALSE
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otherwise. */
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/* Return TRUE if the single-precision floating-point value encoded in IMM
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can be expressed in the AArch64 8-bit signed floating-point format with
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3-bit exponent and normalized 4 bits of precision; in other words, the
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floating-point value must be expressable as
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(+/-) n / 16 * power (2, r)
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where n and r are integers such that 16 <= n <=31 and -3 <= r <= 4. */
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static bfd_boolean
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aarch64_imm_float_p (uint32_t imm)
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{
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/* 3 32222222 2221111111111
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1 09876543 21098765432109876543210
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n Eeeeeexx xxxx0000000000000000000 */
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uint32_t e;
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/* If a single-precision floating-point value has the following bit
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pattern, it can be expressed in the AArch64 8-bit floating-point
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format:
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e = (imm >> 30) & 0x1;
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if (e == 0)
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e = 0x3e000000;
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3 32222222 2221111111111
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1 09876543 21098765432109876543210
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n Eeeeeexx xxxx0000000000000000000
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where n, e and each x are either 0 or 1 independently, with
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E == ~ e. */
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uint32_t pattern;
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/* Prepare the pattern for 'Eeeeee'. */
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if (((imm >> 30) & 0x1) == 0)
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pattern = 0x3e000000;
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else
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e = 0x40000000;
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return (imm & 0x7ffff) == 0 /* lower 19 bits are 0 */
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&& ((imm & 0x7e000000) == e); /* bits 25-29 = ~ bit 30 */
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pattern = 0x40000000;
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return (imm & 0x7ffff) == 0 /* lower 19 bits are 0. */
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&& ((imm & 0x7e000000) == pattern); /* bits 25 - 29 == ~ bit 30. */
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}
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/* Note: this accepts the floating-point 0 constant. */
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/* Like aarch64_imm_float_p but for a double-precision floating-point value.
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Return TRUE if the value encoded in IMM can be expressed in the AArch64
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8-bit signed floating-point format with 3-bit exponent and normalized 4
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bits of precision (i.e. can be used in an FMOV instruction); return the
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equivalent single-precision encoding in *FPWORD.
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Otherwise return FALSE. */
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static bfd_boolean
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parse_aarch64_imm_float (char **ccp, int *immed)
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aarch64_double_precision_fmovable (uint64_t imm, uint32_t *fpword)
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{
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/* If a double-precision floating-point value has the following bit
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pattern, it can be expressed in the AArch64 8-bit floating-point
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format:
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6 66655555555 554444444...21111111111
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3 21098765432 109876543...098765432109876543210
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n Eeeeeeeeexx xxxx00000...000000000000000000000
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where n, e and each x are either 0 or 1 independently, with
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E == ~ e. */
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uint32_t pattern;
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uint32_t high32 = imm >> 32;
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/* Lower 32 bits need to be 0s. */
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if ((imm & 0xffffffff) != 0)
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return FALSE;
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/* Prepare the pattern for 'Eeeeeeeee'. */
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if (((high32 >> 30) & 0x1) == 0)
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pattern = 0x3fc00000;
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else
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pattern = 0x40000000;
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if ((high32 & 0xffff) == 0 /* bits 32 - 47 are 0. */
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&& (high32 & 0x7fc00000) == pattern) /* bits 54 - 61 == ~ bit 62. */
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{
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/* Convert to the single-precision encoding.
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i.e. convert
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n Eeeeeeeeexx xxxx00000...000000000000000000000
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to
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n Eeeeeexx xxxx0000000000000000000. */
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*fpword = ((high32 & 0xfe000000) /* nEeeeee. */
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| (((high32 >> 16) & 0x3f) << 19)); /* xxxxxx. */
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return TRUE;
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}
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else
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return FALSE;
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}
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/* Parse a floating-point immediate. Return TRUE on success and return the
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value in *IMMED in the format of IEEE754 single-precision encoding.
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*CCP points to the start of the string; DP_P is TRUE when the immediate
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is expected to be in double-precision (N.B. this only matters when
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hexadecimal representation is involved).
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N.B. 0.0 is accepted by this function. */
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static bfd_boolean
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parse_aarch64_imm_float (char **ccp, int *immed, bfd_boolean dp_p)
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{
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char *str = *ccp;
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char *fpnum;
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LITTLENUM_TYPE words[MAX_LITTLENUMS];
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int found_fpchar = 0;
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int64_t val = 0;
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unsigned fpword = 0;
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bfd_boolean hex_p = FALSE;
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skip_past_char (&str, '#');
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/* We must not accidentally parse an integer as a floating-point number. Make
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sure that the value we parse is not an integer by checking for special
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characters '.' or 'e'.
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FIXME: This is a hack that is not very efficient, but doing better is
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tricky because type information isn't in a very usable state at parse
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time. */
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fpnum = str;
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skip_whitespace (fpnum);
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if (strncmp (fpnum, "0x", 2) == 0)
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return FALSE;
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{
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/* Support the hexadecimal representation of the IEEE754 encoding.
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Double-precision is expected when DP_P is TRUE, otherwise the
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representation should be in single-precision. */
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if (! parse_constant_immediate (&str, &val))
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goto invalid_fp;
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if (dp_p)
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{
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if (! aarch64_double_precision_fmovable (val, &fpword))
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goto invalid_fp;
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}
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else if ((uint64_t) val > 0xffffffff)
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goto invalid_fp;
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else
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fpword = val;
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hex_p = TRUE;
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}
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else
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{
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/* We must not accidentally parse an integer as a floating-point number.
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Make sure that the value we parse is not an integer by checking for
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special characters '.' or 'e'. */
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for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
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if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
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{
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@ -2043,25 +2134,25 @@ parse_aarch64_imm_float (char **ccp, int *immed)
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return FALSE;
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}
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if ((str = atof_ieee (str, 's', words)) != NULL)
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if (! hex_p)
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{
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unsigned fpword = 0;
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int i;
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if ((str = atof_ieee (str, 's', words)) == NULL)
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goto invalid_fp;
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/* Our FP word must be 32 bits (single-precision FP). */
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for (i = 0; i < 32 / LITTLENUM_NUMBER_OF_BITS; i++)
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{
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fpword <<= LITTLENUM_NUMBER_OF_BITS;
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fpword |= words[i];
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}
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}
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if (aarch64_imm_float_p (fpword) || (fpword & 0x7fffffff) == 0)
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*immed = fpword;
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else
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goto invalid_fp;
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if (aarch64_imm_float_p (fpword) || (fpword & 0x7fffffff) == 0)
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{
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*immed = fpword;
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*ccp = str;
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return TRUE;
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}
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@ -4691,7 +4782,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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bfd_boolean res1 = FALSE, res2 = FALSE;
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/* N.B. -0.0 will be rejected; although -0.0 shouldn't be rejected,
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it is probably not worth the effort to support it. */
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if (!(res1 = parse_aarch64_imm_float (&str, &qfloat))
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if (!(res1 = parse_aarch64_imm_float (&str, &qfloat, FALSE))
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&& !(res2 = parse_constant_immediate (&str, &val)))
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goto failure;
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if ((res1 && qfloat == 0) || (res2 && val == 0))
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@ -4752,7 +4843,10 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_SIMD_FPIMM:
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{
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int qfloat;
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if (! parse_aarch64_imm_float (&str, &qfloat))
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bfd_boolean dp_p
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= (aarch64_get_qualifier_esize (inst.base.operands[0].qualifier)
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== 8);
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if (! parse_aarch64_imm_float (&str, &qfloat, dp_p))
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goto failure;
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if (qfloat == 0)
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{
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@ -1,3 +1,12 @@
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2013-03-05 Yufeng Zhang <yufeng.zhang@arm.com>
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* gas/aarch64/diagnostic.s: Add test.
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* gas/aarch64/diagnostic.l: Update.
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* gas/aarch64/illegal.s: Add test.
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* gas/aarch64/illegal.l: Update.
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* gas/aarch64/fpmov.s: New file.
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* gas/aarch64/fpmov.d: New file.
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2013-03-01 H.J. Lu <hongjiu.lu@intel.com>
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* gas/i386/inval.s: Add tests for invalid addresses and eiz.
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@ -86,3 +86,4 @@
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[^:]*:88: Error: shift is not permitted at operand 2 -- `movi v1.2d,4294967295,lsl#0'
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[^:]*:89: Error: shift amount expected to be 0 at operand 2 -- `movi v1.8b,97,lsl#8'
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[^:]*:90: Error: unknown or missing system register name at operand 1 -- `msr dummy,x1'
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[^:]*:91: Error: invalid floating-point constant at operand 2 -- `fmov s0,0x42000000'
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@ -88,3 +88,4 @@
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movi v1.2d, 4294967295, lsl #0
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movi v1.8b, 97, lsl #8
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msr dummy, x1
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fmov s0, 0x42000000
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19
gas/testsuite/gas/aarch64/fpmov.d
Normal file
19
gas/testsuite/gas/aarch64/fpmov.d
Normal file
@ -0,0 +1,19 @@
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#objdump: -dr
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.*: file format .*
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Disassembly of section .*:
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0000000000000000 <.*>:
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0: 1e251000 fmov s0, #1\.200000000000000000e\+01
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4: 1e251000 fmov s0, #1\.200000000000000000e\+01
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8: 1e251000 fmov s0, #1\.200000000000000000e\+01
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c: 1e351000 fmov s0, #-1\.200000000000000000e\+01
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10: 1e351000 fmov s0, #-1\.200000000000000000e\+01
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14: 1e351000 fmov s0, #-1\.200000000000000000e\+01
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18: 1e751000 fmov d0, #-1\.200000000000000000e\+01
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1c: 1e751000 fmov d0, #-1\.200000000000000000e\+01
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20: 1e751000 fmov d0, #-1\.200000000000000000e\+01
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24: 1e69f000 fmov d0, #2\.421875000000000000e-01
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28: 1e69f000 fmov d0, #2\.421875000000000000e-01
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2c: 1e29f000 fmov s0, #2\.421875000000000000e-01
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17
gas/testsuite/gas/aarch64/fpmov.s
Normal file
17
gas/testsuite/gas/aarch64/fpmov.s
Normal file
@ -0,0 +1,17 @@
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// fpmov.s Test file for AArch64 floating-point move instructions.
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.text
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// fp mov immediate
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fmov s0, 12.0
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fmov s0, 1.2e1
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fmov s0, 0x41400000
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fmov s0, -12.0
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fmov s0, -1.2e1
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fmov s0, 0xc1400000
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fmov d0, -12.0
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fmov d0, -1.2e1
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fmov d0, 0xC028000000000000
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fmov d0, 0.2421875
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fmov d0, 0x3fcf000000000000
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fmov s0, 0x3e780000
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@ -548,4 +548,7 @@
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[^:]*:538: Error: .*`mov x0,##5'
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[^:]*:540: Error: .*`msr daifset,x0'
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[^:]*:541: Error: .*`msr daifclr,x0'
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[^:]*:546: Error: .*
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[^:]*:543: Error: .*`fmov s0,#0x11'
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[^:]*:544: Error: .*`fmov s0,#0xC0280000C1400000'
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[^:]*:545: Error: .*`fmov d0,#0xC02f800000000000'
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[^:]*:550: Error: .*
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@ -540,6 +540,10 @@
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msr daifset, x0
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msr daifclr, x0
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fmov s0, #0x11
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fmov s0, #0xC0280000C1400000
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fmov d0, #0xC02f800000000000
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// No 16-byte relocation
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ldr q0, =one_label
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