Fix tests for PR 18500, revisited
Correct commit a846e9c1.
PR gas/18500
* gas/arm/vfpv2-ldr_immediate.d: Use parentheses, not brackets,
to select alternatives.
* gas/arm/vfpv3-ldr_immediate.d: Likewise.
* gas/arm/vfpv3xd-ldr_immediate.d: Likewise.
This commit is contained in:
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@ -1,3 +1,11 @@
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2015-10-22 Alan Modra <amodra@gmail.com>
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PR gas/18500
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* gas/arm/vfpv2-ldr_immediate.d: Use parentheses, not brackets,
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to select alternatives.
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* gas/arm/vfpv3-ldr_immediate.d: Likewise.
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* gas/arm/vfpv3xd-ldr_immediate.d: Likewise.
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2015-10-21 Nick Clifton <nickc@redhat.com>
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PR gas/18500
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@ -8,43 +8,43 @@ Disassembly of section \.text:
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
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0[0-9a-fx]+ .*[00000000|3fbe0000] .*
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0[0-9a-fx]+ .*[3fbe0000|00000000] .*
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0[0-9a-fx]+ .*(00000000|3fbe0000) .*
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0[0-9a-fx]+ .*(3fbe0000|00000000) .*
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0[0-9a-fx]+ .*3df00000 .*
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.*
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
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0[0-9a-fx]+ .*[00000000|bfc00000] .*
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0[0-9a-fx]+ .*[bfc00000|00000000] .*
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0[0-9a-fx]+ .*(00000000|bfc00000) .*
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0[0-9a-fx]+ .*(bfc00000|00000000) .*
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0[0-9a-fx]+ .*be000000 .*
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.*
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
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0[0-9a-fx]+ .*[00000000|3fc00000] .*
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0[0-9a-fx]+ .*[3fc00000|00000000] .*
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0[0-9a-fx]+ .*(00000000|3fc00000) .*
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0[0-9a-fx]+ .*(3fc00000|00000000) .*
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0[0-9a-fx]+ .*3e000000 .*
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.*
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
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0[0-9a-fx]+ .*[00000000|3fe08000] .*
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0[0-9a-fx]+ .*[3fe08000|00000000] .*
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0[0-9a-fx]+ .*(00000000|3fe08000) .*
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0[0-9a-fx]+ .*(3fe08000|00000000) .*
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0[0-9a-fx]+ .*3f040000 .*
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.*
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
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0[0-9a-fx]+ .*[00000000|3fef0000] .*
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0[0-9a-fx]+ .*[3fef0000|00000000] .*
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0[0-9a-fx]+ .*(00000000|3fef0000) .*
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0[0-9a-fx]+ .*(3fef0000|00000000) .*
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0[0-9a-fx]+ .*3f780000 .*
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.*
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
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0[0-9a-fx]+ .*[00000000|403f0000] .*
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0[0-9a-fx]+ .*[403f0000|00000000] .*
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0[0-9a-fx]+ .*(00000000|403f0000) .*
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0[0-9a-fx]+ .*(403f0000|00000000) .*
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0[0-9a-fx]+ .*41f80000 .*
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.*
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
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0[0-9a-fx]+ .*[00000000|40400000] .*
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0[0-9a-fx]+ .*[40400000|00000000] .*
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0[0-9a-fx]+ .*(00000000|40400000) .*
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0[0-9a-fx]+ .*(40400000|00000000) .*
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0[0-9a-fx]+ .*42000000 .*
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#pass
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@ -8,8 +8,8 @@ Disassembly of section \.text:
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
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0[0-9a-fx]+ .*[00000000|3fbe0000] .*
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0[0-9a-fx]+ .*[3fbe0000|00000000] .*
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0[0-9a-fx]+ .*(00000000|3fbe0000) .*
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0[0-9a-fx]+ .*(3fbe0000|00000000) .*
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0[0-9a-fx]+ .*3df00000 .*
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.*
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@ -19,8 +19,8 @@ Disassembly of section \.text:
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0[0-9a-fx]+ .*eeb40a00 (vmov\.f32|fconsts) s0, #64.*
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
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0[0-9a-fx]+ .*[00000000|3fe08000] .*
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0[0-9a-fx]+ .*[3fe08000|00000000] .*
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0[0-9a-fx]+ .*(00000000|3fe08000) .*
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0[0-9a-fx]+ .*(3fe08000|00000000) .*
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0[0-9a-fx]+ .*3f040000 .*
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.*
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0[0-9a-fx]+ .*eeb60b0f (vmov\.f64|fconstd) d0, #111.*
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@ -29,7 +29,7 @@ Disassembly of section \.text:
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0[0-9a-fx]+ .*eeb30a0f (vmov\.f32|fconsts) s0, #63.*
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
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0[0-9a-fx]+ .*[00000000|40400000] .*
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0[0-9a-fx]+ .*[40400000|00000000] .*
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0[0-9a-fx]+ .*(00000000|40400000) .*
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0[0-9a-fx]+ .*(40400000|00000000) .*
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0[0-9a-fx]+ .*42000000 .*
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#pass
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@ -8,35 +8,35 @@ Disassembly of section \.text:
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
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0[0-9a-fx]+ .*[00000000|3fbe0000] .*
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0[0-9a-fx]+ .*[3fbe0000|00000000] .*
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0[0-9a-fx]+ .*(00000000|3fbe0000) .*
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0[0-9a-fx]+ .*(3fbe0000|00000000) .*
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0[0-9a-fx]+ .*3df00000 .*
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.*
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*eebc0a00 (vmov\.f32|fconsts) s0, #192.*
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0[0-9a-fx]+ .*[00000000|bfc00000] .*
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0[0-9a-fx]+ .*[bfc00000|00000000] .*
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0[0-9a-fx]+ .*(00000000|bfc00000) .*
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0[0-9a-fx]+ .*(bfc00000|00000000) .*
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*eeb40a00 (vmov\.f32|fconsts) s0, #64.*
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0[0-9a-fx]+ .*[00000000|3fc00000] .*
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0[0-9a-fx]+ .*[3fc00000|00000000] .*
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0[0-9a-fx]+ .*(00000000|3fc00000) .*
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0[0-9a-fx]+ .*(3fc00000|00000000) .*
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
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0[0-9a-fx]+ .*[00000000|3fe08000] .*
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0[0-9a-fx]+ .*[3fe08000|00000000] .*
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0[0-9a-fx]+ .*(00000000|3fe08000) .*
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0[0-9a-fx]+ .*(3fe08000|00000000) .*
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0[0-9a-fx]+ .*3f040000 .*
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.*
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*eeb60a0f (vmov\.f32|fconsts) s0, #111.*
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0[0-9a-fx]+ .*[00000000|3fef0000] .*
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0[0-9a-fx]+ .*[3fef0000|00000000] .*
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0[0-9a-fx]+ .*(00000000|3fef0000) .*
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0[0-9a-fx]+ .*(3fef0000|00000000) .*
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*eeb30a0f (vmov\.f32|fconsts) s0, #63.*
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0[0-9a-fx]+ .*[00000000|403f0000] .*
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0[0-9a-fx]+ .*[403f0000|00000000] .*
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0[0-9a-fx]+ .*(00000000|403f0000) .*
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0[0-9a-fx]+ .*(403f0000|00000000) .*
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0[0-9a-fx]+ .*ed9f0b00 vldr d0, \[pc\].*
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0[0-9a-fx]+ .*ed9f0a01 vldr s0, \[pc, #4\].*
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0[0-9a-fx]+ .*[00000000|40400000] .*
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0[0-9a-fx]+ .*[40400000|00000000] .*
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0[0-9a-fx]+ .*(00000000|40400000) .*
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0[0-9a-fx]+ .*(40400000|00000000) .*
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0[0-9a-fx]+ .*42000000 .*
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#pass
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