gold: Add endbr64 to IBT TLSDESC PLT entry
Gold generates: c10: ff 35 da 23 00 00 push 0x23da(%rip) # 2ff0 <_GLOBAL_OFFSET_TABLE_+0x8> c16: f2 ff 25 c3 23 00 00 bnd jmp *0x23c3(%rip) # 2fe0 <_DYNAMIC+0x260> c1d: 0f 1f 00 nopl (%rax) for IBT TLSDESC PLT entry which misses endbr64. Add endbr64 to generate: c10: f3 0f 1e fa endbr64 c14: ff 35 d6 23 00 00 push 0x23d6(%rip) # 2ff0 <_GLOBAL_OFFSET_TABLE_+0x8> c1a: ff 25 c0 23 00 00 jmp *0x23c0(%rip) # 2fe0 <_DYNAMIC+0x260> PR ld/26972 * x86_64.cc (Output_data_plt_x86_64_ibt::tlsdesc_plt_entry): Add endbr64. (Output_data_plt_x86_64_ibt::do_fill_tlsdesc_entry): Adjusted.
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@ -1,3 +1,10 @@
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2020-11-29 H.J. Lu <hongjiu.lu@intel.com>
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PR ld/26972
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* x86_64.cc (Output_data_plt_x86_64_ibt::tlsdesc_plt_entry): Add
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endbr64.
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(Output_data_plt_x86_64_ibt::do_fill_tlsdesc_entry): Adjusted.
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2020-11-29 H.J. Lu <hongjiu.lu@intel.com>
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PR gold/26939
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@ -2480,11 +2480,11 @@ Output_data_plt_x86_64_ibt<size>::tlsdesc_plt_entry[plt_entry_size] =
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{
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// From Alexandre Oliva, "Thread-Local Storage Descriptors for IA32
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// and AMD64/EM64T", Version 0.9.4 (2005-10-10).
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0xf3, 0x0f, 0x1e, 0xfa, // endbr64
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0xff, 0x35, // pushq x(%rip)
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0, 0, 0, 0, // replaced with address of linkmap GOT entry (at PLTGOT + 8)
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0xf2, 0xff, 0x25, // jmpq *y(%rip)
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0xff, 0x25, // jmpq *y(%rip)
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0, 0, 0, 0, // replaced with offset of reserved TLSDESC_GOT entry
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0x0f, 0x1f, 0 // nop
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};
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template<int size>
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@ -2498,15 +2498,15 @@ Output_data_plt_x86_64_ibt<size>::do_fill_tlsdesc_entry(
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unsigned int plt_offset)
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{
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memcpy(pov, tlsdesc_plt_entry, plt_entry_size);
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elfcpp::Swap_unaligned<32, false>::writeval(pov + 2,
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elfcpp::Swap_unaligned<32, false>::writeval(pov + 6,
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(got_address + 8
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- (plt_address + plt_offset
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+ 6)));
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elfcpp::Swap_unaligned<32, false>::writeval(pov + 9,
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+ 10)));
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elfcpp::Swap_unaligned<32, false>::writeval(pov + 12,
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(got_base
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+ tlsdesc_got_offset
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- (plt_address + plt_offset
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+ 13)));
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+ 16)));
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}
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// The .eh_frame unwind information for the PLT.
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