PPC64_OPT_LOCALENTRY is incompatible with tail calls
The save of r2 in __glink_PLTresolve is the culprit. Remove it, unless we know we need it for --plt-localentry. --plt-localentry should not be used with power10 pc-relative code that makes tail calls. The patch also removes use of r2 as a scratch reg in the ELFv2 __glink_PLTresolve. Using r2 isn't a problem, this is just reducing the number of scratch regs. bfd/ * elf64-ppc.c (GLINK_PLTRESOLVE_SIZE): Depend on has_plt_localentry0. (LD_R0_0R11, ADD_R11_R0_R11): Define. (ppc64_elf_tls_setup): Disable params->plt_localentry0 when power10 code detected. (ppc64_elf_size_stubs): Update __glink_PLTresolve eh_frame. (ppc64_elf_build_stubs): Move r2 save to start of __glink_PLTresolve, and only emit for has_plt_localentry0. Don't use r2 in the stub. ld/ * testsuite/ld-powerpc/elfv2so.d, * testsuite/ld-powerpc/notoc2.d, * testsuite/ld-powerpc/tlsdesc.wf, * testsuite/ld-powerpc/tlsdesc2.d, * testsuite/ld-powerpc/tlsdesc2.wf, * testsuite/ld-powerpc/tlsopt5.d, * testsuite/ld-powerpc/tlsopt5.wf, * testsuite/ld-powerpc/tlsopt6.d, * testsuite/ld-powerpc/tlsopt6.wf: Update __glink_PLTresolve.
This commit is contained in:
Alan Modra
parent
0be2fe677c
commit
3cd7c7d7ef
@ -1,3 +1,13 @@
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2020-09-26 Alan Modra <amodra@gmail.com>
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* elf64-ppc.c (GLINK_PLTRESOLVE_SIZE): Depend on has_plt_localentry0.
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(LD_R0_0R11, ADD_R11_R0_R11): Define.
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(ppc64_elf_tls_setup): Disable params->plt_localentry0 when power10
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code detected.
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(ppc64_elf_size_stubs): Update __glink_PLTresolve eh_frame.
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(ppc64_elf_build_stubs): Move r2 save to start of __glink_PLTresolve,
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and only emit for has_plt_localentry0. Don't use r2 in the stub.
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2020-09-24 Alan Modra <amodra@gmail.com>
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PR 26656
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@ -211,9 +211,10 @@ static bfd_vma opd_entry_value
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#define PLD_R12_PC 0x04100000e5800000ULL
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#define PNOP 0x0700000000000000ULL
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/* __glink_PLTresolve stub instructions. We enter with the index in R0. */
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/* __glink_PLTresolve stub instructions. We enter with the index in
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R0 for ELFv1, and the address of a glink branch in R12 for ELFv2. */
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#define GLINK_PLTRESOLVE_SIZE(htab) \
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(8u + (htab->opd_abi ? 11 * 4 : 14 * 4))
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(8u + (htab->opd_abi ? 11 * 4 : htab->has_plt_localentry0 ? 14 * 4 : 13 * 4))
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/* 0: */
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/* .quad plt0-1f */
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/* __glink: */
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@ -229,11 +230,14 @@ static bfd_vma opd_entry_value
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/* mtctr %12 */
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/* ld %11,16(%11) */
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/* bctr */
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#define MFLR_R0 0x7c0802a6 /* mflr %r0 */
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#define MTLR_R0 0x7c0803a6 /* mtlr %r0 */
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#define SUB_R12_R12_R11 0x7d8b6050 /* subf %r12,%r11,%r12 */
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#define ADDI_R0_R12 0x380c0000 /* addi %r0,%r12,0 */
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#define SRDI_R0_R0_2 0x7800f082 /* rldicl %r0,%r0,62,2 */
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#define MFLR_R0 0x7c0802a6 /* mflr %r0 */
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#define MTLR_R0 0x7c0803a6 /* mtlr %r0 */
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#define SUB_R12_R12_R11 0x7d8b6050 /* subf %r12,%r11,%r12 */
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#define ADDI_R0_R12 0x380c0000 /* addi %r0,%r12,0 */
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#define SRDI_R0_R0_2 0x7800f082 /* rldicl %r0,%r0,62,2 */
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#define LD_R0_0R11 0xe80b0000 /* ld %r0,0(%r11) */
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#define ADD_R11_R0_R11 0x7d605a14 /* add %r11,%r0,%r11 */
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/* Pad with this. */
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#define NOP 0x60000000
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@ -7736,6 +7740,19 @@ ppc64_elf_tls_setup (struct bfd_link_info *info)
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--plt-localentry can cause trouble. */
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if (htab->params->plt_localentry0 < 0)
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htab->params->plt_localentry0 = 0;
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if (htab->params->plt_localentry0 && htab->has_power10_relocs)
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{
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/* The issue is that __glink_PLTresolve saves r2, which is done
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because glibc ld.so _dl_runtime_resolve restores r2 to support
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a glibc plt call optimisation where global entry code is
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skipped on calls that resolve to the same binary. The
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__glink_PLTresolve save of r2 is incompatible with code
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making tail calls, because the tail call might go via the
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resolver and thus overwrite the proper saved r2. */
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_bfd_error_handler (_("warning: --plt-localentry is incompatible with "
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"power10 pc-relative code"));
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htab->params->plt_localentry0 = 0;
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}
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if (htab->params->plt_localentry0
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&& elf_link_hash_lookup (&htab->elf, "GLIBC_2.26",
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FALSE, FALSE, FALSE) == NULL)
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@ -13874,11 +13891,11 @@ ppc64_elf_size_stubs (struct bfd_link_info *info)
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/* Augmentation. */
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p += 1;
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*p++ = DW_CFA_advance_loc + 1;
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*p++ = DW_CFA_advance_loc + (htab->has_plt_localentry0 ? 3 : 2);
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*p++ = DW_CFA_register;
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*p++ = 65;
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*p++ = htab->opd_abi ? 12 : 0;
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*p++ = DW_CFA_advance_loc + (htab->opd_abi ? 5 : 7);
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*p++ = DW_CFA_advance_loc + (htab->opd_abi ? 4 : 2);
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*p++ = DW_CFA_restore_extended;
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*p++ = 65;
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p += ((24 + align - 1) & -align) - 24;
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@ -14474,23 +14491,60 @@ ppc64_elf_build_stubs (struct bfd_link_info *info,
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}
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else
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{
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unsigned int insn;
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/* 0:
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. .quad plt0-1f # plt0 entry relative to 1:
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#
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# We get here with r12 initially @ a glink branch
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# Load the address of _dl_runtime_resolve from plt0 and
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# jump to it, with r0 set to the index of the PLT entry
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# to be resolved and r11 the link map.
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__glink_PLTresolve:
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. std %r2,24(%r1) # optional
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. mflr %r0
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. bcl 20,31,1f
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1:
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. mflr %r11
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. mtlr %r0
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. ld %r0,(0b-1b)(%r11)
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. sub %r12,%r12,%r11
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. add %r11,%r0,%r11
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. addi %r0,%r12,1b-2f
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. ld %r12,0(%r11)
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. srdi %r0,%r0,2
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. mtctr %r12
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. ld %r11,8(%r11)
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. bctr
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2:
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. b __glink_PLTresolve
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. ...
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. b __glink_PLTresolve */
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if (htab->has_plt_localentry0)
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{
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bfd_put_32 (htab->glink->owner, STD_R2_0R1 + 24, p);
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p += 4;
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}
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bfd_put_32 (htab->glink->owner, MFLR_R0, p);
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p += 4;
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bfd_put_32 (htab->glink->owner, BCL_20_31, p);
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p += 4;
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bfd_put_32 (htab->glink->owner, MFLR_R11, p);
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p += 4;
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bfd_put_32 (htab->glink->owner, STD_R2_0R1 + 24, p);
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p += 4;
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bfd_put_32 (htab->glink->owner, LD_R2_0R11 | (-16 & 0xfffc), p);
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p += 4;
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bfd_put_32 (htab->glink->owner, MTLR_R0, p);
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p += 4;
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if (htab->has_plt_localentry0)
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insn = LD_R0_0R11 | (-20 & 0xfffc);
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else
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insn = LD_R0_0R11 | (-16 & 0xfffc);
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bfd_put_32 (htab->glink->owner, insn, p);
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p += 4;
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bfd_put_32 (htab->glink->owner, SUB_R12_R12_R11, p);
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p += 4;
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bfd_put_32 (htab->glink->owner, ADD_R11_R2_R11, p);
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bfd_put_32 (htab->glink->owner, ADD_R11_R0_R11, p);
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p += 4;
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bfd_put_32 (htab->glink->owner, ADDI_R0_R12 | (-48 & 0xffff), p);
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bfd_put_32 (htab->glink->owner, ADDI_R0_R12 | (-44 & 0xffff), p);
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p += 4;
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bfd_put_32 (htab->glink->owner, LD_R12_0R11, p);
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p += 4;
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12
ld/ChangeLog
12
ld/ChangeLog
@ -1,3 +1,15 @@
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2020-09-26 Alan Modra <amodra@gmail.com>
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* testsuite/ld-powerpc/elfv2so.d,
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* testsuite/ld-powerpc/notoc2.d,
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* testsuite/ld-powerpc/tlsdesc.wf,
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* testsuite/ld-powerpc/tlsdesc2.d,
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* testsuite/ld-powerpc/tlsdesc2.wf,
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* testsuite/ld-powerpc/tlsopt5.d,
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* testsuite/ld-powerpc/tlsopt5.wf,
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* testsuite/ld-powerpc/tlsopt6.d,
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* testsuite/ld-powerpc/tlsopt6.wf: Update __glink_PLTresolve.
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2020-09-24 Alan Modra <amodra@gmail.com>
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PR 26655
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@ -74,12 +74,11 @@ Disassembly of section \.text:
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.*: (7c 08 02 a6|a6 02 08 7c) mflr r0
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.*: (42 9f 00 05|05 00 9f 42) bcl .*
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.*: (7d 68 02 a6|a6 02 68 7d) mflr r11
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.*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\)
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.*: (e8 4b ff f0|f0 ff 4b e8) ld r2,-16\(r11\)
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.*: (7c 08 03 a6|a6 03 08 7c) mtlr r0
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.*: (e8 0b ff f0|f0 ff 0b e8) ld r0,-16\(r11\)
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.*: (7d 8b 60 50|50 60 8b 7d) subf r12,r11,r12
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.*: (7d 62 5a 14|14 5a 62 7d) add r11,r2,r11
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.*: (38 0c ff d0|d0 ff 0c 38) addi r0,r12,-48
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.*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11
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.*: (38 0c ff d4|d4 ff 0c 38) addi r0,r12,-44
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.*: (e9 8b 00 00|00 00 8b e9) ld r12,0\(r11\)
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.*: (78 00 f0 82|82 f0 00 78) rldicl r0,r0,62,2
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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@ -87,16 +86,16 @@ Disassembly of section \.text:
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.*: (4e 80 04 20|20 04 80 4e) bctr
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.* <f5@plt>:
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.*: (4b ff ff c8|c8 ff ff 4b) b .* <__glink_PLTresolve>
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.*: (4b ff ff cc|cc ff ff 4b) b .* <__glink_PLTresolve>
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.* <f3@plt>:
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.*: (4b ff ff c4|c4 ff ff 4b) b .* <__glink_PLTresolve>
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.*: (4b ff ff c8|c8 ff ff 4b) b .* <__glink_PLTresolve>
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.* <f2@plt>:
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.*: (4b ff ff c0|c0 ff ff 4b) b .* <__glink_PLTresolve>
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.*: (4b ff ff c4|c4 ff ff 4b) b .* <__glink_PLTresolve>
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.* <f4@plt>:
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.*: (4b ff ff bc|bc ff ff 4b) b .* <__glink_PLTresolve>
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.*: (4b ff ff c0|c0 ff ff 4b) b .* <__glink_PLTresolve>
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.* <f1@plt>:
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.*: (4b ff ff b8|b8 ff ff 4b) b .* <__glink_PLTresolve>
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.*: (4b ff ff bc|bc ff ff 4b) b .* <__glink_PLTresolve>
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@ -22,8 +22,8 @@ Disassembly of section \.text:
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.*: (39 80 ff ff|ff ff 80 39)
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.*: (06 10 00 00|00 00 10 06) pla r12,0
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.*: (39 80 00 00|00 00 80 39)
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.*: (06 10 00 00|00 00 10 06) pla r3,92
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.*: (38 60 00 5c|5c 00 60 38)
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.*: (06 10 00 00|00 00 10 06) pla r3,88
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.*: (38 60 00 58|58 00 60 38)
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.*: (4b ff ff 99|99 ff ff 4b) bl .* <.*\.plt_call\.puts>
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.*: (60 00 00 00|00 00 00 60) nop
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#pass
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@ -38,9 +38,9 @@ Contents of the \.eh_frame section:
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DW_CFA_nop
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0+4c 0+14 0+50 FDE cie=0+ pc=0+2f8\.\.0+32c
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DW_CFA_advance_loc: 4 to 0+2fc
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DW_CFA_advance_loc: 8 to 0+300
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DW_CFA_register: r65 in r12
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DW_CFA_advance_loc: 20 to 0+310
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DW_CFA_advance_loc: 16 to 0+310
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DW_CFA_restore_extended: r65
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0+64 0+10 0+68 FDE cie=0+ pc=0+2e0\.\.0+2ec
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@ -53,12 +53,11 @@ Disassembly of section \.text:
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.*: (7c 08 02 a6|a6 02 08 7c) mflr r0
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.*: (42 9f 00 05|05 00 9f 42) bcl .*
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.*: (7d 68 02 a6|a6 02 68 7d) mflr r11
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.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
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.*: (e8 4b ff f0|f0 ff 4b e8) ld r2,-16\(r11\)
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.*: (7c 08 03 a6|a6 03 08 7c) mtlr r0
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.*: (e8 0b ff f0|f0 ff 0b e8) ld r0,-16\(r11\)
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.*: (7d 8b 60 50|50 60 8b 7d) subf r12,r11,r12
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.*: (7d 62 5a 14|14 5a 62 7d) add r11,r2,r11
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.*: (38 0c ff d0|d0 ff 0c 38) addi r0,r12,-48
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.*: (7d 60 5a 14|14 5a 60 7d) add r11,r0,r11
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.*: (38 0c ff d4|d4 ff 0c 38) addi r0,r12,-44
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.*: (e9 8b 00 00|00 00 8b e9) ld r12,0\(r11\)
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.*: (78 00 f0 82|82 f0 00 78) rldicl r0,r0,62,2
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.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
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@ -66,4 +65,4 @@ Disassembly of section \.text:
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.*: (4e 80 04 20|20 04 80 4e) bctr
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.* <__tls_get_addr_opt@plt>:
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.*: (4b ff ff c8|c8 ff ff 4b) b .* <__glink_PLTresolve>
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.*: (4b ff ff cc|cc ff ff 4b) b .* <__glink_PLTresolve>
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@ -37,10 +37,10 @@ Contents of the \.eh_frame section:
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DW_CFA_nop
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DW_CFA_nop
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0+4c 0+14 0+50 FDE cie=0+ pc=0+318\.\.0+354
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DW_CFA_advance_loc: 4 to 0+31c
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0+4c 0+14 0+50 FDE cie=0+ pc=0+318\.\.0+350
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DW_CFA_advance_loc: 8 to 0+320
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DW_CFA_register: r65 in r0
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DW_CFA_advance_loc: 28 to 0+338
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DW_CFA_advance_loc: 8 to 0+328
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DW_CFA_restore_extended: r65
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0+64 0+10 0+68 FDE cie=0+ pc=0+300\.\.0+30c
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@ -49,12 +49,11 @@ Disassembly of section \.text:
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.*: (a6 02 08 7c|7c 08 02 a6) mflr r0
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.*: (05 00 9f 42|42 9f 00 05) bcl .*
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.*: (a6 02 68 7d|7d 68 02 a6) mflr r11
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.*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\)
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.*: (f0 ff 4b e8|e8 4b ff f0) ld r2,-16\(r11\)
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.*: (a6 03 08 7c|7c 08 03 a6) mtlr r0
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.*: (f0 ff 0b e8|e8 0b ff f0) ld r0,-16\(r11\)
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.*: (50 60 8b 7d|7d 8b 60 50) subf r12,r11,r12
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.*: (14 5a 62 7d|7d 62 5a 14) add r11,r2,r11
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.*: (d0 ff 0c 38|38 0c ff d0) addi r0,r12,-48
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.*: (14 5a 60 7d|7d 60 5a 14) add r11,r0,r11
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.*: (d4 ff 0c 38|38 0c ff d4) addi r0,r12,-44
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.*: (00 00 8b e9|e9 8b 00 00) ld r12,0\(r11\)
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.*: (82 f0 00 78|78 00 f0 82) rldicl r0,r0,62,2
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.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12
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@ -62,7 +61,7 @@ Disassembly of section \.text:
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.*: (20 04 80 4e|4e 80 04 20) bctr
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.* <__tls_get_addr_opt@plt>:
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.* (c8 ff ff 4b|4b ff ff c8) b .*
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.* (cc ff ff 4b|4b ff ff cc) b .*
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.* <aaaaa@plt>:
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.*: (c4 ff ff 4b|4b ff ff c4) b .*
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.*: (c8 ff ff 4b|4b ff ff c8) b .*
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@ -16,9 +16,9 @@ Contents of the \.eh_frame section:
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DW_CFA_restore_extended: r65
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0+2c 0+14 0+30 FDE cie=0+ pc=.*
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DW_CFA_advance_loc: 4 to .*
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DW_CFA_advance_loc: 8 to .*
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DW_CFA_register: r65 in r0
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DW_CFA_advance_loc: 28 to .*
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DW_CFA_advance_loc: 8 to .*
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DW_CFA_restore_extended: r65
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0+44 0+10 0+48 FDE cie=0+ pc=.*
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@ -67,12 +67,11 @@ Disassembly of section \.text:
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.*: (a6 02 08 7c|7c 08 02 a6) mflr r0
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.*: (05 00 9f 42|42 9f 00 05) bcl .*
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.*: (a6 02 68 7d|7d 68 02 a6) mflr r11
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.*: (18 00 41 f8|f8 41 00 18) std r2,24\(r1\)
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.*: (f0 ff 4b e8|e8 4b ff f0) ld r2,-16\(r11\)
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.*: (a6 03 08 7c|7c 08 03 a6) mtlr r0
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.*: (f0 ff 0b e8|e8 0b ff f0) ld r0,-16\(r11\)
|
||||
.*: (50 60 8b 7d|7d 8b 60 50) subf r12,r11,r12
|
||||
.*: (14 5a 62 7d|7d 62 5a 14) add r11,r2,r11
|
||||
.*: (d0 ff 0c 38|38 0c ff d0) addi r0,r12,-48
|
||||
.*: (14 5a 60 7d|7d 60 5a 14) add r11,r0,r11
|
||||
.*: (d4 ff 0c 38|38 0c ff d4) addi r0,r12,-44
|
||||
.*: (00 00 8b e9|e9 8b 00 00) ld r12,0\(r11\)
|
||||
.*: (82 f0 00 78|78 00 f0 82) rldicl r0,r0,62,2
|
||||
.*: (a6 03 89 7d|7d 89 03 a6) mtctr r12
|
||||
@ -80,7 +79,7 @@ Disassembly of section \.text:
|
||||
.*: (20 04 80 4e|4e 80 04 20) bctr
|
||||
|
||||
.* <__tls_get_addr_opt@plt>:
|
||||
.* (c8 ff ff 4b|4b ff ff c8) b .*
|
||||
.* (cc ff ff 4b|4b ff ff cc) b .*
|
||||
|
||||
.* <aaaaa@plt>:
|
||||
.*: (c4 ff ff 4b|4b ff ff c4) b .*
|
||||
.*: (c8 ff ff 4b|4b ff ff c8) b .*
|
||||
|
||||
@ -38,9 +38,9 @@ Contents of the \.eh_frame section:
|
||||
DW_CFA_nop
|
||||
|
||||
0+4c 0+14 0+50 FDE cie=0+ pc=.*
|
||||
DW_CFA_advance_loc: 4 to .*
|
||||
DW_CFA_advance_loc: 8 to .*
|
||||
DW_CFA_register: r65 in r0
|
||||
DW_CFA_advance_loc: 28 to .*
|
||||
DW_CFA_advance_loc: 8 to .*
|
||||
DW_CFA_restore_extended: r65
|
||||
|
||||
0+64 0+10 0+68 FDE cie=0+ pc=.*
|
||||
|
||||
Loading…
Reference in New Issue
Block a user