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* bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the

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logic to identify halfword shifts.
This commit is contained in:
Bernd Schmidt 2006-03-16 19:09:48 +00:00
parent 2db51539bb
commit 331f1cbe1c
2 changed files with 35 additions and 112 deletions
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5
opcodes/ChangeLog
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@ -1,3 +1,8 @@
2006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
* bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
logic to identify halfword shifts.
2006-03-16 Paul Brook <paul@codesourcery.com>
* arm-dis.c (arm_opcodes): Rename swi to svc.

142
opcodes/bfin-dis.c
View File

@ -4034,130 +4034,48 @@ decode_dsp32shiftimm_0 (TIword iw0, TIword iw1, disassemble_info *outf)
int HLs = ((iw1 >> DSP32ShiftImm_HLs_bits) & DSP32ShiftImm_HLs_mask);
if (HLs == 0 && sop == 0 && sopcde == 0)
if (sop == 0 && sopcde == 0)
{
OUTS (outf, dregs_lo (dst0));
OUTS (outf, "=");
OUTS (outf, dregs_lo (src1));
OUTS (outf, ">>>");
OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
OUTS (outf, " = ");
OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
OUTS (outf, " >>> ");
OUTS (outf, uimm4 (newimmag));
}
else if (HLs == 1 && sop == 0 && sopcde == 0)
else if (sop == 1 && sopcde == 0 && bit8 == 0)
{
OUTS (outf, dregs_lo (dst0));
OUTS (outf, "=");
OUTS (outf, dregs_hi (src1));
OUTS (outf, ">>>");
OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
OUTS (outf, " = ");
OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
OUTS (outf, " << ");
OUTS (outf, uimm4 (immag));
OUTS (outf, " (S)");
}
else if (sop == 1 && sopcde == 0 && bit8 == 1)
{
OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
OUTS (outf, " = ");
OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
OUTS (outf, " >>> ");
OUTS (outf, uimm4 (newimmag));
OUTS (outf, " (S)");
}
else if (HLs == 2 && sop == 0 && sopcde == 0)
else if (sop == 2 && sopcde == 0 && bit8 == 0)
{
OUTS (outf, dregs_hi (dst0));
OUTS (outf, "=");
OUTS (outf, dregs_lo (src1));
OUTS (outf, ">>>");
OUTS (outf, uimm4 (newimmag));
}
else if (HLs == 3 && sop == 0 && sopcde == 0)
{
OUTS (outf, dregs_hi (dst0));
OUTS (outf, "=");
OUTS (outf, dregs_hi (src1));
OUTS (outf, ">>>");
OUTS (outf, uimm4 (newimmag));
}
else if (HLs == 0 && sop == 1 && sopcde == 0)
{
OUTS (outf, dregs_lo (dst0));
OUTS (outf, "=");
OUTS (outf, dregs_lo (src1));
OUTS (outf, "<<");
OUTS (outf, uimm4 (immag));
OUTS (outf, "(S)");
}
else if (HLs == 1 && sop == 1 && sopcde == 0)
{
OUTS (outf, dregs_lo (dst0));
OUTS (outf, "=");
OUTS (outf, dregs_hi (src1));
OUTS (outf, "<<");
OUTS (outf, uimm4 (immag));
OUTS (outf, "(S)");
}
else if (HLs == 2 && sop == 1 && sopcde == 0)
{
OUTS (outf, dregs_hi (dst0));
OUTS (outf, "=");
OUTS (outf, dregs_lo (src1));
OUTS (outf, "<<");
OUTS (outf, uimm4 (immag));
OUTS (outf, "(S)");
}
else if (HLs == 3 && sop == 1 && sopcde == 0)
{
OUTS (outf, dregs_hi (dst0));
OUTS (outf, "=");
OUTS (outf, dregs_hi (src1));
OUTS (outf, "<<");
OUTS (outf, uimm4 (immag));
OUTS (outf, "(S)");
}
else if (HLs == 0 && sop == 2 && sopcde == 0 && bit8 == 0)
{
OUTS (outf, dregs_lo (dst0));
OUTS (outf, "=");
OUTS (outf, dregs_lo (src1));
OUTS (outf, "<<");
OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
OUTS (outf, " = ");
OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
OUTS (outf, " << ");
OUTS (outf, uimm4 (immag));
}
else if (HLs == 0 && sop == 2 && sopcde == 0 && bit8 == 1)
else if (sop == 2 && sopcde == 0 && bit8 == 1)
{
OUTS (outf, dregs_lo (dst0));
OUTS (outf, "=");
OUTS (outf, dregs_lo (src1));
OUTS (outf, ">>");
OUTS (outf, (HLs & 2) ? dregs_hi (dst0) : dregs_lo (dst0));
OUTS (outf, " = ");
OUTS (outf, (HLs & 1) ? dregs_hi (src1) : dregs_lo (src1));
OUTS (outf, " >> ");
OUTS (outf, uimm4 (newimmag));
}
else if (HLs == 1 && sop == 2 && sopcde == 0)
{
OUTS (outf, dregs_lo (dst0));
OUTS (outf, "=");
OUTS (outf, dregs_hi (src1));
OUTS (outf, ">>");
OUTS (outf, uimm4 (newimmag));
}
else if (HLs == 2 && sop == 2 && sopcde == 0 && bit8 == 1)
{
OUTS (outf, dregs_hi (dst0));
OUTS (outf, "=");
OUTS (outf, dregs_lo (src1));
OUTS (outf, ">>");
OUTS (outf, uimm4 (newimmag));
}
else if (HLs == 2 && sop == 2 && sopcde == 0 && bit8 == 0)
{
OUTS (outf, dregs_hi (dst0));
OUTS (outf, "=");
OUTS (outf, dregs_lo (src1));
OUTS (outf, "<<");
OUTS (outf, uimm4 (immag));
}
else if (HLs == 3 && sop == 2 && sopcde == 0 && bit8 == 1)
{
OUTS (outf, dregs_hi (dst0));
OUTS (outf, "=");
OUTS (outf, dregs_hi (src1));
OUTS (outf, ">>");
OUTS (outf, uimm4 (newimmag));
}
else if (HLs == 3 && sop == 2 && sopcde == 0 && bit8 == 0)
{
OUTS (outf, dregs_hi (dst0));
OUTS (outf, "=");
OUTS (outf, dregs_hi (src1));
OUTS (outf, "<<");
OUTS (outf, uimm4 (immag));
}
else if (sop == 2 && sopcde == 3 && HLs == 1)
{
OUTS (outf, "A1= ROT A1 BY ");