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When decoding a BLX(1) instruction do not add in the second bit of the base

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address - this has already been accounted for.
This commit is contained in:
Nick Clifton 2002-05-23 12:38:31 +00:00
parent c62e1cc30f
commit 2984e11475
2 changed files with 8 additions and 5 deletions
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6
sim/arm/ChangeLog
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@ -1,3 +1,9 @@
2002-05-23 Nick Clifton <nickc@cambridge.redhat.com>
* thumbemu.c (ARMul_ThumbDecode): When decoding a BLX(1)
instruction do not add in the second bit of the base address -
this has already been accounted for.
2002-05-21 Nick Clifton <nickc@cambridge.redhat.com> 2002-05-21 Nick Clifton <nickc@cambridge.redhat.com>
* armcopro.c (check_cp13_access): Allow access to register 1 when * armcopro.c (check_cp13_access): Allow access to register 1 when

7
sim/arm/thumbemu.c
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@ -520,12 +520,8 @@ tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr)
{ {
ARMword tmp = (pc + 2); ARMword tmp = (pc + 2);
/* Bit one of the destination address comes from bit one of the
address of the first (H == 10) half of the instruction, not
from the offset in the instruction. */
state->Reg[15] = ((state->Reg[14] state->Reg[15] = ((state->Reg[14]
+ ((tinstr & 0x07FE) << 1) + ((tinstr & 0x07FE) << 1))
+ ((pc - 2) & 2))
& 0xFFFFFFFC); & 0xFFFFFFFC);
CLEART; CLEART;
state->Reg[14] = (tmp | 1); state->Reg[14] = (tmp | 1);
@ -538,6 +534,7 @@ tdstate ARMul_ThumbDecode (state, pc, tinstr, ainstr)
break; break;
} }
/* else we fall through to process the second half of the BL */ /* else we fall through to process the second half of the BL */
pc += 2; /* point the pc at the 2nd half */
case 31: /* BL instruction 2 */ case 31: /* BL instruction 2 */
/* Format 19 */ /* Format 19 */
/* There is no single ARM instruction equivalent for this /* There is no single ARM instruction equivalent for this