gas/
* config/tc-mips.c (mips_check_isa_supports_ase, reg_lookup) (mips_parse_argument_token, validate_micromips_insn, md_begin) (check_regno, match_float_constant, check_completed_insn, append_insn) (match_insn, match_mips16_insn, match_insns, macro_start) (macro_build_ldst_constoffset, load_register, macro, mips_ip) (mips16_ip, mips_set_option_string, md_parse_option) (mips_after_parse_args, mips_after_parse_args, md_pcrel_from) (md_apply_fix, s_align, s_option, s_mipsset, s_tls_rel_directive) (s_gpword, s_gpdword, s_ehword, s_nan, tc_gen_reloc, md_convert_frag) (s_mips_end, s_mips_ent, s_mips_frame, s_mips_mask, mips_parse_cpu): Start error messages with a lower-case letter. Do not end error messages with a period. Wrap long messages to 80 character-lines. Use "cannot" instead of "can't" and "can not". gas/testsuite/ * gas/mips/ase-errors-1.l, gas/mips/ase-errors-2.l, gas/mips/ase-errors-3.l, gas/mips/ase-errors-4.l, gas/mips/at-2.l, gas/mips/baddata1.l, gas/mips/elf-rel30.l, gas/mips/illegal.l, gas/mips/jalr.l, gas/mips/ldstla-32-1.l, gas/mips/ldstla-32-mips3-1.l, gas/mips/lui-1.l, gas/mips/macro-warn-1.l, gas/mips/macro-warn-1-n32.l, gas/mips/macro-warn-2.l, gas/mips/macro-warn-3.l, gas/mips/macro-warn-4.l, gas/mips/micromips-branch-delay.l, gas/mips/micromips-branch-relax.l, gas/mips/micromips-branch-relax-pic.l, gas/mips/micromips-ill.l, gas/mips/micromips.l, gas/mips/micromips-size-0.l, gas/mips/micromips-size-1.l, gas/mips/micromips-warn-branch-delay.l, gas/mips/micromips-warn.l, gas/mips/mips16e-64.l, gas/mips/mips16e-save-err.l, gas/mips/mips1-fp.l, gas/mips/mips32r2-fp32.l, gas/mips/mips32r2-ill.l, gas/mips/mips32-sf32.l, gas/mips/mips4-branch-likely.l, gas/mips/mips4-fp.l, gas/mips/mips5-fp.l, gas/mips/mips64-mips3d.l, gas/mips/mips-double-float-flag.l, gas/mips/mips-gp64-fp32.l, gas/mips/mips-gp64-fp64.l, gas/mips/mips-hard-float-flag.l, gas/mips/mips-macro-ill-nofp.l, gas/mips/mips-macro-ill-sfp.l, gas/mips/nan-error-1.l, gas/mips/nan-error-2.l, gas/mips/noat-2.l, gas/mips/noat-3.l, gas/mips/noat-4.l, gas/mips/noat-5.l, gas/mips/noat-6.l, gas/mips/noat-7.l, gas/mips/octeon-ill.l, gas/mips/r5900-error-vu0.l, gas/mips/r5900-nollsc.l, gas/mips/relax-bc1any.l, gas/mips/relax-bposge.l, gas/mips/relax.l, gas/mips/relax-swap1.l, gas/mips/relax-swap2.l, gas/mips/set-arch.l, gas/mips/tls-ill.l, gas/mips/vr5400-ill.l: Adjust expected output.
This commit is contained in:
Richard Sandiford
parent
b0e6f033d5
commit
1661c76c19
@ -1,3 +1,19 @@
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2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (mips_check_isa_supports_ase, reg_lookup)
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(mips_parse_argument_token, validate_micromips_insn, md_begin)
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(check_regno, match_float_constant, check_completed_insn, append_insn)
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(match_insn, match_mips16_insn, match_insns, macro_start)
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(macro_build_ldst_constoffset, load_register, macro, mips_ip)
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(mips16_ip, mips_set_option_string, md_parse_option)
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(mips_after_parse_args, mips_after_parse_args, md_pcrel_from)
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(md_apply_fix, s_align, s_option, s_mipsset, s_tls_rel_directive)
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(s_gpword, s_gpdword, s_ehword, s_nan, tc_gen_reloc, md_convert_frag)
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(s_mips_end, s_mips_ent, s_mips_frame, s_mips_mask, mips_parse_cpu):
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Start error messages with a lower-case letter. Do not end error
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messages with a period. Wrap long messages to 80 character-lines.
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Use "cannot" instead of "can't" and "can not".
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2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
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2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
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* config/tc-mips.c (imm_expr): Expand comment.
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* config/tc-mips.c (imm_expr): Expand comment.
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@ -1885,10 +1885,10 @@ mips_check_isa_supports_ase (const struct mips_ase *ase)
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base = mips_opts.micromips ? "microMIPS" : "MIPS";
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base = mips_opts.micromips ? "microMIPS" : "MIPS";
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size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
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size = ISA_HAS_64BIT_REGS (mips_opts.isa) ? 64 : 32;
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if (min_rev < 0)
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if (min_rev < 0)
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as_warn (_("The %d-bit %s architecture does not support the"
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as_warn (_("the %d-bit %s architecture does not support the"
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" `%s' extension"), size, base, ase->name);
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" `%s' extension"), size, base, ase->name);
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else
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else
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as_warn (_("The `%s' extension requires %s%d revision %d or greater"),
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as_warn (_("the `%s' extension requires %s%d revision %d or greater"),
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ase->name, base, size, min_rev);
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ase->name, base, size, min_rev);
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}
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}
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if ((ase->flags & FP64_ASES)
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if ((ase->flags & FP64_ASES)
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@ -1896,7 +1896,7 @@ mips_check_isa_supports_ase (const struct mips_ase *ase)
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&& (warned_fp32 & ase->flags) != ase->flags)
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&& (warned_fp32 & ase->flags) != ase->flags)
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{
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{
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warned_fp32 |= ase->flags;
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warned_fp32 |= ase->flags;
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as_warn (_("The `%s' extension requires 64-bit FPRs"), ase->name);
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as_warn (_("the `%s' extension requires 64-bit FPRs"), ase->name);
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}
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}
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}
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}
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@ -2713,7 +2713,7 @@ reg_lookup (char **s, unsigned int types, unsigned int *regnop)
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else
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else
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{
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{
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if (types & RWARN)
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if (types & RWARN)
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as_warn (_("Unrecognized register name `%s'"), *s);
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as_warn (_("unrecognized register name `%s'"), *s);
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regno = ~0;
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regno = ~0;
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}
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}
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if (regnop)
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if (regnop)
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@ -2939,7 +2939,7 @@ mips_parse_argument_token (char *s, char float_format)
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SKIP_SPACE_TABS (s);
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SKIP_SPACE_TABS (s);
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if (!mips_parse_register (&s, ®no2, NULL))
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if (!mips_parse_register (&s, ®no2, NULL))
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{
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{
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set_insn_error (0, _("Invalid register range"));
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set_insn_error (0, _("invalid register range"));
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return 0;
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return 0;
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}
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}
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@ -2958,14 +2958,14 @@ mips_parse_argument_token (char *s, char float_format)
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my_getExpression (&element, s);
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my_getExpression (&element, s);
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if (element.X_op != O_constant)
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if (element.X_op != O_constant)
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{
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{
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set_insn_error (0, _("Vector element must be constant"));
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set_insn_error (0, _("vector element must be constant"));
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return 0;
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return 0;
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}
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}
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s = expr_end;
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s = expr_end;
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SKIP_SPACE_TABS (s);
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SKIP_SPACE_TABS (s);
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if (*s != ']')
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if (*s != ']')
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{
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{
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set_insn_error (0, _("Missing `]'"));
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set_insn_error (0, _("missing `]'"));
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return 0;
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return 0;
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}
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}
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++s;
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++s;
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@ -3281,7 +3281,7 @@ validate_micromips_insn (const struct mips_opcode *opc,
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length = micromips_insn_length (opc);
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length = micromips_insn_length (opc);
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if (length != 2 && length != 4)
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if (length != 2 && length != 4)
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{
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{
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as_bad (_("Internal error: bad microMIPS opcode (incorrect length: %u): "
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as_bad (_("internal error: bad microMIPS opcode (incorrect length: %u): "
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"%s %s"), length, opc->name, opc->args);
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"%s %s"), length, opc->name, opc->args);
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return 0;
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return 0;
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}
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}
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@ -3289,7 +3289,7 @@ validate_micromips_insn (const struct mips_opcode *opc,
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if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
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if ((length == 2 && (major & 7) != 1 && (major & 6) != 2)
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|| (length == 4 && (major & 7) != 0 && (major & 4) != 4))
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|| (length == 4 && (major & 7) != 0 && (major & 4) != 4))
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{
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{
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as_bad (_("Internal error: bad microMIPS opcode "
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as_bad (_("internal error: bad microMIPS opcode "
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"(opcode/length mismatch): %s %s"), opc->name, opc->args);
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"(opcode/length mismatch): %s %s"), opc->name, opc->args);
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return 0;
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return 0;
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}
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}
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@ -3320,7 +3320,7 @@ md_begin (void)
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}
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}
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if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
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if (! bfd_set_arch_mach (stdoutput, bfd_arch_mips, file_mips_arch))
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as_warn (_("Could not set architecture and machine"));
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as_warn (_("could not set architecture and machine"));
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op_hash = hash_new ();
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op_hash = hash_new ();
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@ -3335,7 +3335,7 @@ md_begin (void)
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fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
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fprintf (stderr, _("internal error: can't hash `%s': %s\n"),
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mips_opcodes[i].name, retval);
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mips_opcodes[i].name, retval);
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/* Probably a memory allocation problem? Give up now. */
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/* Probably a memory allocation problem? Give up now. */
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as_fatal (_("Broken assembler. No assembly attempted."));
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as_fatal (_("broken assembler, no assembly attempted"));
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}
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}
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do
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do
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{
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{
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@ -3426,7 +3426,7 @@ md_begin (void)
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}
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}
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if (broken)
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if (broken)
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as_fatal (_("Broken assembler. No assembly attempted."));
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as_fatal (_("broken assembler, no assembly attempted"));
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/* We add all the general register names to the symbol table. This
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/* We add all the general register names to the symbol table. This
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helps us detect invalid uses of them. */
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helps us detect invalid uses of them. */
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@ -4425,7 +4425,7 @@ check_regno (struct mips_arg_info *arg,
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&& (regno & 1) != 0
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&& (regno & 1) != 0
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&& HAVE_32BIT_FPRS
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&& HAVE_32BIT_FPRS
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&& !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
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&& !mips_oddfpreg_ok (arg->insn->insn_mo, arg->opnum))
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as_warn (_("Float register should be even, was %d"), regno);
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as_warn (_("float register should be even, was %d"), regno);
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if (type == OP_REG_CCC)
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if (type == OP_REG_CCC)
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{
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{
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@ -4437,12 +4437,12 @@ check_regno (struct mips_arg_info *arg,
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if ((regno & 1) != 0
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if ((regno & 1) != 0
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&& ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
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&& ((length >= 3 && strcmp (name + length - 3, ".ps") == 0)
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|| (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
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|| (length >= 5 && strncmp (name + length - 5, "any2", 4) == 0)))
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as_warn (_("Condition code register should be even for %s, was %d"),
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as_warn (_("condition code register should be even for %s, was %d"),
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name, regno);
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name, regno);
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if ((regno & 3) != 0
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if ((regno & 3) != 0
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&& (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
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&& (length >= 5 && strncmp (name + length - 5, "any4", 4) == 0))
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as_warn (_("Condition code register should be 0 or 4 for %s, was %d"),
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as_warn (_("condition code register should be 0 or 4 for %s, was %d"),
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name, regno);
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name, regno);
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}
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}
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}
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}
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@ -5310,7 +5310,7 @@ match_float_constant (struct mips_arg_info *arg, expressionS *imm,
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else
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else
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record_alignment (new_seg, length == 4 ? 2 : 3);
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record_alignment (new_seg, length == 4 ? 2 : 3);
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if (seg == now_seg)
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if (seg == now_seg)
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as_bad (_("Can't use floating point insn in this section"));
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as_bad (_("cannot use `%s' in this section"), arg->insn->insn_mo->name);
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/* Set the argument to the current address in the section. */
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/* Set the argument to the current address in the section. */
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imm->X_op = O_absent;
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imm->X_op = O_absent;
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@ -5439,9 +5439,9 @@ check_completed_insn (struct mips_arg_info *arg)
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if (arg->seen_at)
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if (arg->seen_at)
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{
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{
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if (AT == ATREG)
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if (AT == ATREG)
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as_warn (_("Used $at without \".set noat\""));
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as_warn (_("used $at without \".set noat\""));
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else
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else
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as_warn (_("Used $%u with \".set at=$%u\""), AT, AT);
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as_warn (_("used $%u with \".set at=$%u\""), AT, AT);
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}
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}
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}
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}
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@ -6406,7 +6406,7 @@ append_insn (struct mips_cl_insn *ip, expressionS *address_expr,
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&& micromips_insn_length (ip->insn_mo) != 2)
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&& micromips_insn_length (ip->insn_mo) != 2)
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|| ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
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|| ((prev_pinfo2 & INSN2_BRANCH_DELAY_32BIT) != 0
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&& micromips_insn_length (ip->insn_mo) != 4)))
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&& micromips_insn_length (ip->insn_mo) != 4)))
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as_warn (_("Wrong size instruction in a %u-bit branch delay slot"),
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as_warn (_("wrong size instruction in a %u-bit branch delay slot"),
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(prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
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(prev_pinfo2 & INSN2_BRANCH_DELAY_16BIT) != 0 ? 16 : 32);
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if (address_expr == NULL)
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if (address_expr == NULL)
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@ -7086,10 +7086,10 @@ match_insn (struct mips_cl_insn *insn, const struct mips_opcode *opcode,
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{
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{
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if (arg.opnum == 2)
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if (arg.opnum == 2)
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set_insn_error
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set_insn_error
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(0, _("Source and destination must be different"));
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(0, _("source and destination must be different"));
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else if (arg.last_regno == 31)
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else if (arg.last_regno == 31)
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set_insn_error
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set_insn_error
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(0, _("A destination register must be supplied"));
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(0, _("a destination register must be supplied"));
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}
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}
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check_completed_insn (&arg);
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check_completed_insn (&arg);
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return TRUE;
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return TRUE;
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@ -7420,7 +7420,7 @@ static void
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match_invalid_for_isa (void)
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match_invalid_for_isa (void)
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{
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{
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set_insn_error_ss
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set_insn_error_ss
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(0, _("Opcode not supported on this processor: %s (%s)"),
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(0, _("opcode not supported on this processor: %s (%s)"),
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mips_cpu_info_from_arch (mips_opts.arch)->name,
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mips_cpu_info_from_arch (mips_opts.arch)->name,
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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mips_cpu_info_from_isa (mips_opts.isa)->name);
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}
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}
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@ -7499,10 +7499,10 @@ match_insns (struct mips_cl_insn *insn, const struct mips_opcode *first,
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if (!seen_valid_for_size)
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if (!seen_valid_for_size)
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{
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{
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if (mips_opts.insn32)
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if (mips_opts.insn32)
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set_insn_error (0, _("Opcode not supported in the `insn32' mode"));
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set_insn_error (0, _("opcode not supported in the `insn32' mode"));
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else
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else
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set_insn_error_i
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set_insn_error_i
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(0, _("Unrecognized %d-bit version of microMIPS opcode"),
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(0, _("unrecognized %d-bit version of microMIPS opcode"),
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8 * forced_insn_length);
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8 * forced_insn_length);
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return TRUE;
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return TRUE;
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}
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}
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@ -7586,16 +7586,16 @@ static const char *
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macro_warning (relax_substateT subtype)
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macro_warning (relax_substateT subtype)
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{
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{
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if (subtype & RELAX_DELAY_SLOT)
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if (subtype & RELAX_DELAY_SLOT)
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return _("Macro instruction expanded into multiple instructions"
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return _("macro instruction expanded into multiple instructions"
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" in a branch delay slot");
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" in a branch delay slot");
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else if (subtype & RELAX_NOMACRO)
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else if (subtype & RELAX_NOMACRO)
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return _("Macro instruction expanded into multiple instructions");
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return _("macro instruction expanded into multiple instructions");
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else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
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else if (subtype & (RELAX_DELAY_SLOT_SIZE_FIRST
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| RELAX_DELAY_SLOT_SIZE_SECOND))
|
| RELAX_DELAY_SLOT_SIZE_SECOND))
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return ((subtype & RELAX_DELAY_SLOT_16BIT)
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return ((subtype & RELAX_DELAY_SLOT_16BIT)
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? _("Macro instruction expanded into a wrong size instruction"
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? _("macro instruction expanded into a wrong size instruction"
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" in a 16-bit branch delay slot")
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" in a 16-bit branch delay slot")
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: _("Macro instruction expanded into a wrong size instruction"
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: _("macro instruction expanded into a wrong size instruction"
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" in a 32-bit branch delay slot"));
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" in a 32-bit branch delay slot"));
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else
|
else
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return 0;
|
return 0;
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@ -8056,7 +8056,7 @@ macro_build_ldst_constoffset (expressionS *ep, const char *op,
|
|||||||
macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
|
macro_build (ep, op, "t,o(b)", treg, BFD_RELOC_LO16, AT);
|
||||||
|
|
||||||
if (!mips_opts.at)
|
if (!mips_opts.at)
|
||||||
as_bad (_("Macro used $at after \".set noat\""));
|
as_bad (_("macro used $at after \".set noat\""));
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -8204,7 +8204,7 @@ load_register (int reg, expressionS *ep, int dbl)
|
|||||||
char value[32];
|
char value[32];
|
||||||
|
|
||||||
sprintf_vma (value, ep->X_add_number);
|
sprintf_vma (value, ep->X_add_number);
|
||||||
as_bad (_("Number (0x%s) larger than 32 bits"), value);
|
as_bad (_("number (0x%s) larger than 32 bits"), value);
|
||||||
macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
|
macro_build (ep, "addiu", "t,r,j", reg, 0, BFD_RELOC_LO16);
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
@ -8224,7 +8224,7 @@ load_register (int reg, expressionS *ep, int dbl)
|
|||||||
if (ep->X_add_number == 3)
|
if (ep->X_add_number == 3)
|
||||||
generic_bignum[3] = 0;
|
generic_bignum[3] = 0;
|
||||||
else if (ep->X_add_number > 4)
|
else if (ep->X_add_number > 4)
|
||||||
as_bad (_("Number larger than 64 bits"));
|
as_bad (_("number larger than 64 bits"));
|
||||||
lo32.X_op = O_constant;
|
lo32.X_op = O_constant;
|
||||||
lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
|
lo32.X_add_number = generic_bignum[0] + (generic_bignum[1] << 16);
|
||||||
hi32.X_op = O_constant;
|
hi32.X_op = O_constant;
|
||||||
@ -8640,7 +8640,7 @@ load_address (int reg, expressionS *ep, int *used_at)
|
|||||||
abort ();
|
abort ();
|
||||||
|
|
||||||
if (!mips_opts.at && *used_at == 1)
|
if (!mips_opts.at && *used_at == 1)
|
||||||
as_bad (_("Macro used $at after \".set noat\""));
|
as_bad (_("macro used $at after \".set noat\""));
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Move the contents of register SOURCE into register DEST. */
|
/* Move the contents of register SOURCE into register DEST. */
|
||||||
@ -9251,7 +9251,7 @@ macro (struct mips_cl_insn *ip, char *str)
|
|||||||
{
|
{
|
||||||
do_true:
|
do_true:
|
||||||
/* result is always true */
|
/* result is always true */
|
||||||
as_warn (_("Branch %s is always true"), ip->insn_mo->name);
|
as_warn (_("branch %s is always true"), ip->insn_mo->name);
|
||||||
macro_build (&offset_expr, "b", "p");
|
macro_build (&offset_expr, "b", "p");
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
@ -9467,7 +9467,7 @@ macro (struct mips_cl_insn *ip, char *str)
|
|||||||
do_div3:
|
do_div3:
|
||||||
if (op[2] == 0)
|
if (op[2] == 0)
|
||||||
{
|
{
|
||||||
as_warn (_("Divide by zero."));
|
as_warn (_("divide by zero"));
|
||||||
if (mips_trap)
|
if (mips_trap)
|
||||||
macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
|
macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
|
||||||
else
|
else
|
||||||
@ -9577,7 +9577,7 @@ macro (struct mips_cl_insn *ip, char *str)
|
|||||||
do_divi:
|
do_divi:
|
||||||
if (imm_expr.X_add_number == 0)
|
if (imm_expr.X_add_number == 0)
|
||||||
{
|
{
|
||||||
as_warn (_("Divide by zero."));
|
as_warn (_("divide by zero"));
|
||||||
if (mips_trap)
|
if (mips_trap)
|
||||||
macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
|
macro_build (NULL, "teq", TRAP_FMT, ZERO, ZERO, 7);
|
||||||
else
|
else
|
||||||
@ -9688,7 +9688,7 @@ macro (struct mips_cl_insn *ip, char *str)
|
|||||||
if (offset_expr.X_op != O_symbol
|
if (offset_expr.X_op != O_symbol
|
||||||
&& offset_expr.X_op != O_constant)
|
&& offset_expr.X_op != O_constant)
|
||||||
{
|
{
|
||||||
as_bad (_("Expression too complex"));
|
as_bad (_("expression too complex"));
|
||||||
offset_expr.X_op = O_constant;
|
offset_expr.X_op = O_constant;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -9776,7 +9776,7 @@ macro (struct mips_cl_insn *ip, char *str)
|
|||||||
relax_switch ();
|
relax_switch ();
|
||||||
}
|
}
|
||||||
if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
|
if (!IS_SEXT_32BIT_NUM (offset_expr.X_add_number))
|
||||||
as_bad (_("Offset too large"));
|
as_bad (_("offset too large"));
|
||||||
macro_build_lui (&offset_expr, tempreg);
|
macro_build_lui (&offset_expr, tempreg);
|
||||||
macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
|
macro_build (&offset_expr, ADDRESS_ADDI_INSN, "t,r,j",
|
||||||
tempreg, tempreg, BFD_RELOC_LO16);
|
tempreg, tempreg, BFD_RELOC_LO16);
|
||||||
@ -10298,7 +10298,7 @@ macro (struct mips_cl_insn *ip, char *str)
|
|||||||
gas_assert (mips_opts.micromips);
|
gas_assert (mips_opts.micromips);
|
||||||
if (mips_opts.insn32)
|
if (mips_opts.insn32)
|
||||||
{
|
{
|
||||||
as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
|
as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
jals = 1;
|
jals = 1;
|
||||||
@ -10342,18 +10342,18 @@ macro (struct mips_cl_insn *ip, char *str)
|
|||||||
if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
|
if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
|
||||||
{
|
{
|
||||||
if (mips_cprestore_offset < 0)
|
if (mips_cprestore_offset < 0)
|
||||||
as_warn (_("No .cprestore pseudo-op used in PIC code"));
|
as_warn (_("no .cprestore pseudo-op used in PIC code"));
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
if (!mips_frame_reg_valid)
|
if (!mips_frame_reg_valid)
|
||||||
{
|
{
|
||||||
as_warn (_("No .frame pseudo-op used in PIC code"));
|
as_warn (_("no .frame pseudo-op used in PIC code"));
|
||||||
/* Quiet this warning. */
|
/* Quiet this warning. */
|
||||||
mips_frame_reg_valid = 1;
|
mips_frame_reg_valid = 1;
|
||||||
}
|
}
|
||||||
if (!mips_cprestore_valid)
|
if (!mips_cprestore_valid)
|
||||||
{
|
{
|
||||||
as_warn (_("No .cprestore pseudo-op used in PIC code"));
|
as_warn (_("no .cprestore pseudo-op used in PIC code"));
|
||||||
/* Quiet this warning. */
|
/* Quiet this warning. */
|
||||||
mips_cprestore_valid = 1;
|
mips_cprestore_valid = 1;
|
||||||
}
|
}
|
||||||
@ -10374,7 +10374,7 @@ macro (struct mips_cl_insn *ip, char *str)
|
|||||||
gas_assert (mips_opts.micromips);
|
gas_assert (mips_opts.micromips);
|
||||||
if (mips_opts.insn32)
|
if (mips_opts.insn32)
|
||||||
{
|
{
|
||||||
as_bad (_("Opcode not supported in the `insn32' mode `%s'"), str);
|
as_bad (_("opcode not supported in the `insn32' mode `%s'"), str);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
jals = 1;
|
jals = 1;
|
||||||
@ -10486,18 +10486,18 @@ macro (struct mips_cl_insn *ip, char *str)
|
|||||||
macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
|
macro_build_jalr (&offset_expr, mips_cprestore_offset >= 0);
|
||||||
|
|
||||||
if (mips_cprestore_offset < 0)
|
if (mips_cprestore_offset < 0)
|
||||||
as_warn (_("No .cprestore pseudo-op used in PIC code"));
|
as_warn (_("no .cprestore pseudo-op used in PIC code"));
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
if (!mips_frame_reg_valid)
|
if (!mips_frame_reg_valid)
|
||||||
{
|
{
|
||||||
as_warn (_("No .frame pseudo-op used in PIC code"));
|
as_warn (_("no .frame pseudo-op used in PIC code"));
|
||||||
/* Quiet this warning. */
|
/* Quiet this warning. */
|
||||||
mips_frame_reg_valid = 1;
|
mips_frame_reg_valid = 1;
|
||||||
}
|
}
|
||||||
if (!mips_cprestore_valid)
|
if (!mips_cprestore_valid)
|
||||||
{
|
{
|
||||||
as_warn (_("No .cprestore pseudo-op used in PIC code"));
|
as_warn (_("no .cprestore pseudo-op used in PIC code"));
|
||||||
/* Quiet this warning. */
|
/* Quiet this warning. */
|
||||||
mips_cprestore_valid = 1;
|
mips_cprestore_valid = 1;
|
||||||
}
|
}
|
||||||
@ -10512,7 +10512,7 @@ macro (struct mips_cl_insn *ip, char *str)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
else if (mips_pic == VXWORKS_PIC)
|
else if (mips_pic == VXWORKS_PIC)
|
||||||
as_bad (_("Non-PIC jump used in PIC library"));
|
as_bad (_("non-PIC jump used in PIC library"));
|
||||||
else
|
else
|
||||||
abort ();
|
abort ();
|
||||||
|
|
||||||
@ -10920,7 +10920,7 @@ macro (struct mips_cl_insn *ip, char *str)
|
|||||||
if (offset_expr.X_op != O_constant
|
if (offset_expr.X_op != O_constant
|
||||||
&& offset_expr.X_op != O_symbol)
|
&& offset_expr.X_op != O_symbol)
|
||||||
{
|
{
|
||||||
as_bad (_("Expression too complex"));
|
as_bad (_("expression too complex"));
|
||||||
offset_expr.X_op = O_constant;
|
offset_expr.X_op = O_constant;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -10930,7 +10930,7 @@ macro (struct mips_cl_insn *ip, char *str)
|
|||||||
char value [32];
|
char value [32];
|
||||||
|
|
||||||
sprintf_vma (value, offset_expr.X_add_number);
|
sprintf_vma (value, offset_expr.X_add_number);
|
||||||
as_bad (_("Number (0x%s) larger than 32 bits"), value);
|
as_bad (_("number (0x%s) larger than 32 bits"), value);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* A constant expression in PIC code can be handled just as it
|
/* A constant expression in PIC code can be handled just as it
|
||||||
@ -11575,7 +11575,7 @@ macro (struct mips_cl_insn *ip, char *str)
|
|||||||
if (offset_expr.X_op != O_symbol
|
if (offset_expr.X_op != O_symbol
|
||||||
&& offset_expr.X_op != O_constant)
|
&& offset_expr.X_op != O_constant)
|
||||||
{
|
{
|
||||||
as_bad (_("Expression too complex"));
|
as_bad (_("expression too complex"));
|
||||||
offset_expr.X_op = O_constant;
|
offset_expr.X_op = O_constant;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -11585,7 +11585,7 @@ macro (struct mips_cl_insn *ip, char *str)
|
|||||||
char value [32];
|
char value [32];
|
||||||
|
|
||||||
sprintf_vma (value, offset_expr.X_add_number);
|
sprintf_vma (value, offset_expr.X_add_number);
|
||||||
as_bad (_("Number (0x%s) larger than 32 bits"), value);
|
as_bad (_("number (0x%s) larger than 32 bits"), value);
|
||||||
}
|
}
|
||||||
|
|
||||||
if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
|
if (mips_pic == NO_PIC || offset_expr.X_op == O_constant)
|
||||||
@ -12139,7 +12139,7 @@ macro (struct mips_cl_insn *ip, char *str)
|
|||||||
}
|
}
|
||||||
if (op[1] == 0)
|
if (op[1] == 0)
|
||||||
{
|
{
|
||||||
as_warn (_("Instruction %s: result is always false"),
|
as_warn (_("instruction %s: result is always false"),
|
||||||
ip->insn_mo->name);
|
ip->insn_mo->name);
|
||||||
move_register (op[0], 0);
|
move_register (op[0], 0);
|
||||||
break;
|
break;
|
||||||
@ -12292,7 +12292,7 @@ macro (struct mips_cl_insn *ip, char *str)
|
|||||||
}
|
}
|
||||||
if (op[1] == 0)
|
if (op[1] == 0)
|
||||||
{
|
{
|
||||||
as_warn (_("Instruction %s: result is always true"),
|
as_warn (_("instruction %s: result is always true"),
|
||||||
ip->insn_mo->name);
|
ip->insn_mo->name);
|
||||||
macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
|
macro_build (&expr1, HAVE_32BIT_GPRS ? "addiu" : "daddiu", "t,r,j",
|
||||||
op[0], 0, BFD_RELOC_LO16);
|
op[0], 0, BFD_RELOC_LO16);
|
||||||
@ -12577,11 +12577,11 @@ macro (struct mips_cl_insn *ip, char *str)
|
|||||||
default:
|
default:
|
||||||
/* FIXME: Check if this is one of the itbl macros, since they
|
/* FIXME: Check if this is one of the itbl macros, since they
|
||||||
are added dynamically. */
|
are added dynamically. */
|
||||||
as_bad (_("Macro %s not implemented yet"), ip->insn_mo->name);
|
as_bad (_("macro %s not implemented yet"), ip->insn_mo->name);
|
||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
if (!mips_opts.at && used_at)
|
if (!mips_opts.at && used_at)
|
||||||
as_bad (_("Macro used $at after \".set noat\""));
|
as_bad (_("macro used $at after \".set noat\""));
|
||||||
}
|
}
|
||||||
|
|
||||||
/* Implement macros in mips16 mode. */
|
/* Implement macros in mips16 mode. */
|
||||||
@ -12918,7 +12918,7 @@ mips_ip (char *str, struct mips_cl_insn *insn)
|
|||||||
first = mips_lookup_insn (hash, str, end, &opcode_extra);
|
first = mips_lookup_insn (hash, str, end, &opcode_extra);
|
||||||
if (first == NULL)
|
if (first == NULL)
|
||||||
{
|
{
|
||||||
set_insn_error (0, _("Unrecognized opcode"));
|
set_insn_error (0, _("unrecognized opcode"));
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -12934,7 +12934,7 @@ mips_ip (char *str, struct mips_cl_insn *insn)
|
|||||||
|
|
||||||
if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE)
|
if (!match_insns (insn, first, past, tokens, opcode_extra, FALSE)
|
||||||
&& !match_insns (insn, first, past, tokens, opcode_extra, TRUE))
|
&& !match_insns (insn, first, past, tokens, opcode_extra, TRUE))
|
||||||
set_insn_error (0, _("Illegal operands"));
|
set_insn_error (0, _("invalid operands"));
|
||||||
|
|
||||||
obstack_free (&mips_operand_tokens, tokens);
|
obstack_free (&mips_operand_tokens, tokens);
|
||||||
}
|
}
|
||||||
@ -12980,7 +12980,7 @@ mips16_ip (char *str, struct mips_cl_insn *insn)
|
|||||||
}
|
}
|
||||||
/* Fall through. */
|
/* Fall through. */
|
||||||
default:
|
default:
|
||||||
set_insn_error (0, _("Unrecognized opcode"));
|
set_insn_error (0, _("unrecognized opcode"));
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -12993,7 +12993,7 @@ mips16_ip (char *str, struct mips_cl_insn *insn)
|
|||||||
|
|
||||||
if (!first)
|
if (!first)
|
||||||
{
|
{
|
||||||
set_insn_error (0, _("Unrecognized opcode"));
|
set_insn_error (0, _("unrecognized opcode"));
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -13002,7 +13002,7 @@ mips16_ip (char *str, struct mips_cl_insn *insn)
|
|||||||
return;
|
return;
|
||||||
|
|
||||||
if (!match_mips16_insns (insn, first, tokens))
|
if (!match_mips16_insns (insn, first, tokens))
|
||||||
set_insn_error (0, _("Illegal operands"));
|
set_insn_error (0, _("invalid operands"));
|
||||||
|
|
||||||
obstack_free (&mips_operand_tokens, tokens);
|
obstack_free (&mips_operand_tokens, tokens);
|
||||||
}
|
}
|
||||||
@ -13329,7 +13329,7 @@ static void
|
|||||||
mips_set_option_string (const char **string_ptr, const char *new_value)
|
mips_set_option_string (const char **string_ptr, const char *new_value)
|
||||||
{
|
{
|
||||||
if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
|
if (*string_ptr != 0 && strcasecmp (*string_ptr, new_value) != 0)
|
||||||
as_warn (_("A different %s was already specified, is now %s"),
|
as_warn (_("a different %s was already specified, is now %s"),
|
||||||
string_ptr == &mips_arch_string ? "-march" : "-mtune",
|
string_ptr == &mips_arch_string ? "-march" : "-mtune",
|
||||||
new_value);
|
new_value);
|
||||||
|
|
||||||
@ -13622,7 +13622,7 @@ md_parse_option (int c, char *arg)
|
|||||||
case OPTION_64:
|
case OPTION_64:
|
||||||
mips_abi = N64_ABI;
|
mips_abi = N64_ABI;
|
||||||
if (!support_64bit_objects())
|
if (!support_64bit_objects())
|
||||||
as_fatal (_("No compiled in support for 64 bit object file format"));
|
as_fatal (_("no compiled in support for 64 bit object file format"));
|
||||||
break;
|
break;
|
||||||
|
|
||||||
case OPTION_GP32:
|
case OPTION_GP32:
|
||||||
@ -13668,7 +13668,7 @@ md_parse_option (int c, char *arg)
|
|||||||
{
|
{
|
||||||
mips_abi = N64_ABI;
|
mips_abi = N64_ABI;
|
||||||
if (! support_64bit_objects())
|
if (! support_64bit_objects())
|
||||||
as_fatal (_("No compiled in support for 64 bit object file "
|
as_fatal (_("no compiled in support for 64 bit object file "
|
||||||
"format"));
|
"format"));
|
||||||
}
|
}
|
||||||
else if (strcmp (arg, "eabi") == 0)
|
else if (strcmp (arg, "eabi") == 0)
|
||||||
@ -13715,7 +13715,7 @@ md_parse_option (int c, char *arg)
|
|||||||
mips_flag_nan2008 = FALSE;
|
mips_flag_nan2008 = FALSE;
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
as_fatal (_("Invalid NaN setting -mnan=%s"), arg);
|
as_fatal (_("invalid NaN setting -mnan=%s"), arg);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
@ -13764,7 +13764,7 @@ mips_after_parse_args (void)
|
|||||||
if (strncmp (TARGET_OS, "pe", 2) == 0)
|
if (strncmp (TARGET_OS, "pe", 2) == 0)
|
||||||
{
|
{
|
||||||
if (g_switch_seen && g_switch_value != 0)
|
if (g_switch_seen && g_switch_value != 0)
|
||||||
as_bad (_("-G not supported in this configuration."));
|
as_bad (_("-G not supported in this configuration"));
|
||||||
g_switch_value = 0;
|
g_switch_value = 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -13790,7 +13790,8 @@ mips_after_parse_args (void)
|
|||||||
There's no harm in specifying both as long as the ISA levels
|
There's no harm in specifying both as long as the ISA levels
|
||||||
are the same. */
|
are the same. */
|
||||||
if (file_mips_isa != arch_info->isa)
|
if (file_mips_isa != arch_info->isa)
|
||||||
as_bad (_("-%s conflicts with the other architecture options, which imply -%s"),
|
as_bad (_("-%s conflicts with the other architecture options,"
|
||||||
|
" which imply -%s"),
|
||||||
mips_cpu_info_from_isa (file_mips_isa)->name,
|
mips_cpu_info_from_isa (file_mips_isa)->name,
|
||||||
mips_cpu_info_from_isa (arch_info->isa)->name);
|
mips_cpu_info_from_isa (arch_info->isa)->name);
|
||||||
}
|
}
|
||||||
@ -13951,7 +13952,8 @@ md_pcrel_from (fixS *fixP)
|
|||||||
/* We have no relocation type for PC relative MIPS16 instructions. */
|
/* We have no relocation type for PC relative MIPS16 instructions. */
|
||||||
if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
|
if (fixP->fx_addsy && S_GET_SEGMENT (fixP->fx_addsy) != now_seg)
|
||||||
as_bad_where (fixP->fx_file, fixP->fx_line,
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
||||||
_("PC relative MIPS16 instruction references a different section"));
|
_("PC relative MIPS16 instruction references"
|
||||||
|
" a different section"));
|
||||||
return addr;
|
return addr;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -14292,7 +14294,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
|
|||||||
}
|
}
|
||||||
else
|
else
|
||||||
as_bad_where (fixP->fx_file, fixP->fx_line,
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
||||||
_("Unsupported constant in relocation"));
|
_("unsupported constant in relocation"));
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
@ -14331,7 +14333,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
|
|||||||
case BFD_RELOC_16_PCREL_S2:
|
case BFD_RELOC_16_PCREL_S2:
|
||||||
if ((*valP & 0x3) != 0)
|
if ((*valP & 0x3) != 0)
|
||||||
as_bad_where (fixP->fx_file, fixP->fx_line,
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
||||||
_("Branch to misaligned address (%lx)"), (long) *valP);
|
_("branch to misaligned address (%lx)"), (long) *valP);
|
||||||
|
|
||||||
/* We need to save the bits in the instruction since fixup_segment()
|
/* We need to save the bits in the instruction since fixup_segment()
|
||||||
might be deleting the relocation entry (i.e., a branch within
|
might be deleting the relocation entry (i.e., a branch within
|
||||||
@ -14375,7 +14377,7 @@ md_apply_fix (fixS *fixP, valueT *valP, segT seg ATTRIBUTE_UNUSED)
|
|||||||
and there's nothing we can do to fix this instruction
|
and there's nothing we can do to fix this instruction
|
||||||
without turning it into a longer sequence. */
|
without turning it into a longer sequence. */
|
||||||
as_bad_where (fixP->fx_file, fixP->fx_line,
|
as_bad_where (fixP->fx_file, fixP->fx_line,
|
||||||
_("Branch out of range"));
|
_("branch out of range"));
|
||||||
}
|
}
|
||||||
break;
|
break;
|
||||||
|
|
||||||
@ -14473,10 +14475,10 @@ s_align (int x ATTRIBUTE_UNUSED)
|
|||||||
|
|
||||||
temp = get_absolute_expression ();
|
temp = get_absolute_expression ();
|
||||||
if (temp > max_alignment)
|
if (temp > max_alignment)
|
||||||
as_bad (_("Alignment too large: %d. assumed."), temp = max_alignment);
|
as_bad (_("alignment too large, %d assumed"), temp = max_alignment);
|
||||||
else if (temp < 0)
|
else if (temp < 0)
|
||||||
{
|
{
|
||||||
as_warn (_("Alignment negative: 0 assumed."));
|
as_warn (_("alignment negative, 0 assumed"));
|
||||||
temp = 0;
|
temp = 0;
|
||||||
}
|
}
|
||||||
if (*input_line_pointer == ',')
|
if (*input_line_pointer == ',')
|
||||||
@ -14772,7 +14774,7 @@ s_option (int x ATTRIBUTE_UNUSED)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
else
|
else
|
||||||
as_warn (_("Unrecognized option \"%s\""), opt);
|
as_warn (_("unrecognized option \"%s\""), opt);
|
||||||
|
|
||||||
*input_line_pointer = c;
|
*input_line_pointer = c;
|
||||||
demand_empty_rest_of_line ();
|
demand_empty_rest_of_line ();
|
||||||
@ -14816,7 +14818,7 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
|
|||||||
char *s = name + 3;
|
char *s = name + 3;
|
||||||
|
|
||||||
if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
|
if (!reg_lookup (&s, RTYPE_NUM | RTYPE_GP, &mips_opts.at))
|
||||||
as_bad (_("Unrecognized register name `%s'"), s);
|
as_bad (_("unrecognized register name `%s'"), s);
|
||||||
}
|
}
|
||||||
else if (strcmp (name, "at") == 0)
|
else if (strcmp (name, "at") == 0)
|
||||||
{
|
{
|
||||||
@ -15035,7 +15037,7 @@ s_mipsset (int x ATTRIBUTE_UNUSED)
|
|||||||
}
|
}
|
||||||
else
|
else
|
||||||
{
|
{
|
||||||
as_warn (_("Tried to set unrecognized symbol: %s\n"), name);
|
as_warn (_("tried to set unrecognized symbol: %s\n"), name);
|
||||||
}
|
}
|
||||||
mips_check_isa_supports_ases ();
|
mips_check_isa_supports_ases ();
|
||||||
*input_line_pointer = ch;
|
*input_line_pointer = ch;
|
||||||
@ -15392,7 +15394,7 @@ s_tls_rel_directive (const size_t bytes, const char *dirstr,
|
|||||||
|
|
||||||
if (ex.X_op != O_symbol)
|
if (ex.X_op != O_symbol)
|
||||||
{
|
{
|
||||||
as_bad (_("Unsupported use of %s"), dirstr);
|
as_bad (_("unsupported use of %s"), dirstr);
|
||||||
ignore_rest_of_line ();
|
ignore_rest_of_line ();
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -15483,7 +15485,7 @@ s_gpword (int ignore ATTRIBUTE_UNUSED)
|
|||||||
|
|
||||||
if (ex.X_op != O_symbol || ex.X_add_number != 0)
|
if (ex.X_op != O_symbol || ex.X_add_number != 0)
|
||||||
{
|
{
|
||||||
as_bad (_("Unsupported use of .gpword"));
|
as_bad (_("unsupported use of .gpword"));
|
||||||
ignore_rest_of_line ();
|
ignore_rest_of_line ();
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -15521,7 +15523,7 @@ s_gpdword (int ignore ATTRIBUTE_UNUSED)
|
|||||||
|
|
||||||
if (ex.X_op != O_symbol || ex.X_add_number != 0)
|
if (ex.X_op != O_symbol || ex.X_add_number != 0)
|
||||||
{
|
{
|
||||||
as_bad (_("Unsupported use of .gpdword"));
|
as_bad (_("unsupported use of .gpdword"));
|
||||||
ignore_rest_of_line ();
|
ignore_rest_of_line ();
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -15553,7 +15555,7 @@ s_ehword (int ignore ATTRIBUTE_UNUSED)
|
|||||||
|
|
||||||
if (ex.X_op != O_symbol || ex.X_add_number != 0)
|
if (ex.X_op != O_symbol || ex.X_add_number != 0)
|
||||||
{
|
{
|
||||||
as_bad (_("Unsupported use of .ehword"));
|
as_bad (_("unsupported use of .ehword"));
|
||||||
ignore_rest_of_line ();
|
ignore_rest_of_line ();
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -15628,7 +15630,7 @@ s_nan (int ignore ATTRIBUTE_UNUSED)
|
|||||||
&& memcmp (input_line_pointer, str_legacy, i) == 0)
|
&& memcmp (input_line_pointer, str_legacy, i) == 0)
|
||||||
mips_flag_nan2008 = FALSE;
|
mips_flag_nan2008 = FALSE;
|
||||||
else
|
else
|
||||||
as_bad (_("Bad .nan directive"));
|
as_bad (_("bad .nan directive"));
|
||||||
|
|
||||||
input_line_pointer += i;
|
input_line_pointer += i;
|
||||||
demand_empty_rest_of_line ();
|
demand_empty_rest_of_line ();
|
||||||
@ -16427,7 +16429,8 @@ tc_gen_reloc (asection *section ATTRIBUTE_UNUSED, fixS *fixp)
|
|||||||
if (reloc->howto == NULL)
|
if (reloc->howto == NULL)
|
||||||
{
|
{
|
||||||
as_bad_where (fixp->fx_file, fixp->fx_line,
|
as_bad_where (fixp->fx_file, fixp->fx_line,
|
||||||
_("Can not represent %s relocation in this object file format"),
|
_("cannot represent %s relocation in this object file"
|
||||||
|
" format"),
|
||||||
bfd_get_reloc_code_name (code));
|
bfd_get_reloc_code_name (code));
|
||||||
retval[0] = NULL;
|
retval[0] = NULL;
|
||||||
}
|
}
|
||||||
@ -16521,7 +16524,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
|
|||||||
int i;
|
int i;
|
||||||
|
|
||||||
as_warn_where (fragp->fr_file, fragp->fr_line,
|
as_warn_where (fragp->fr_file, fragp->fr_line,
|
||||||
_("Relaxed out-of-range branch into a jump"));
|
_("relaxed out-of-range branch into a jump"));
|
||||||
|
|
||||||
if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
|
if (RELAX_BRANCH_UNCOND (fragp->fr_subtype))
|
||||||
goto uncond;
|
goto uncond;
|
||||||
@ -16774,7 +16777,7 @@ md_convert_frag (bfd *abfd ATTRIBUTE_UNUSED, segT asec, fragS *fragp)
|
|||||||
|
|
||||||
/* Relax 32-bit branches to a sequence of instructions. */
|
/* Relax 32-bit branches to a sequence of instructions. */
|
||||||
as_warn_where (fragp->fr_file, fragp->fr_line,
|
as_warn_where (fragp->fr_file, fragp->fr_line,
|
||||||
_("Relaxed out-of-range branch into a jump"));
|
_("relaxed out-of-range branch into a jump"));
|
||||||
|
|
||||||
/* Set the short-delay-slot bit. */
|
/* Set the short-delay-slot bit. */
|
||||||
short_ds = al && (insn & 0x02000000) != 0;
|
short_ds = al && (insn & 0x02000000) != 0;
|
||||||
@ -17441,7 +17444,7 @@ s_mips_end (int x ATTRIBUTE_UNUSED)
|
|||||||
|
|
||||||
if (!cur_proc_ptr)
|
if (!cur_proc_ptr)
|
||||||
{
|
{
|
||||||
as_warn (_(".end directive without a preceding .ent directive."));
|
as_warn (_(".end directive without a preceding .ent directive"));
|
||||||
demand_empty_rest_of_line ();
|
demand_empty_rest_of_line ();
|
||||||
return;
|
return;
|
||||||
}
|
}
|
||||||
@ -17450,7 +17453,7 @@ s_mips_end (int x ATTRIBUTE_UNUSED)
|
|||||||
{
|
{
|
||||||
gas_assert (S_GET_NAME (p));
|
gas_assert (S_GET_NAME (p));
|
||||||
if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
|
if (strcmp (S_GET_NAME (p), S_GET_NAME (cur_proc_ptr->func_sym)))
|
||||||
as_warn (_(".end symbol does not match .ent symbol."));
|
as_warn (_(".end symbol does not match .ent symbol"));
|
||||||
|
|
||||||
if (debug_type == DEBUG_STABS)
|
if (debug_type == DEBUG_STABS)
|
||||||
stabs_generate_asm_endfunc (S_GET_NAME (p),
|
stabs_generate_asm_endfunc (S_GET_NAME (p),
|
||||||
@ -17527,7 +17530,7 @@ s_mips_ent (int aent)
|
|||||||
get_number ();
|
get_number ();
|
||||||
|
|
||||||
if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
|
if ((bfd_get_section_flags (stdoutput, now_seg) & SEC_CODE) == 0)
|
||||||
as_warn (_(".ent or .aent not in text section."));
|
as_warn (_(".ent or .aent not in text section"));
|
||||||
|
|
||||||
if (!aent && cur_proc_ptr)
|
if (!aent && cur_proc_ptr)
|
||||||
as_warn (_("missing .end"));
|
as_warn (_("missing .end"));
|
||||||
@ -17583,7 +17586,7 @@ s_mips_frame (int ignore ATTRIBUTE_UNUSED)
|
|||||||
if (*input_line_pointer++ != ','
|
if (*input_line_pointer++ != ','
|
||||||
|| get_absolute_expression_and_terminator (&val) != ',')
|
|| get_absolute_expression_and_terminator (&val) != ',')
|
||||||
{
|
{
|
||||||
as_warn (_("Bad .frame directive"));
|
as_warn (_("bad .frame directive"));
|
||||||
--input_line_pointer;
|
--input_line_pointer;
|
||||||
demand_empty_rest_of_line ();
|
demand_empty_rest_of_line ();
|
||||||
return;
|
return;
|
||||||
@ -17620,7 +17623,7 @@ s_mips_mask (int reg_type)
|
|||||||
|
|
||||||
if (get_absolute_expression_and_terminator (&mask) != ',')
|
if (get_absolute_expression_and_terminator (&mask) != ',')
|
||||||
{
|
{
|
||||||
as_warn (_("Bad .mask/.fmask directive"));
|
as_warn (_("bad .mask/.fmask directive"));
|
||||||
--input_line_pointer;
|
--input_line_pointer;
|
||||||
demand_empty_rest_of_line ();
|
demand_empty_rest_of_line ();
|
||||||
return;
|
return;
|
||||||
@ -17891,7 +17894,7 @@ mips_parse_cpu (const char *option, const char *cpu_string)
|
|||||||
if (mips_matching_cpu_name_p (p->name, cpu_string))
|
if (mips_matching_cpu_name_p (p->name, cpu_string))
|
||||||
return p;
|
return p;
|
||||||
|
|
||||||
as_bad (_("Bad value (%s) for %s"), cpu_string, option);
|
as_bad (_("bad value (%s) for %s"), cpu_string, option);
|
||||||
return 0;
|
return 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
@ -1,3 +1,32 @@
|
|||||||
|
2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
|
||||||
|
|
||||||
|
* gas/mips/ase-errors-1.l, gas/mips/ase-errors-2.l,
|
||||||
|
gas/mips/ase-errors-3.l, gas/mips/ase-errors-4.l, gas/mips/at-2.l,
|
||||||
|
gas/mips/baddata1.l, gas/mips/elf-rel30.l, gas/mips/illegal.l,
|
||||||
|
gas/mips/jalr.l, gas/mips/ldstla-32-1.l, gas/mips/ldstla-32-mips3-1.l,
|
||||||
|
gas/mips/lui-1.l, gas/mips/macro-warn-1.l, gas/mips/macro-warn-1-n32.l,
|
||||||
|
gas/mips/macro-warn-2.l, gas/mips/macro-warn-3.l,
|
||||||
|
gas/mips/macro-warn-4.l, gas/mips/micromips-branch-delay.l,
|
||||||
|
gas/mips/micromips-branch-relax.l,
|
||||||
|
gas/mips/micromips-branch-relax-pic.l, gas/mips/micromips-ill.l,
|
||||||
|
gas/mips/micromips.l, gas/mips/micromips-size-0.l,
|
||||||
|
gas/mips/micromips-size-1.l, gas/mips/micromips-warn-branch-delay.l,
|
||||||
|
gas/mips/micromips-warn.l, gas/mips/mips16e-64.l,
|
||||||
|
gas/mips/mips16e-save-err.l, gas/mips/mips1-fp.l,
|
||||||
|
gas/mips/mips32r2-fp32.l, gas/mips/mips32r2-ill.l,
|
||||||
|
gas/mips/mips32-sf32.l, gas/mips/mips4-branch-likely.l,
|
||||||
|
gas/mips/mips4-fp.l, gas/mips/mips5-fp.l, gas/mips/mips64-mips3d.l,
|
||||||
|
gas/mips/mips-double-float-flag.l, gas/mips/mips-gp64-fp32.l,
|
||||||
|
gas/mips/mips-gp64-fp64.l, gas/mips/mips-hard-float-flag.l,
|
||||||
|
gas/mips/mips-macro-ill-nofp.l, gas/mips/mips-macro-ill-sfp.l,
|
||||||
|
gas/mips/nan-error-1.l, gas/mips/nan-error-2.l, gas/mips/noat-2.l,
|
||||||
|
gas/mips/noat-3.l, gas/mips/noat-4.l, gas/mips/noat-5.l,
|
||||||
|
gas/mips/noat-6.l, gas/mips/noat-7.l, gas/mips/octeon-ill.l,
|
||||||
|
gas/mips/r5900-error-vu0.l, gas/mips/r5900-nollsc.l,
|
||||||
|
gas/mips/relax-bc1any.l, gas/mips/relax-bposge.l, gas/mips/relax.l,
|
||||||
|
gas/mips/relax-swap1.l, gas/mips/relax-swap2.l, gas/mips/set-arch.l,
|
||||||
|
gas/mips/tls-ill.l, gas/mips/vr5400-ill.l: Adjust expected output.
|
||||||
|
|
||||||
2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
|
2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
|
||||||
|
|
||||||
* gas/mips/ext-ill.l, gas/mips/mips64r2-ill.l: Expect DEXT and DINS
|
* gas/mips/ext-ill.l, gas/mips/mips64r2-ill.l: Expect DEXT and DINS
|
||||||
|
|||||||
@ -1,42 +1,42 @@
|
|||||||
.*Assembler messages:
|
.*Assembler messages:
|
||||||
.*:6: Error: Opcode not supported.* `ldx \$4,\$5\(\$6\)'
|
.*:6: Error: opcode not supported.* `ldx \$4,\$5\(\$6\)'
|
||||||
.*:7: Error: Opcode not supported.* `absq_s\.qb \$3,\$4'
|
.*:7: Error: opcode not supported.* `absq_s\.qb \$3,\$4'
|
||||||
.*:9: Warning: The `dsp' extension requires MIPS32 revision 2 or greater
|
.*:9: Warning: the `dsp' extension requires MIPS32 revision 2 or greater
|
||||||
.*:11: Error: Opcode not supported.* `ldx \$4,\$5\(\$6\)'
|
.*:11: Error: opcode not supported.* `ldx \$4,\$5\(\$6\)'
|
||||||
.*:12: Error: Opcode not supported.* `absq_s\.qb \$3,\$4'
|
.*:12: Error: opcode not supported.* `absq_s\.qb \$3,\$4'
|
||||||
.*:14: Error: Opcode not supported.* `lbux \$4,\$5\(\$6\)'
|
.*:14: Error: opcode not supported.* `lbux \$4,\$5\(\$6\)'
|
||||||
.*:15: Error: Opcode not supported.* `ldx \$4,\$5\(\$6\)'
|
.*:15: Error: opcode not supported.* `ldx \$4,\$5\(\$6\)'
|
||||||
.*:16: Error: Opcode not supported.* `absq_s\.qb \$3,\$4'
|
.*:16: Error: opcode not supported.* `absq_s\.qb \$3,\$4'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:22: Error: Opcode not supported.* `ldx \$4,\$5\(\$6\)'
|
.*:22: Error: opcode not supported.* `ldx \$4,\$5\(\$6\)'
|
||||||
.*:25: Warning: The `dspr2' extension requires MIPS32 revision 2 or greater
|
.*:25: Warning: the `dspr2' extension requires MIPS32 revision 2 or greater
|
||||||
.*:27: Error: Opcode not supported.* `ldx \$4,\$5\(\$6\)'
|
.*:27: Error: opcode not supported.* `ldx \$4,\$5\(\$6\)'
|
||||||
.*:30: Error: Opcode not supported.* `lbux \$4,\$5\(\$6\)'
|
.*:30: Error: opcode not supported.* `lbux \$4,\$5\(\$6\)'
|
||||||
.*:31: Error: Opcode not supported.* `ldx \$4,\$5\(\$6\)'
|
.*:31: Error: opcode not supported.* `ldx \$4,\$5\(\$6\)'
|
||||||
.*:32: Error: Opcode not supported.* `absq_s\.qb \$3,\$4'
|
.*:32: Error: opcode not supported.* `absq_s\.qb \$3,\$4'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:39: Warning: The `mcu' extension requires MIPS32 revision 2 or greater
|
.*:39: Warning: the `mcu' extension requires MIPS32 revision 2 or greater
|
||||||
.*:42: Error: Opcode not supported.* `aclr 4,100\(\$4\)'
|
.*:42: Error: opcode not supported.* `aclr 4,100\(\$4\)'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:46: Warning: The 32-bit MIPS architecture does not support the `mdmx' extension
|
.*:46: Warning: the 32-bit MIPS architecture does not support the `mdmx' extension
|
||||||
.*:48: Warning: The `mdmx' extension requires 64-bit FPRs
|
.*:48: Warning: the `mdmx' extension requires 64-bit FPRs
|
||||||
.*:51: Error: Opcode not supported.* `add.ob \$f4,\$f6,\$f8'
|
.*:51: Error: opcode not supported.* `add.ob \$f4,\$f6,\$f8'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:57: Warning: The `mips3d' extension requires 64-bit FPRs
|
.*:57: Warning: the `mips3d' extension requires 64-bit FPRs
|
||||||
.*:58: Warning: The `mips3d' extension requires MIPS32 revision 2 or greater
|
.*:58: Warning: the `mips3d' extension requires MIPS32 revision 2 or greater
|
||||||
.*:61: Error: Opcode not supported.* `addr.ps \$f4,\$f6,\$f8'
|
.*:61: Error: opcode not supported.* `addr.ps \$f4,\$f6,\$f8'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:68: Warning: The `mt' extension requires MIPS32 revision 2 or greater
|
.*:68: Warning: the `mt' extension requires MIPS32 revision 2 or greater
|
||||||
.*:71: Error: Opcode not supported.* `dmt *'
|
.*:71: Error: opcode not supported.* `dmt *'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:77: Warning: The `smartmips' extension requires MIPS32 revision 1 or greater
|
.*:77: Warning: the `smartmips' extension requires MIPS32 revision 1 or greater
|
||||||
.*:80: Error: Opcode not supported.* `maddp \$4,\$5'
|
.*:80: Error: opcode not supported.* `maddp \$4,\$5'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:86: Error: Opcode not supported.* `dmfgc0 \$3,\$29'
|
.*:86: Error: opcode not supported.* `dmfgc0 \$3,\$29'
|
||||||
.*:88: Warning: The `virt' extension requires MIPS32 revision 2 or greater
|
.*:88: Warning: the `virt' extension requires MIPS32 revision 2 or greater
|
||||||
.*:90: Error: Opcode not supported.* `dmfgc0 \$3,\$29'
|
.*:90: Error: opcode not supported.* `dmfgc0 \$3,\$29'
|
||||||
.*:92: Error: Opcode not supported.* `hypcall *'
|
.*:92: Error: opcode not supported.* `hypcall *'
|
||||||
.*:93: Error: Opcode not supported.* `dmfgc0 \$3,\$29'
|
.*:93: Error: opcode not supported.* `dmfgc0 \$3,\$29'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:100: Warning: The `eva' extension requires MIPS32 revision 2 or greater
|
.*:100: Warning: the `eva' extension requires MIPS32 revision 2 or greater
|
||||||
.*:103: Error: Opcode not supported.* `lbue \$4,16\(\$5\)'
|
.*:103: Error: opcode not supported.* `lbue \$4,16\(\$5\)'
|
||||||
|
|||||||
@ -1,34 +1,34 @@
|
|||||||
.*Assembler messages:
|
.*Assembler messages:
|
||||||
.*:6: Error: Opcode not supported.* `absq_s\.qb \$3,\$4'
|
.*:6: Error: opcode not supported.* `absq_s\.qb \$3,\$4'
|
||||||
.*:7: Warning: The `dsp' extension requires MIPS64 revision 2 or greater
|
.*:7: Warning: the `dsp' extension requires MIPS64 revision 2 or greater
|
||||||
.*:10: Error: Opcode not supported.* `absq_s\.qb \$3,\$4'
|
.*:10: Error: opcode not supported.* `absq_s\.qb \$3,\$4'
|
||||||
.*:12: Error: Opcode not supported.* `lbux \$4,\$5\(\$6\)'
|
.*:12: Error: opcode not supported.* `lbux \$4,\$5\(\$6\)'
|
||||||
.*:13: Error: Opcode not supported.* `ldx \$4,\$5\(\$6\)'
|
.*:13: Error: opcode not supported.* `ldx \$4,\$5\(\$6\)'
|
||||||
.*:14: Error: Opcode not supported.* `absq_s\.qb \$3,\$4'
|
.*:14: Error: opcode not supported.* `absq_s\.qb \$3,\$4'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:21: Warning: The `dspr2' extension requires MIPS64 revision 2 or greater
|
.*:21: Warning: the `dspr2' extension requires MIPS64 revision 2 or greater
|
||||||
.*:26: Error: Opcode not supported.* `lbux \$4,\$5\(\$6\)'
|
.*:26: Error: opcode not supported.* `lbux \$4,\$5\(\$6\)'
|
||||||
.*:27: Error: Opcode not supported.* `ldx \$4,\$5\(\$6\)'
|
.*:27: Error: opcode not supported.* `ldx \$4,\$5\(\$6\)'
|
||||||
.*:28: Error: Opcode not supported.* `absq_s\.qb \$3,\$4'
|
.*:28: Error: opcode not supported.* `absq_s\.qb \$3,\$4'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:33: Warning: The `mcu' extension requires MIPS64 revision 2 or greater
|
.*:33: Warning: the `mcu' extension requires MIPS64 revision 2 or greater
|
||||||
.*:36: Error: Opcode not supported.* `aclr 4,100\(\$4\)'
|
.*:36: Error: opcode not supported.* `aclr 4,100\(\$4\)'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:41: Warning: The `mdmx' extension requires MIPS64 revision 1 or greater
|
.*:41: Warning: the `mdmx' extension requires MIPS64 revision 1 or greater
|
||||||
.*:44: Error: Opcode not supported.* `add.ob \$f4,\$f6,\$f8'
|
.*:44: Error: opcode not supported.* `add.ob \$f4,\$f6,\$f8'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:49: Warning: The `mips3d' extension requires MIPS64 revision 1 or greater
|
.*:49: Warning: the `mips3d' extension requires MIPS64 revision 1 or greater
|
||||||
.*:52: Error: Opcode not supported.* `addr.ps \$f4,\$f6,\$f8'
|
.*:52: Error: opcode not supported.* `addr.ps \$f4,\$f6,\$f8'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:57: Warning: The `mt' extension requires MIPS64 revision 2 or greater
|
.*:57: Warning: the `mt' extension requires MIPS64 revision 2 or greater
|
||||||
.*:60: Error: Opcode not supported.* `dmt *'
|
.*:60: Error: opcode not supported.* `dmt *'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:63: Warning: The 64-bit MIPS architecture does not support the `smartmips' extension
|
.*:63: Warning: the 64-bit MIPS architecture does not support the `smartmips' extension
|
||||||
.*:68: Error: Opcode not supported.* `maddp \$4,\$5'
|
.*:68: Error: opcode not supported.* `maddp \$4,\$5'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:74: Warning: The `virt' extension requires MIPS64 revision 2 or greater
|
.*:74: Warning: the `virt' extension requires MIPS64 revision 2 or greater
|
||||||
.*:78: Error: Opcode not supported.* `hypcall *'
|
.*:78: Error: opcode not supported.* `hypcall *'
|
||||||
.*:79: Error: Opcode not supported.* `dmfgc0 \$3,\$29'
|
.*:79: Error: opcode not supported.* `dmfgc0 \$3,\$29'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:84: Warning: The `eva' extension requires MIPS64 revision 2 or greater
|
.*:84: Warning: the `eva' extension requires MIPS64 revision 2 or greater
|
||||||
.*:87: Error: Opcode not supported.* `lbue \$4,16\(\$5\)'
|
.*:87: Error: opcode not supported.* `lbue \$4,16\(\$5\)'
|
||||||
|
|||||||
@ -1,30 +1,30 @@
|
|||||||
.*Assembler messages:
|
.*Assembler messages:
|
||||||
.*:5: Error: Unrecognized opcode `ldx \$4,\$5\(\$6\)'
|
.*:5: Error: unrecognized opcode `ldx \$4,\$5\(\$6\)'
|
||||||
.*:6: Error: Opcode not supported.* `absq_s\.qb \$3,\$4'
|
.*:6: Error: opcode not supported.* `absq_s\.qb \$3,\$4'
|
||||||
.*:9: Error: Opcode not supported.* `lbux \$4,\$5\(\$6\)'
|
.*:9: Error: opcode not supported.* `lbux \$4,\$5\(\$6\)'
|
||||||
.*:10: Error: Opcode not supported.* `absq_s\.qb \$3,\$4'
|
.*:10: Error: opcode not supported.* `absq_s\.qb \$3,\$4'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:18: Error: Opcode not supported.* `lbux \$4,\$5\(\$6\)'
|
.*:18: Error: opcode not supported.* `lbux \$4,\$5\(\$6\)'
|
||||||
.*:19: Error: Opcode not supported.* `absq_s\.qb \$3,\$4'
|
.*:19: Error: opcode not supported.* `absq_s\.qb \$3,\$4'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:26: Error: Opcode not supported.* `aclr 4,100\(\$4\)'
|
.*:26: Error: opcode not supported.* `aclr 4,100\(\$4\)'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:29: Warning: The 32-bit microMIPS architecture does not support the `mdmx' extension
|
.*:29: Warning: the 32-bit microMIPS architecture does not support the `mdmx' extension
|
||||||
.*:29: Warning: The `mdmx' extension requires 64-bit FPRs
|
.*:29: Warning: the `mdmx' extension requires 64-bit FPRs
|
||||||
.*:30: Error: Unrecognized opcode `add.ob \$f4,\$f6,\$f8'
|
.*:30: Error: unrecognized opcode `add.ob \$f4,\$f6,\$f8'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:34: Warning: The 32-bit microMIPS architecture does not support the `mips3d' extension
|
.*:34: Warning: the 32-bit microMIPS architecture does not support the `mips3d' extension
|
||||||
.*:34: Warning: The `mips3d' extension requires 64-bit FPRs
|
.*:34: Warning: the `mips3d' extension requires 64-bit FPRs
|
||||||
.*:35: Error: Unrecognized opcode `addr.ps \$f4,\$f6,\$f8'
|
.*:35: Error: unrecognized opcode `addr.ps \$f4,\$f6,\$f8'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:39: Warning: The 32-bit microMIPS architecture does not support the `mt' extension
|
.*:39: Warning: the 32-bit microMIPS architecture does not support the `mt' extension
|
||||||
.*:40: Error: Unrecognized opcode `dmt *'
|
.*:40: Error: unrecognized opcode `dmt *'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:44: Warning: The 32-bit microMIPS architecture does not support the `smartmips' extension
|
.*:44: Warning: the 32-bit microMIPS architecture does not support the `smartmips' extension
|
||||||
.*:45: Error: Unrecognized opcode `maddp \$4,\$5'
|
.*:45: Error: unrecognized opcode `maddp \$4,\$5'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:51: Error: Opcode not supported.* `dmfgc0 \$3,\$29'
|
.*:51: Error: opcode not supported.* `dmfgc0 \$3,\$29'
|
||||||
.*:54: Error: Opcode not supported.* `hypcall *'
|
.*:54: Error: opcode not supported.* `hypcall *'
|
||||||
.*:55: Error: Opcode not supported.* `dmfgc0 \$3,\$29'
|
.*:55: Error: opcode not supported.* `dmfgc0 \$3,\$29'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:65: Error: Opcode not supported.* `lbue \$4,16\(\$5\)'
|
.*:65: Error: opcode not supported.* `lbue \$4,16\(\$5\)'
|
||||||
|
|||||||
@ -1,27 +1,27 @@
|
|||||||
.*Assembler messages:
|
.*Assembler messages:
|
||||||
.*:5: Error: Unrecognized opcode `ldx \$4,\$5\(\$6\)'
|
.*:5: Error: unrecognized opcode `ldx \$4,\$5\(\$6\)'
|
||||||
.*:6: Error: Opcode not supported.* `absq_s\.qb \$3,\$4'
|
.*:6: Error: opcode not supported.* `absq_s\.qb \$3,\$4'
|
||||||
.*:9: Error: Opcode not supported.* `lbux \$4,\$5\(\$6\)'
|
.*:9: Error: opcode not supported.* `lbux \$4,\$5\(\$6\)'
|
||||||
.*:10: Error: Opcode not supported.* `absq_s\.qb \$3,\$4'
|
.*:10: Error: opcode not supported.* `absq_s\.qb \$3,\$4'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:18: Error: Opcode not supported.* `lbux \$4,\$5\(\$6\)'
|
.*:18: Error: opcode not supported.* `lbux \$4,\$5\(\$6\)'
|
||||||
.*:19: Error: Opcode not supported.* `absq_s\.qb \$3,\$4'
|
.*:19: Error: opcode not supported.* `absq_s\.qb \$3,\$4'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:26: Error: Opcode not supported.* `aclr 4,100\(\$4\)'
|
.*:26: Error: opcode not supported.* `aclr 4,100\(\$4\)'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:29: Warning: The 64-bit microMIPS architecture does not support the `mdmx' extension
|
.*:29: Warning: the 64-bit microMIPS architecture does not support the `mdmx' extension
|
||||||
.*:30: Error: Unrecognized opcode `add.ob \$f4,\$f6,\$f8'
|
.*:30: Error: unrecognized opcode `add.ob \$f4,\$f6,\$f8'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:34: Warning: The 64-bit microMIPS architecture does not support the `mips3d' extension
|
.*:34: Warning: the 64-bit microMIPS architecture does not support the `mips3d' extension
|
||||||
.*:35: Error: Unrecognized opcode `addr.ps \$f4,\$f6,\$f8'
|
.*:35: Error: unrecognized opcode `addr.ps \$f4,\$f6,\$f8'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:39: Warning: The 64-bit microMIPS architecture does not support the `mt' extension
|
.*:39: Warning: the 64-bit microMIPS architecture does not support the `mt' extension
|
||||||
.*:40: Error: Unrecognized opcode `dmt *'
|
.*:40: Error: unrecognized opcode `dmt *'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:44: Warning: The 64-bit microMIPS architecture does not support the `smartmips' extension
|
.*:44: Warning: the 64-bit microMIPS architecture does not support the `smartmips' extension
|
||||||
.*:45: Error: Unrecognized opcode `maddp \$4,\$5'
|
.*:45: Error: unrecognized opcode `maddp \$4,\$5'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:54: Error: Opcode not supported.* `hypcall *'
|
.*:54: Error: opcode not supported.* `hypcall *'
|
||||||
.*:55: Error: Opcode not supported.* `dmfgc0 \$3,\$29'
|
.*:55: Error: opcode not supported.* `dmfgc0 \$3,\$29'
|
||||||
# ----------------------------------------------------------------------------
|
# ----------------------------------------------------------------------------
|
||||||
.*:63: Error: Opcode not supported.* `lbue \$4,16\(\$5\)'
|
.*:63: Error: opcode not supported.* `lbue \$4,16\(\$5\)'
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
.*\.s: Assembler messages:
|
.*\.s: Assembler messages:
|
||||||
.*\.s:4: Error: Macro used \$at after ".set noat"
|
.*\.s:4: Error: macro used \$at after ".set noat"
|
||||||
.*\.s:5: Error: Macro used \$at after ".set noat"
|
.*\.s:5: Error: macro used \$at after ".set noat"
|
||||||
.*\.s:6: Error: Macro used \$at after ".set noat"
|
.*\.s:6: Error: macro used \$at after ".set noat"
|
||||||
.*\.s:8: Warning: Used \$at without ".set noat"
|
.*\.s:8: Warning: used \$at without ".set noat"
|
||||||
.*\.s:13: Warning: Used \$26 with ".set at=\$26"
|
.*\.s:13: Warning: used \$26 with ".set at=\$26"
|
||||||
.*\.s:18: Warning: Used \$27 with ".set at=\$27"
|
.*\.s:18: Warning: used \$27 with ".set at=\$27"
|
||||||
|
|||||||
@ -1,3 +1,3 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:8: Error: Can not represent BFD_RELOC_8 relocation in this object file format
|
.*:8: Error: cannot represent BFD_RELOC_8 relocation in this object file format
|
||||||
.*:9: Error: Can not represent BFD_RELOC_8 relocation in this object file format
|
.*:9: Error: cannot represent BFD_RELOC_8 relocation in this object file format
|
||||||
|
|||||||
@ -1,26 +1,26 @@
|
|||||||
.*:
|
.*:
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: Unsupported constant in relocation
|
.*: unsupported constant in relocation
|
||||||
.*: TLS relocation against a constant
|
.*: TLS relocation against a constant
|
||||||
.*: TLS relocation against a constant
|
.*: TLS relocation against a constant
|
||||||
.*: TLS relocation against a constant
|
.*: TLS relocation against a constant
|
||||||
|
|||||||
@ -1,3 +1,3 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:4: Error: Illegal operands `move 1,2'
|
.*:4: Error: invalid operands `move 1,2'
|
||||||
.*:5: Error: Illegal operands `c.eq.s 1,2'
|
.*:5: Error: invalid operands `c.eq.s 1,2'
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:1: Error: Illegal operands.*
|
.*:1: Error: invalid operands.*
|
||||||
.*:2: Error: A destination register must be supplied.*
|
.*:2: Error: a destination register must be supplied.*
|
||||||
.*:3: Error: Source and destination must be different.*
|
.*:3: Error: source and destination must be different.*
|
||||||
.*:10: Error: Illegal operands.*
|
.*:10: Error: invalid operands.*
|
||||||
.*:11: Error: A destination register must be supplied.*
|
.*:11: Error: a destination register must be supplied.*
|
||||||
.*:12: Error: Source and destination must be different.*
|
.*:12: Error: source and destination must be different.*
|
||||||
|
|||||||
@ -1,81 +1,81 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:3: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
|
.*:3: Error: number \(0xfffffffeffffffff\) larger than 32 bits
|
||||||
.*:4: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:4: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:5: Error: Number \(0xabcdef0123456789\) larger than 32 bits
|
.*:5: Error: number \(0xabcdef0123456789\) larger than 32 bits
|
||||||
.*:6: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
|
.*:6: Error: number \(0x0*123456789abcdef\) larger than 32 bits
|
||||||
.*:7: Error: Number \(0x0*1ffffffff\) larger than 32 bits
|
.*:7: Error: number \(0x0*1ffffffff\) larger than 32 bits
|
||||||
.*:8: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:8: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:10: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
|
.*:10: Error: number \(0xfffffffeffffffff\) larger than 32 bits
|
||||||
.*:11: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:11: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:12: Error: Number \(0xabcdef0123456789\) larger than 32 bits
|
.*:12: Error: number \(0xabcdef0123456789\) larger than 32 bits
|
||||||
.*:13: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
|
.*:13: Error: number \(0x0*123456789abcdef\) larger than 32 bits
|
||||||
.*:14: Error: Number \(0x0*1ffffffff\) larger than 32 bits
|
.*:14: Error: number \(0x0*1ffffffff\) larger than 32 bits
|
||||||
.*:15: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:15: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:17: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
|
.*:17: Error: number \(0xfffffffeffffffff\) larger than 32 bits
|
||||||
.*:18: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:18: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:19: Error: Number \(0xabcdef0123456789\) larger than 32 bits
|
.*:19: Error: number \(0xabcdef0123456789\) larger than 32 bits
|
||||||
.*:20: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
|
.*:20: Error: number \(0x0*123456789abcdef\) larger than 32 bits
|
||||||
.*:21: Error: Number \(0x0*1ffffffff\) larger than 32 bits
|
.*:21: Error: number \(0x0*1ffffffff\) larger than 32 bits
|
||||||
.*:22: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:22: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:24: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
|
.*:24: Error: number \(0xfffffffeffffffff\) larger than 32 bits
|
||||||
.*:25: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:25: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:26: Error: Number \(0xabcdef0123456789\) larger than 32 bits
|
.*:26: Error: number \(0xabcdef0123456789\) larger than 32 bits
|
||||||
.*:27: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
|
.*:27: Error: number \(0x0*123456789abcdef\) larger than 32 bits
|
||||||
.*:28: Error: Number \(0x0*1ffffffff\) larger than 32 bits
|
.*:28: Error: number \(0x0*1ffffffff\) larger than 32 bits
|
||||||
.*:29: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:29: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:31: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
|
.*:31: Error: number \(0xfffffffeffffffff\) larger than 32 bits
|
||||||
.*:32: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:32: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:32: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:32: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:33: Error: Number \(0xabcdef0123456789\) larger than 32 bits
|
.*:33: Error: number \(0xabcdef0123456789\) larger than 32 bits
|
||||||
.*:33: Error: Number \(0xabcdef0123450000\) larger than 32 bits
|
.*:33: Error: number \(0xabcdef0123450000\) larger than 32 bits
|
||||||
.*:34: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
|
.*:34: Error: number \(0x0*123456789abcdef\) larger than 32 bits
|
||||||
.*:34: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
|
.*:34: Error: number \(0x0*123456789ac0000\) larger than 32 bits
|
||||||
.*:35: Error: Number \(0x0*1ffffffff\) larger than 32 bits
|
.*:35: Error: number \(0x0*1ffffffff\) larger than 32 bits
|
||||||
.*:35: Error: Number \(0x0*200000000\) larger than 32 bits
|
.*:35: Error: number \(0x0*200000000\) larger than 32 bits
|
||||||
.*:36: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:36: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:36: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:36: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:38: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
|
.*:38: Error: number \(0xfffffffeffffffff\) larger than 32 bits
|
||||||
.*:39: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:39: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:39: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:39: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:40: Error: Number \(0xabcdef0123456789\) larger than 32 bits
|
.*:40: Error: number \(0xabcdef0123456789\) larger than 32 bits
|
||||||
.*:40: Error: Number \(0xabcdef0123450000\) larger than 32 bits
|
.*:40: Error: number \(0xabcdef0123450000\) larger than 32 bits
|
||||||
.*:41: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
|
.*:41: Error: number \(0x0*123456789abcdef\) larger than 32 bits
|
||||||
.*:41: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
|
.*:41: Error: number \(0x0*123456789ac0000\) larger than 32 bits
|
||||||
.*:42: Error: Number \(0x0*1ffffffff\) larger than 32 bits
|
.*:42: Error: number \(0x0*1ffffffff\) larger than 32 bits
|
||||||
.*:42: Error: Number \(0x0*200000000\) larger than 32 bits
|
.*:42: Error: number \(0x0*200000000\) larger than 32 bits
|
||||||
.*:43: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:43: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:43: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:43: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:45: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
|
.*:45: Error: number \(0xfffffffeffffffff\) larger than 32 bits
|
||||||
.*:46: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:46: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:46: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:46: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:47: Error: Number \(0xabcdef0123456789\) larger than 32 bits
|
.*:47: Error: number \(0xabcdef0123456789\) larger than 32 bits
|
||||||
.*:47: Error: Number \(0xabcdef0123450000\) larger than 32 bits
|
.*:47: Error: number \(0xabcdef0123450000\) larger than 32 bits
|
||||||
.*:48: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
|
.*:48: Error: number \(0x0*123456789abcdef\) larger than 32 bits
|
||||||
.*:48: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
|
.*:48: Error: number \(0x0*123456789ac0000\) larger than 32 bits
|
||||||
.*:49: Error: Number \(0x0*1ffffffff\) larger than 32 bits
|
.*:49: Error: number \(0x0*1ffffffff\) larger than 32 bits
|
||||||
.*:49: Error: Number \(0x0*200000000\) larger than 32 bits
|
.*:49: Error: number \(0x0*200000000\) larger than 32 bits
|
||||||
.*:50: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:50: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:50: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:50: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:52: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
|
.*:52: Error: number \(0xfffffffeffffffff\) larger than 32 bits
|
||||||
.*:53: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:53: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:53: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:53: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:54: Error: Number \(0xabcdef0123456789\) larger than 32 bits
|
.*:54: Error: number \(0xabcdef0123456789\) larger than 32 bits
|
||||||
.*:54: Error: Number \(0xabcdef0123450000\) larger than 32 bits
|
.*:54: Error: number \(0xabcdef0123450000\) larger than 32 bits
|
||||||
.*:55: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
|
.*:55: Error: number \(0x0*123456789abcdef\) larger than 32 bits
|
||||||
.*:55: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
|
.*:55: Error: number \(0x0*123456789ac0000\) larger than 32 bits
|
||||||
.*:56: Error: Number \(0x0*1ffffffff\) larger than 32 bits
|
.*:56: Error: number \(0x0*1ffffffff\) larger than 32 bits
|
||||||
.*:56: Error: Number \(0x0*200000000\) larger than 32 bits
|
.*:56: Error: number \(0x0*200000000\) larger than 32 bits
|
||||||
.*:57: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:57: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:57: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:57: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:59: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
|
.*:59: Error: number \(0xfffffffeffffffff\) larger than 32 bits
|
||||||
.*:60: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:60: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:61: Error: Number \(0xabcdef0123456789\) larger than 32 bits
|
.*:61: Error: number \(0xabcdef0123456789\) larger than 32 bits
|
||||||
.*:62: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
|
.*:62: Error: number \(0x0*123456789abcdef\) larger than 32 bits
|
||||||
.*:63: Error: Number \(0x0*1ffffffff\) larger than 32 bits
|
.*:63: Error: number \(0x0*1ffffffff\) larger than 32 bits
|
||||||
.*:64: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:64: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:66: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
|
.*:66: Error: number \(0xfffffffeffffffff\) larger than 32 bits
|
||||||
.*:67: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:67: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:68: Error: Number \(0xabcdef0123456789\) larger than 32 bits
|
.*:68: Error: number \(0xabcdef0123456789\) larger than 32 bits
|
||||||
.*:69: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
|
.*:69: Error: number \(0x0*123456789abcdef\) larger than 32 bits
|
||||||
.*:70: Error: Number \(0x0*1ffffffff\) larger than 32 bits
|
.*:70: Error: number \(0x0*1ffffffff\) larger than 32 bits
|
||||||
.*:71: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:71: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
|
|||||||
@ -1,101 +1,101 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:3: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
|
.*:3: Error: number \(0xfffffffeffffffff\) larger than 32 bits
|
||||||
.*:4: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:4: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:4: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:4: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:5: Error: Number \(0xabcdef0123456789\) larger than 32 bits
|
.*:5: Error: number \(0xabcdef0123456789\) larger than 32 bits
|
||||||
.*:5: Error: Number \(0xabcdef0123450000\) larger than 32 bits
|
.*:5: Error: number \(0xabcdef0123450000\) larger than 32 bits
|
||||||
.*:6: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
|
.*:6: Error: number \(0x0*123456789abcdef\) larger than 32 bits
|
||||||
.*:6: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
|
.*:6: Error: number \(0x0*123456789ac0000\) larger than 32 bits
|
||||||
.*:7: Error: Number \(0x0*1ffffffff\) larger than 32 bits
|
.*:7: Error: number \(0x0*1ffffffff\) larger than 32 bits
|
||||||
.*:7: Error: Number \(0x0*200000000\) larger than 32 bits
|
.*:7: Error: number \(0x0*200000000\) larger than 32 bits
|
||||||
.*:8: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:8: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:8: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:8: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:10: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
|
.*:10: Error: number \(0xfffffffeffffffff\) larger than 32 bits
|
||||||
.*:11: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:11: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:11: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:11: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:12: Error: Number \(0xabcdef0123456789\) larger than 32 bits
|
.*:12: Error: number \(0xabcdef0123456789\) larger than 32 bits
|
||||||
.*:12: Error: Number \(0xabcdef0123450000\) larger than 32 bits
|
.*:12: Error: number \(0xabcdef0123450000\) larger than 32 bits
|
||||||
.*:13: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
|
.*:13: Error: number \(0x0*123456789abcdef\) larger than 32 bits
|
||||||
.*:13: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
|
.*:13: Error: number \(0x0*123456789ac0000\) larger than 32 bits
|
||||||
.*:14: Error: Number \(0x0*1ffffffff\) larger than 32 bits
|
.*:14: Error: number \(0x0*1ffffffff\) larger than 32 bits
|
||||||
.*:14: Error: Number \(0x0*200000000\) larger than 32 bits
|
.*:14: Error: number \(0x0*200000000\) larger than 32 bits
|
||||||
.*:15: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:15: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:15: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:15: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:17: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
|
.*:17: Error: number \(0xfffffffeffffffff\) larger than 32 bits
|
||||||
.*:18: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:18: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:18: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:18: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:19: Error: Number \(0xabcdef0123456789\) larger than 32 bits
|
.*:19: Error: number \(0xabcdef0123456789\) larger than 32 bits
|
||||||
.*:19: Error: Number \(0xabcdef0123450000\) larger than 32 bits
|
.*:19: Error: number \(0xabcdef0123450000\) larger than 32 bits
|
||||||
.*:20: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
|
.*:20: Error: number \(0x0*123456789abcdef\) larger than 32 bits
|
||||||
.*:20: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
|
.*:20: Error: number \(0x0*123456789ac0000\) larger than 32 bits
|
||||||
.*:21: Error: Number \(0x0*1ffffffff\) larger than 32 bits
|
.*:21: Error: number \(0x0*1ffffffff\) larger than 32 bits
|
||||||
.*:21: Error: Number \(0x0*200000000\) larger than 32 bits
|
.*:21: Error: number \(0x0*200000000\) larger than 32 bits
|
||||||
.*:22: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:22: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:22: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:22: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:24: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
|
.*:24: Error: number \(0xfffffffeffffffff\) larger than 32 bits
|
||||||
.*:25: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:25: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:25: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:25: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:26: Error: Number \(0xabcdef0123456789\) larger than 32 bits
|
.*:26: Error: number \(0xabcdef0123456789\) larger than 32 bits
|
||||||
.*:26: Error: Number \(0xabcdef0123450000\) larger than 32 bits
|
.*:26: Error: number \(0xabcdef0123450000\) larger than 32 bits
|
||||||
.*:27: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
|
.*:27: Error: number \(0x0*123456789abcdef\) larger than 32 bits
|
||||||
.*:27: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
|
.*:27: Error: number \(0x0*123456789ac0000\) larger than 32 bits
|
||||||
.*:28: Error: Number \(0x0*1ffffffff\) larger than 32 bits
|
.*:28: Error: number \(0x0*1ffffffff\) larger than 32 bits
|
||||||
.*:28: Error: Number \(0x0*200000000\) larger than 32 bits
|
.*:28: Error: number \(0x0*200000000\) larger than 32 bits
|
||||||
.*:29: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:29: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:29: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:29: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:31: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
|
.*:31: Error: number \(0xfffffffeffffffff\) larger than 32 bits
|
||||||
.*:32: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:32: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:32: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:32: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:33: Error: Number \(0xabcdef0123456789\) larger than 32 bits
|
.*:33: Error: number \(0xabcdef0123456789\) larger than 32 bits
|
||||||
.*:33: Error: Number \(0xabcdef0123450000\) larger than 32 bits
|
.*:33: Error: number \(0xabcdef0123450000\) larger than 32 bits
|
||||||
.*:34: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
|
.*:34: Error: number \(0x0*123456789abcdef\) larger than 32 bits
|
||||||
.*:34: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
|
.*:34: Error: number \(0x0*123456789ac0000\) larger than 32 bits
|
||||||
.*:35: Error: Number \(0x0*1ffffffff\) larger than 32 bits
|
.*:35: Error: number \(0x0*1ffffffff\) larger than 32 bits
|
||||||
.*:35: Error: Number \(0x0*200000000\) larger than 32 bits
|
.*:35: Error: number \(0x0*200000000\) larger than 32 bits
|
||||||
.*:36: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:36: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:36: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:36: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:38: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
|
.*:38: Error: number \(0xfffffffeffffffff\) larger than 32 bits
|
||||||
.*:39: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:39: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:39: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:39: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:40: Error: Number \(0xabcdef0123456789\) larger than 32 bits
|
.*:40: Error: number \(0xabcdef0123456789\) larger than 32 bits
|
||||||
.*:40: Error: Number \(0xabcdef0123450000\) larger than 32 bits
|
.*:40: Error: number \(0xabcdef0123450000\) larger than 32 bits
|
||||||
.*:41: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
|
.*:41: Error: number \(0x0*123456789abcdef\) larger than 32 bits
|
||||||
.*:41: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
|
.*:41: Error: number \(0x0*123456789ac0000\) larger than 32 bits
|
||||||
.*:42: Error: Number \(0x0*1ffffffff\) larger than 32 bits
|
.*:42: Error: number \(0x0*1ffffffff\) larger than 32 bits
|
||||||
.*:42: Error: Number \(0x0*200000000\) larger than 32 bits
|
.*:42: Error: number \(0x0*200000000\) larger than 32 bits
|
||||||
.*:43: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:43: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:43: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:43: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:45: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
|
.*:45: Error: number \(0xfffffffeffffffff\) larger than 32 bits
|
||||||
.*:46: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:46: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:46: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:46: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:47: Error: Number \(0xabcdef0123456789\) larger than 32 bits
|
.*:47: Error: number \(0xabcdef0123456789\) larger than 32 bits
|
||||||
.*:47: Error: Number \(0xabcdef0123450000\) larger than 32 bits
|
.*:47: Error: number \(0xabcdef0123450000\) larger than 32 bits
|
||||||
.*:48: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
|
.*:48: Error: number \(0x0*123456789abcdef\) larger than 32 bits
|
||||||
.*:48: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
|
.*:48: Error: number \(0x0*123456789ac0000\) larger than 32 bits
|
||||||
.*:49: Error: Number \(0x0*1ffffffff\) larger than 32 bits
|
.*:49: Error: number \(0x0*1ffffffff\) larger than 32 bits
|
||||||
.*:49: Error: Number \(0x0*200000000\) larger than 32 bits
|
.*:49: Error: number \(0x0*200000000\) larger than 32 bits
|
||||||
.*:50: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:50: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:50: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:50: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:52: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
|
.*:52: Error: number \(0xfffffffeffffffff\) larger than 32 bits
|
||||||
.*:53: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:53: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:53: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:53: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:54: Error: Number \(0xabcdef0123456789\) larger than 32 bits
|
.*:54: Error: number \(0xabcdef0123456789\) larger than 32 bits
|
||||||
.*:54: Error: Number \(0xabcdef0123450000\) larger than 32 bits
|
.*:54: Error: number \(0xabcdef0123450000\) larger than 32 bits
|
||||||
.*:55: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
|
.*:55: Error: number \(0x0*123456789abcdef\) larger than 32 bits
|
||||||
.*:55: Error: Number \(0x0*123456789ac0000\) larger than 32 bits
|
.*:55: Error: number \(0x0*123456789ac0000\) larger than 32 bits
|
||||||
.*:56: Error: Number \(0x0*1ffffffff\) larger than 32 bits
|
.*:56: Error: number \(0x0*1ffffffff\) larger than 32 bits
|
||||||
.*:56: Error: Number \(0x0*200000000\) larger than 32 bits
|
.*:56: Error: number \(0x0*200000000\) larger than 32 bits
|
||||||
.*:57: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:57: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:57: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:57: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:59: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
|
.*:59: Error: number \(0xfffffffeffffffff\) larger than 32 bits
|
||||||
.*:60: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:60: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:61: Error: Number \(0xabcdef0123456789\) larger than 32 bits
|
.*:61: Error: number \(0xabcdef0123456789\) larger than 32 bits
|
||||||
.*:62: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
|
.*:62: Error: number \(0x0*123456789abcdef\) larger than 32 bits
|
||||||
.*:63: Error: Number \(0x0*1ffffffff\) larger than 32 bits
|
.*:63: Error: number \(0x0*1ffffffff\) larger than 32 bits
|
||||||
.*:64: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:64: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
.*:66: Error: Number \(0xfffffffeffffffff\) larger than 32 bits
|
.*:66: Error: number \(0xfffffffeffffffff\) larger than 32 bits
|
||||||
.*:67: Error: Number \(0xfffffffe00000000\) larger than 32 bits
|
.*:67: Error: number \(0xfffffffe00000000\) larger than 32 bits
|
||||||
.*:68: Error: Number \(0xabcdef0123456789\) larger than 32 bits
|
.*:68: Error: number \(0xabcdef0123456789\) larger than 32 bits
|
||||||
.*:69: Error: Number \(0x0*123456789abcdef\) larger than 32 bits
|
.*:69: Error: number \(0x0*123456789abcdef\) larger than 32 bits
|
||||||
.*:70: Error: Number \(0x0*1ffffffff\) larger than 32 bits
|
.*:70: Error: number \(0x0*1ffffffff\) larger than 32 bits
|
||||||
.*:71: Error: Number \(0x0*100000000\) larger than 32 bits
|
.*:71: Error: number \(0x0*100000000\) larger than 32 bits
|
||||||
|
|||||||
@ -3,6 +3,6 @@
|
|||||||
.*\.s:6: Error: operand 2 out of range `lui \$2,65536'
|
.*\.s:6: Error: operand 2 out of range `lui \$2,65536'
|
||||||
.*\.s:7: Error: bignum invalid
|
.*\.s:7: Error: bignum invalid
|
||||||
.*\.s:8: Error: operand 2 must be an immediate expression `lui \$2,\$3'
|
.*\.s:8: Error: operand 2 must be an immediate expression `lui \$2,\$3'
|
||||||
.*\.s:9: Error: Illegal operands `lui \$2,\(\$3\)'
|
.*\.s:9: Error: invalid operands `lui \$2,\(\$3\)'
|
||||||
.*\.s:10: Error: register value used as expression `lui \$2,0\+\$3'
|
.*\.s:10: Error: register value used as expression `lui \$2,0\+\$3'
|
||||||
.*\.s:11: Error: register value used as expression `lui \$2,\(\(\$3\)\)'
|
.*\.s:11: Error: register value used as expression `lui \$2,\(\(\$3\)\)'
|
||||||
|
|||||||
@ -1,6 +1,6 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:6: Warning: Macro instruction expanded into multiple instructions
|
.*:6: Warning: macro instruction expanded into multiple instructions
|
||||||
.*:10: Warning: Macro instruction expanded into multiple instructions
|
.*:10: Warning: macro instruction expanded into multiple instructions
|
||||||
.*:12: Warning: Macro instruction expanded into multiple instructions
|
.*:12: Warning: macro instruction expanded into multiple instructions
|
||||||
.*:16: Warning: Macro instruction expanded into multiple instructions.*slot
|
.*:16: Warning: macro instruction expanded into multiple instructions.*slot
|
||||||
.*:20: Warning: Macro instruction expanded into multiple instructions.*slot
|
.*:20: Warning: macro instruction expanded into multiple instructions.*slot
|
||||||
|
|||||||
@ -1,8 +1,8 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:5: Warning: Macro instruction expanded into multiple instructions
|
.*:5: Warning: macro instruction expanded into multiple instructions
|
||||||
.*:10: Warning: Macro instruction expanded into multiple instructions
|
.*:10: Warning: macro instruction expanded into multiple instructions
|
||||||
.*:11: Warning: Macro instruction expanded into multiple instructions
|
.*:11: Warning: macro instruction expanded into multiple instructions
|
||||||
.*:12: Warning: Macro instruction expanded into multiple instructions
|
.*:12: Warning: macro instruction expanded into multiple instructions
|
||||||
.*:16: Warning: Macro instruction expanded into multiple instructions.*slot
|
.*:16: Warning: macro instruction expanded into multiple instructions.*slot
|
||||||
.*:18: Warning: Macro instruction expanded into multiple instructions.*slot
|
.*:18: Warning: macro instruction expanded into multiple instructions.*slot
|
||||||
.*:20: Warning: Macro instruction expanded into multiple instructions.*slot
|
.*:20: Warning: macro instruction expanded into multiple instructions.*slot
|
||||||
|
|||||||
@ -1,3 +1,3 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:5: Warning: Macro instruction expanded into multiple instructions
|
.*:5: Warning: macro instruction expanded into multiple instructions
|
||||||
.*:9: Warning: Macro instruction expanded into multiple instructions.*slot
|
.*:9: Warning: macro instruction expanded into multiple instructions.*slot
|
||||||
|
|||||||
@ -1,3 +1,3 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:4: Warning: Macro instruction expanded into multiple instructions
|
.*:4: Warning: macro instruction expanded into multiple instructions
|
||||||
.*:7: Warning: Macro instruction expanded into multiple instructions.*slot
|
.*:7: Warning: macro instruction expanded into multiple instructions.*slot
|
||||||
|
|||||||
@ -1,3 +1,3 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:3: Warning: Macro instruction expanded into multiple instructions
|
.*:3: Warning: macro instruction expanded into multiple instructions
|
||||||
.*:5: Warning: Macro instruction expanded into multiple instructions.*slot
|
.*:5: Warning: macro instruction expanded into multiple instructions.*slot
|
||||||
|
|||||||
@ -1,24 +1,24 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:17: Warning: Wrong size instruction in a 16-bit branch delay slot
|
.*:17: Warning: wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:19: Warning: Wrong size instruction in a 16-bit branch delay slot
|
.*:19: Warning: wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:21: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
.*:21: Warning: macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:40: Warning: Wrong size instruction in a 16-bit branch delay slot
|
.*:40: Warning: wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:44: Warning: Wrong size instruction in a 16-bit branch delay slot
|
.*:44: Warning: wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:46: Warning: Wrong size instruction in a 16-bit branch delay slot
|
.*:46: Warning: wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:71: Warning: Wrong size instruction in a 16-bit branch delay slot
|
.*:71: Warning: wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:90: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
|
.*:90: Warning: macro instruction expanded into multiple instructions in a branch delay slot
|
||||||
.*:92: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
.*:92: Warning: macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:94: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
.*:94: Warning: macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:96: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
.*:96: Warning: macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:98: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
.*:98: Warning: macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:100: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
.*:100: Warning: macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:100: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
|
.*:100: Warning: macro instruction expanded into multiple instructions in a branch delay slot
|
||||||
.*:110: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
|
.*:110: Warning: macro instruction expanded into multiple instructions in a branch delay slot
|
||||||
.*:121: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
|
.*:121: Warning: macro instruction expanded into multiple instructions in a branch delay slot
|
||||||
.*:123: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
.*:123: Warning: macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:125: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
.*:125: Warning: macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:127: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
.*:127: Warning: macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:129: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
.*:129: Warning: macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:131: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
.*:131: Warning: macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:131: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
|
.*:131: Warning: macro instruction expanded into multiple instructions in a branch delay slot
|
||||||
.*:141: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
|
.*:141: Warning: macro instruction expanded into multiple instructions in a branch delay slot
|
||||||
|
|||||||
@ -1,50 +1,50 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:61: Warning: No .cprestore pseudo-op used in PIC code
|
.*:61: Warning: no .cprestore pseudo-op used in PIC code
|
||||||
.*:59: Warning: Relaxed out-of-range branch into a jump
|
.*:59: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:63: Warning: Relaxed out-of-range branch into a jump
|
.*:63: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:65: Warning: Relaxed out-of-range branch into a jump
|
.*:65: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:67: Warning: Relaxed out-of-range branch into a jump
|
.*:67: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:69: Warning: Relaxed out-of-range branch into a jump
|
.*:69: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:71: Warning: Relaxed out-of-range branch into a jump
|
.*:71: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:73: Warning: Relaxed out-of-range branch into a jump
|
.*:73: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:75: Warning: Relaxed out-of-range branch into a jump
|
.*:75: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:77: Warning: Relaxed out-of-range branch into a jump
|
.*:77: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:79: Warning: Relaxed out-of-range branch into a jump
|
.*:79: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:81: Warning: Relaxed out-of-range branch into a jump
|
.*:81: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:83: Warning: Relaxed out-of-range branch into a jump
|
.*:83: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:85: Warning: Relaxed out-of-range branch into a jump
|
.*:85: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:87: Warning: Relaxed out-of-range branch into a jump
|
.*:87: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:89: Warning: Relaxed out-of-range branch into a jump
|
.*:89: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:91: Warning: Relaxed out-of-range branch into a jump
|
.*:91: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:93: Warning: Relaxed out-of-range branch into a jump
|
.*:93: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:95: Warning: Relaxed out-of-range branch into a jump
|
.*:95: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:97: Warning: Relaxed out-of-range branch into a jump
|
.*:97: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:99: Warning: Relaxed out-of-range branch into a jump
|
.*:99: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:101: Warning: Relaxed out-of-range branch into a jump
|
.*:101: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:103: Warning: Relaxed out-of-range branch into a jump
|
.*:103: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:105: Warning: Relaxed out-of-range branch into a jump
|
.*:105: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:107: Warning: Relaxed out-of-range branch into a jump
|
.*:107: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:109: Warning: Relaxed out-of-range branch into a jump
|
.*:109: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:111: Warning: Relaxed out-of-range branch into a jump
|
.*:111: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:113: Warning: Relaxed out-of-range branch into a jump
|
.*:113: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:115: Warning: Relaxed out-of-range branch into a jump
|
.*:115: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:117: Warning: Relaxed out-of-range branch into a jump
|
.*:117: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:119: Warning: Relaxed out-of-range branch into a jump
|
.*:119: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:121: Warning: Relaxed out-of-range branch into a jump
|
.*:121: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:123: Warning: Relaxed out-of-range branch into a jump
|
.*:123: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:125: Warning: Relaxed out-of-range branch into a jump
|
.*:125: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:127: Warning: Relaxed out-of-range branch into a jump
|
.*:127: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:129: Warning: Relaxed out-of-range branch into a jump
|
.*:129: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:131: Warning: Relaxed out-of-range branch into a jump
|
.*:131: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:133: Warning: Relaxed out-of-range branch into a jump
|
.*:133: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:135: Warning: Relaxed out-of-range branch into a jump
|
.*:135: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:137: Warning: Relaxed out-of-range branch into a jump
|
.*:137: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:139: Warning: Relaxed out-of-range branch into a jump
|
.*:139: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:141: Warning: Relaxed out-of-range branch into a jump
|
.*:141: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:143: Warning: Relaxed out-of-range branch into a jump
|
.*:143: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:145: Warning: Relaxed out-of-range branch into a jump
|
.*:145: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:147: Warning: Relaxed out-of-range branch into a jump
|
.*:147: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:149: Warning: Relaxed out-of-range branch into a jump
|
.*:149: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:151: Warning: Relaxed out-of-range branch into a jump
|
.*:151: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:153: Warning: Relaxed out-of-range branch into a jump
|
.*:153: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:155: Warning: Relaxed out-of-range branch into a jump
|
.*:155: Warning: relaxed out-of-range branch into a jump
|
||||||
|
|||||||
@ -1,48 +1,48 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:63: Warning: Relaxed out-of-range branch into a jump
|
.*:63: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:65: Warning: Relaxed out-of-range branch into a jump
|
.*:65: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:67: Warning: Relaxed out-of-range branch into a jump
|
.*:67: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:69: Warning: Relaxed out-of-range branch into a jump
|
.*:69: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:71: Warning: Relaxed out-of-range branch into a jump
|
.*:71: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:73: Warning: Relaxed out-of-range branch into a jump
|
.*:73: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:75: Warning: Relaxed out-of-range branch into a jump
|
.*:75: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:77: Warning: Relaxed out-of-range branch into a jump
|
.*:77: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:79: Warning: Relaxed out-of-range branch into a jump
|
.*:79: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:81: Warning: Relaxed out-of-range branch into a jump
|
.*:81: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:83: Warning: Relaxed out-of-range branch into a jump
|
.*:83: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:85: Warning: Relaxed out-of-range branch into a jump
|
.*:85: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:87: Warning: Relaxed out-of-range branch into a jump
|
.*:87: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:89: Warning: Relaxed out-of-range branch into a jump
|
.*:89: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:91: Warning: Relaxed out-of-range branch into a jump
|
.*:91: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:93: Warning: Relaxed out-of-range branch into a jump
|
.*:93: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:95: Warning: Relaxed out-of-range branch into a jump
|
.*:95: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:97: Warning: Relaxed out-of-range branch into a jump
|
.*:97: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:99: Warning: Relaxed out-of-range branch into a jump
|
.*:99: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:101: Warning: Relaxed out-of-range branch into a jump
|
.*:101: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:103: Warning: Relaxed out-of-range branch into a jump
|
.*:103: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:105: Warning: Relaxed out-of-range branch into a jump
|
.*:105: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:107: Warning: Relaxed out-of-range branch into a jump
|
.*:107: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:109: Warning: Relaxed out-of-range branch into a jump
|
.*:109: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:111: Warning: Relaxed out-of-range branch into a jump
|
.*:111: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:113: Warning: Relaxed out-of-range branch into a jump
|
.*:113: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:115: Warning: Relaxed out-of-range branch into a jump
|
.*:115: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:117: Warning: Relaxed out-of-range branch into a jump
|
.*:117: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:119: Warning: Relaxed out-of-range branch into a jump
|
.*:119: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:121: Warning: Relaxed out-of-range branch into a jump
|
.*:121: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:123: Warning: Relaxed out-of-range branch into a jump
|
.*:123: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:125: Warning: Relaxed out-of-range branch into a jump
|
.*:125: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:127: Warning: Relaxed out-of-range branch into a jump
|
.*:127: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:129: Warning: Relaxed out-of-range branch into a jump
|
.*:129: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:131: Warning: Relaxed out-of-range branch into a jump
|
.*:131: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:133: Warning: Relaxed out-of-range branch into a jump
|
.*:133: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:135: Warning: Relaxed out-of-range branch into a jump
|
.*:135: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:137: Warning: Relaxed out-of-range branch into a jump
|
.*:137: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:139: Warning: Relaxed out-of-range branch into a jump
|
.*:139: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:141: Warning: Relaxed out-of-range branch into a jump
|
.*:141: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:143: Warning: Relaxed out-of-range branch into a jump
|
.*:143: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:145: Warning: Relaxed out-of-range branch into a jump
|
.*:145: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:147: Warning: Relaxed out-of-range branch into a jump
|
.*:147: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:149: Warning: Relaxed out-of-range branch into a jump
|
.*:149: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:151: Warning: Relaxed out-of-range branch into a jump
|
.*:151: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:153: Warning: Relaxed out-of-range branch into a jump
|
.*:153: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:155: Warning: Relaxed out-of-range branch into a jump
|
.*:155: Warning: relaxed out-of-range branch into a jump
|
||||||
|
|||||||
@ -1,9 +1,9 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:2: Error: Invalid register range `lwm \$16-17,0\(\$4\)'
|
.*:2: Error: invalid register range `lwm \$16-17,0\(\$4\)'
|
||||||
.*:3: Error: Illegal operands `lwm \$17-\$16,0\(\$4\)'
|
.*:3: Error: invalid operands `lwm \$17-\$16,0\(\$4\)'
|
||||||
.*:4: Error: Illegal operands `lwm \$16-\$f17,0\(\$4\)'
|
.*:4: Error: invalid operands `lwm \$16-\$f17,0\(\$4\)'
|
||||||
.*:5: Error: Illegal operands `lwm \$f16-\$17,0\(\$4\)'
|
.*:5: Error: invalid operands `lwm \$f16-\$17,0\(\$4\)'
|
||||||
.*:6: Error: floating-point expression required `li\.s \$4,foo'
|
.*:6: Error: floating-point expression required `li\.s \$4,foo'
|
||||||
.*:7: Error: cannot create floating-point number
|
.*:7: Error: cannot create floating-point number
|
||||||
.*:8: Error: floating-point expression required `li\.s \$4,\$4'
|
.*:8: Error: floating-point expression required `li\.s \$4,\$4'
|
||||||
.*:9: Error: Illegal operands `li\.s 1.0'
|
.*:9: Error: invalid operands `li\.s 1.0'
|
||||||
|
|||||||
@ -1,39 +1,39 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:15: Error: Illegal operands `addu16 \$12,\$14'
|
.*:15: Error: invalid operands `addu16 \$12,\$14'
|
||||||
.*:18: Error: Unrecognized 16-bit version of microMIPS opcode `add16\.ps \$f2,\$f4'
|
.*:18: Error: unrecognized 16-bit version of microMIPS opcode `add16\.ps \$f2,\$f4'
|
||||||
.*:22: Error: Unrecognized 32-bit version of microMIPS opcode `addiusp32 256'
|
.*:22: Error: unrecognized 32-bit version of microMIPS opcode `addiusp32 256'
|
||||||
.*:25: Error: Unrecognized opcode `jar \$23'
|
.*:25: Error: unrecognized opcode `jar \$23'
|
||||||
.*:26: Error: Unrecognized opcode `jar16 \$23'
|
.*:26: Error: unrecognized opcode `jar16 \$23'
|
||||||
.*:27: Error: Unrecognized opcode `jar32 \$23'
|
.*:27: Error: unrecognized opcode `jar32 \$23'
|
||||||
.*:41: Error: Illegal operands `jalr16 \$30,\$26'
|
.*:41: Error: invalid operands `jalr16 \$30,\$26'
|
||||||
.*:50: Error: Illegal operands `beqz16 \$27,bar'
|
.*:50: Error: invalid operands `beqz16 \$27,bar'
|
||||||
.*:58: Warning: Wrong size instruction in a 32-bit branch delay slot
|
.*:58: Warning: wrong size instruction in a 32-bit branch delay slot
|
||||||
.*:66: Warning: Wrong size instruction in a 16-bit branch delay slot
|
.*:66: Warning: wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:70: Error: Unrecognized 16-bit version of microMIPS opcode `add16\.ps \$f2,\$f4'
|
.*:70: Error: unrecognized 16-bit version of microMIPS opcode `add16\.ps \$f2,\$f4'
|
||||||
.*:74: Warning: Wrong size instruction in a 16-bit branch delay slot
|
.*:74: Warning: wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:76: Error: Unrecognized 16-bit version of microMIPS opcode `add16\.ps \$f2,\$f4'
|
.*:76: Error: unrecognized 16-bit version of microMIPS opcode `add16\.ps \$f2,\$f4'
|
||||||
.*:77: Warning: Wrong size instruction in a 16-bit branch delay slot
|
.*:77: Warning: wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:78: Warning: Wrong size instruction in a 16-bit branch delay slot
|
.*:78: Warning: wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:80: Warning: Wrong size instruction in a 32-bit branch delay slot
|
.*:80: Warning: wrong size instruction in a 32-bit branch delay slot
|
||||||
.*:82: Warning: Wrong size instruction in a 32-bit branch delay slot
|
.*:82: Warning: wrong size instruction in a 32-bit branch delay slot
|
||||||
.*:84: Error: Unrecognized 32-bit version of microMIPS opcode `addiusp32 256'
|
.*:84: Error: unrecognized 32-bit version of microMIPS opcode `addiusp32 256'
|
||||||
.*:90: Error: Unrecognized 32-bit version of microMIPS opcode `addiusp32 256'
|
.*:90: Error: unrecognized 32-bit version of microMIPS opcode `addiusp32 256'
|
||||||
.*:95: Warning: Macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
.*:95: Warning: macro instruction expanded into a wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:95: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
|
.*:95: Warning: macro instruction expanded into multiple instructions in a branch delay slot
|
||||||
.*:98: Warning: Wrong size instruction in a 32-bit branch delay slot
|
.*:98: Warning: wrong size instruction in a 32-bit branch delay slot
|
||||||
.*:104: Error: Unrecognized 16-bit version of microMIPS opcode `add16\.ps \$f2,\$f4'
|
.*:104: Error: unrecognized 16-bit version of microMIPS opcode `add16\.ps \$f2,\$f4'
|
||||||
.*:105: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
|
.*:105: Warning: macro instruction expanded into multiple instructions in a branch delay slot
|
||||||
.*:108: Warning: Wrong size instruction in a 32-bit branch delay slot
|
.*:108: Warning: wrong size instruction in a 32-bit branch delay slot
|
||||||
.*:110: Warning: Wrong size instruction in a 32-bit branch delay slot
|
.*:110: Warning: wrong size instruction in a 32-bit branch delay slot
|
||||||
.*:112: Error: Unrecognized 32-bit version of microMIPS opcode `addiusp32 256'
|
.*:112: Error: unrecognized 32-bit version of microMIPS opcode `addiusp32 256'
|
||||||
.*:120: Error: operand 3 out of range `sll16 \$2,\$3,13'
|
.*:120: Error: operand 3 out of range `sll16 \$2,\$3,13'
|
||||||
.*:123: Error: Illegal operands `sll16 \$10,\$11,5'
|
.*:123: Error: invalid operands `sll16 \$10,\$11,5'
|
||||||
.*:128: Error: Unrecognized 16-bit version of microMIPS opcode `dsll16 \$2,\$3,5'
|
.*:128: Error: unrecognized 16-bit version of microMIPS opcode `dsll16 \$2,\$3,5'
|
||||||
.*:130: Error: Unrecognized 16-bit version of microMIPS opcode `dsll3216 \$2,\$3,5'
|
.*:130: Error: unrecognized 16-bit version of microMIPS opcode `dsll3216 \$2,\$3,5'
|
||||||
.*:133: Error: Unrecognized 16-bit version of microMIPS opcode `dsll16 \$2,\$3,13'
|
.*:133: Error: unrecognized 16-bit version of microMIPS opcode `dsll16 \$2,\$3,13'
|
||||||
.*:135: Error: Unrecognized 16-bit version of microMIPS opcode `dsll3216 \$2,\$3,13'
|
.*:135: Error: unrecognized 16-bit version of microMIPS opcode `dsll3216 \$2,\$3,13'
|
||||||
.*:138: Error: Unrecognized 16-bit version of microMIPS opcode `dsll16 \$10,\$11,5'
|
.*:138: Error: unrecognized 16-bit version of microMIPS opcode `dsll16 \$10,\$11,5'
|
||||||
.*:140: Error: Unrecognized 16-bit version of microMIPS opcode `dsll3216 \$10,\$11,5'
|
.*:140: Error: unrecognized 16-bit version of microMIPS opcode `dsll3216 \$10,\$11,5'
|
||||||
.*:145: Error: operand 3 out of range `addiu16 \$2,\$4,5'
|
.*:145: Error: operand 3 out of range `addiu16 \$2,\$4,5'
|
||||||
.*:146: Error: operand 3 out of range `addiu16 \$2,\$4,7'
|
.*:146: Error: operand 3 out of range `addiu16 \$2,\$4,7'
|
||||||
.*:149: Error: operand 3 out of range `andi16 \$2,\$4,5'
|
.*:149: Error: operand 3 out of range `andi16 \$2,\$4,5'
|
||||||
|
|||||||
@ -1,10 +1,10 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:50: Warning: Wrong size instruction in a 32-bit branch delay slot
|
.*:50: Warning: wrong size instruction in a 32-bit branch delay slot
|
||||||
.*:58: Warning: Wrong size instruction in a 16-bit branch delay slot
|
.*:58: Warning: wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:64: Warning: Wrong size instruction in a 16-bit branch delay slot
|
.*:64: Warning: wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:66: Warning: Wrong size instruction in a 16-bit branch delay slot
|
.*:66: Warning: wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:68: Warning: Wrong size instruction in a 32-bit branch delay slot
|
.*:68: Warning: wrong size instruction in a 32-bit branch delay slot
|
||||||
.*:70: Warning: Wrong size instruction in a 32-bit branch delay slot
|
.*:70: Warning: wrong size instruction in a 32-bit branch delay slot
|
||||||
.*:82: Warning: Wrong size instruction in a 32-bit branch delay slot
|
.*:82: Warning: wrong size instruction in a 32-bit branch delay slot
|
||||||
.*:90: Warning: Wrong size instruction in a 32-bit branch delay slot
|
.*:90: Warning: wrong size instruction in a 32-bit branch delay slot
|
||||||
.*:92: Warning: Wrong size instruction in a 32-bit branch delay slot
|
.*:92: Warning: wrong size instruction in a 32-bit branch delay slot
|
||||||
|
|||||||
@ -1,8 +1,8 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:8: Warning: Wrong size instruction in a 16-bit branch delay slot
|
.*:8: Warning: wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:10: Warning: Wrong size instruction in a 16-bit branch delay slot
|
.*:10: Warning: wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:12: Warning: Wrong size instruction in a 16-bit branch delay slot
|
.*:12: Warning: wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:14: Warning: Wrong size instruction in a 16-bit branch delay slot
|
.*:14: Warning: wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:16: Warning: Wrong size instruction in a 16-bit branch delay slot
|
.*:16: Warning: wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:18: Warning: Wrong size instruction in a 16-bit branch delay slot
|
.*:18: Warning: wrong size instruction in a 16-bit branch delay slot
|
||||||
.*:20: Warning: Wrong size instruction in a 16-bit branch delay slot
|
.*:20: Warning: wrong size instruction in a 16-bit branch delay slot
|
||||||
|
|||||||
@ -1,27 +1,27 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:578: Warning: Divide by zero.
|
.*:578: Warning: divide by zero
|
||||||
.*:581: Warning: Divide by zero.
|
.*:581: Warning: divide by zero
|
||||||
.*:594: Warning: Divide by zero.
|
.*:594: Warning: divide by zero
|
||||||
.*:1559: Warning: Divide by zero.
|
.*:1559: Warning: divide by zero
|
||||||
.*:1562: Warning: Divide by zero.
|
.*:1562: Warning: divide by zero
|
||||||
.*:1575: Warning: Divide by zero.
|
.*:1575: Warning: divide by zero
|
||||||
.*:2622: Warning: Branch bge is always true
|
.*:2622: Warning: branch bge is always true
|
||||||
.*:2625: Warning: Branch bgeu is always true
|
.*:2625: Warning: branch bgeu is always true
|
||||||
.*:2634: Warning: Branch bgeu is always true
|
.*:2634: Warning: branch bgeu is always true
|
||||||
.*:2709: Warning: Branch ble is always true
|
.*:2709: Warning: branch ble is always true
|
||||||
.*:2724: Warning: Branch bleu is always true
|
.*:2724: Warning: branch bleu is always true
|
||||||
.*:2730: Warning: Branch bleu is always true
|
.*:2730: Warning: branch bleu is always true
|
||||||
.*:2733: Warning: Branch bleu is always true
|
.*:2733: Warning: branch bleu is always true
|
||||||
.*:2832: Warning: Branch bgel is always true
|
.*:2832: Warning: branch bgel is always true
|
||||||
.*:2835: Warning: Branch bgeul is always true
|
.*:2835: Warning: branch bgeul is always true
|
||||||
.*:2844: Warning: Branch bgeul is always true
|
.*:2844: Warning: branch bgeul is always true
|
||||||
.*:2919: Warning: Branch blel is always true
|
.*:2919: Warning: branch blel is always true
|
||||||
.*:2934: Warning: Branch bleul is always true
|
.*:2934: Warning: branch bleul is always true
|
||||||
.*:2940: Warning: Branch bleul is always true
|
.*:2940: Warning: branch bleul is always true
|
||||||
.*:2943: Warning: Branch bleul is always true
|
.*:2943: Warning: branch bleul is always true
|
||||||
.*:4759: Warning: Divide by zero.
|
.*:4759: Warning: divide by zero
|
||||||
.*:4762: Warning: Divide by zero.
|
.*:4762: Warning: divide by zero
|
||||||
.*:4775: Warning: Divide by zero.
|
.*:4775: Warning: divide by zero
|
||||||
.*:5180: Warning: Divide by zero.
|
.*:5180: Warning: divide by zero
|
||||||
.*:5190: Warning: Divide by zero.
|
.*:5190: Warning: divide by zero
|
||||||
.*:5200: Warning: Divide by zero.
|
.*:5200: Warning: divide by zero
|
||||||
|
|||||||
@ -1,107 +1,107 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:39: Error: Opcode not supported in the `insn32' mode `nop16'
|
.*:39: Error: opcode not supported in the `insn32' mode `nop16'
|
||||||
.*:98: Error: Opcode not supported in the `insn32' mode `move16 \$2,\$22'
|
.*:98: Error: opcode not supported in the `insn32' mode `move16 \$2,\$22'
|
||||||
.*:99: Error: Opcode not supported in the `insn32' mode `move16 \$22,\$2'
|
.*:99: Error: opcode not supported in the `insn32' mode `move16 \$22,\$2'
|
||||||
.*:106: Error: Opcode not supported in the `insn32' mode `b16 test'
|
.*:106: Error: opcode not supported in the `insn32' mode `b16 test'
|
||||||
.*:111: Error: Opcode not supported in the `insn32' mode `b16 1f'
|
.*:111: Error: opcode not supported in the `insn32' mode `b16 1f'
|
||||||
.*:117: Error: Opcode not supported in the `insn32' mode `b16 1b'
|
.*:117: Error: opcode not supported in the `insn32' mode `b16 1b'
|
||||||
.*:277: Error: Opcode not supported in the `insn32' mode `and16 \$2,\$2,\$3'
|
.*:277: Error: opcode not supported in the `insn32' mode `and16 \$2,\$2,\$3'
|
||||||
.*:315: Error: Opcode not supported in the `insn32' mode `andi16 \$7,65535'
|
.*:315: Error: opcode not supported in the `insn32' mode `andi16 \$7,65535'
|
||||||
.*:387: Error: Opcode not supported in the `insn32' mode `beqz16 \$16,test2'
|
.*:387: Error: opcode not supported in the `insn32' mode `beqz16 \$16,test2'
|
||||||
.*:475: Error: Opcode not supported in the `insn32' mode `bnez16 \$16,test3'
|
.*:475: Error: opcode not supported in the `insn32' mode `bnez16 \$16,test3'
|
||||||
.*:578: Warning: Divide by zero.
|
.*:578: Warning: divide by zero
|
||||||
.*:581: Warning: Divide by zero.
|
.*:581: Warning: divide by zero
|
||||||
.*:594: Warning: Divide by zero.
|
.*:594: Warning: divide by zero
|
||||||
.*:1559: Warning: Divide by zero.
|
.*:1559: Warning: divide by zero
|
||||||
.*:1562: Warning: Divide by zero.
|
.*:1562: Warning: divide by zero
|
||||||
.*:1575: Warning: Divide by zero.
|
.*:1575: Warning: divide by zero
|
||||||
.*:2622: Warning: Branch bge is always true
|
.*:2622: Warning: branch bge is always true
|
||||||
.*:2625: Warning: Branch bgeu is always true
|
.*:2625: Warning: branch bgeu is always true
|
||||||
.*:2634: Warning: Branch bgeu is always true
|
.*:2634: Warning: branch bgeu is always true
|
||||||
.*:2709: Warning: Branch ble is always true
|
.*:2709: Warning: branch ble is always true
|
||||||
.*:2724: Warning: Branch bleu is always true
|
.*:2724: Warning: branch bleu is always true
|
||||||
.*:2730: Warning: Branch bleu is always true
|
.*:2730: Warning: branch bleu is always true
|
||||||
.*:2733: Warning: Branch bleu is always true
|
.*:2733: Warning: branch bleu is always true
|
||||||
.*:2832: Warning: Branch bgel is always true
|
.*:2832: Warning: branch bgel is always true
|
||||||
.*:2835: Warning: Branch bgeul is always true
|
.*:2835: Warning: branch bgeul is always true
|
||||||
.*:2844: Warning: Branch bgeul is always true
|
.*:2844: Warning: branch bgeul is always true
|
||||||
.*:2919: Warning: Branch blel is always true
|
.*:2919: Warning: branch blel is always true
|
||||||
.*:2934: Warning: Branch bleul is always true
|
.*:2934: Warning: branch bleul is always true
|
||||||
.*:2940: Warning: Branch bleul is always true
|
.*:2940: Warning: branch bleul is always true
|
||||||
.*:2943: Warning: Branch bleul is always true
|
.*:2943: Warning: branch bleul is always true
|
||||||
.*:3010: Error: Opcode not supported in the `insn32' mode `addiur1sp \$2,0'
|
.*:3010: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,0'
|
||||||
.*:3011: Error: Opcode not supported in the `insn32' mode `addiur1sp \$2,1<<2'
|
.*:3011: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,1<<2'
|
||||||
.*:3012: Error: Opcode not supported in the `insn32' mode `addiur1sp \$2,2<<2'
|
.*:3012: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,2<<2'
|
||||||
.*:3013: Error: Opcode not supported in the `insn32' mode `addiur1sp \$2,3<<2'
|
.*:3013: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,3<<2'
|
||||||
.*:3014: Error: Opcode not supported in the `insn32' mode `addiur1sp \$2,4<<2'
|
.*:3014: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,4<<2'
|
||||||
.*:3015: Error: Opcode not supported in the `insn32' mode `addiur1sp \$2,63<<2'
|
.*:3015: Error: opcode not supported in the `insn32' mode `addiur1sp \$2,63<<2'
|
||||||
.*:3016: Error: Opcode not supported in the `insn32' mode `addiur1sp \$3,63<<2'
|
.*:3016: Error: opcode not supported in the `insn32' mode `addiur1sp \$3,63<<2'
|
||||||
.*:3017: Error: Opcode not supported in the `insn32' mode `addiur1sp \$4,63<<2'
|
.*:3017: Error: opcode not supported in the `insn32' mode `addiur1sp \$4,63<<2'
|
||||||
.*:3018: Error: Opcode not supported in the `insn32' mode `addiur1sp \$5,63<<2'
|
.*:3018: Error: opcode not supported in the `insn32' mode `addiur1sp \$5,63<<2'
|
||||||
.*:3019: Error: Opcode not supported in the `insn32' mode `addiur1sp \$6,63<<2'
|
.*:3019: Error: opcode not supported in the `insn32' mode `addiur1sp \$6,63<<2'
|
||||||
.*:3020: Error: Opcode not supported in the `insn32' mode `addiur1sp \$7,63<<2'
|
.*:3020: Error: opcode not supported in the `insn32' mode `addiur1sp \$7,63<<2'
|
||||||
.*:3021: Error: Opcode not supported in the `insn32' mode `addiur1sp \$16,63<<2'
|
.*:3021: Error: opcode not supported in the `insn32' mode `addiur1sp \$16,63<<2'
|
||||||
.*:3022: Error: Opcode not supported in the `insn32' mode `addiur1sp \$17,63<<2'
|
.*:3022: Error: opcode not supported in the `insn32' mode `addiur1sp \$17,63<<2'
|
||||||
.*:3024: Error: Opcode not supported in the `insn32' mode `addiur2 \$2,\$2,-1'
|
.*:3024: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$2,-1'
|
||||||
.*:3025: Error: Opcode not supported in the `insn32' mode `addiur2 \$2,\$3,-1'
|
.*:3025: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$3,-1'
|
||||||
.*:3026: Error: Opcode not supported in the `insn32' mode `addiur2 \$2,\$4,-1'
|
.*:3026: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$4,-1'
|
||||||
.*:3027: Error: Opcode not supported in the `insn32' mode `addiur2 \$2,\$5,-1'
|
.*:3027: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$5,-1'
|
||||||
.*:3028: Error: Opcode not supported in the `insn32' mode `addiur2 \$2,\$6,-1'
|
.*:3028: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$6,-1'
|
||||||
.*:3029: Error: Opcode not supported in the `insn32' mode `addiur2 \$2,\$7,-1'
|
.*:3029: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$7,-1'
|
||||||
.*:3030: Error: Opcode not supported in the `insn32' mode `addiur2 \$2,\$16,-1'
|
.*:3030: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$16,-1'
|
||||||
.*:3031: Error: Opcode not supported in the `insn32' mode `addiur2 \$2,\$17,-1'
|
.*:3031: Error: opcode not supported in the `insn32' mode `addiur2 \$2,\$17,-1'
|
||||||
.*:3032: Error: Opcode not supported in the `insn32' mode `addiur2 \$3,\$17,-1'
|
.*:3032: Error: opcode not supported in the `insn32' mode `addiur2 \$3,\$17,-1'
|
||||||
.*:3033: Error: Opcode not supported in the `insn32' mode `addiur2 \$4,\$17,-1'
|
.*:3033: Error: opcode not supported in the `insn32' mode `addiur2 \$4,\$17,-1'
|
||||||
.*:3034: Error: Opcode not supported in the `insn32' mode `addiur2 \$5,\$17,-1'
|
.*:3034: Error: opcode not supported in the `insn32' mode `addiur2 \$5,\$17,-1'
|
||||||
.*:3035: Error: Opcode not supported in the `insn32' mode `addiur2 \$6,\$17,-1'
|
.*:3035: Error: opcode not supported in the `insn32' mode `addiur2 \$6,\$17,-1'
|
||||||
.*:3036: Error: Opcode not supported in the `insn32' mode `addiur2 \$7,\$17,-1'
|
.*:3036: Error: opcode not supported in the `insn32' mode `addiur2 \$7,\$17,-1'
|
||||||
.*:3037: Error: Opcode not supported in the `insn32' mode `addiur2 \$16,\$17,-1'
|
.*:3037: Error: opcode not supported in the `insn32' mode `addiur2 \$16,\$17,-1'
|
||||||
.*:3038: Error: Opcode not supported in the `insn32' mode `addiur2 \$17,\$17,-1'
|
.*:3038: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,-1'
|
||||||
.*:3039: Error: Opcode not supported in the `insn32' mode `addiur2 \$17,\$17,1'
|
.*:3039: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,1'
|
||||||
.*:3040: Error: Opcode not supported in the `insn32' mode `addiur2 \$17,\$17,4'
|
.*:3040: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,4'
|
||||||
.*:3041: Error: Opcode not supported in the `insn32' mode `addiur2 \$17,\$17,8'
|
.*:3041: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,8'
|
||||||
.*:3042: Error: Opcode not supported in the `insn32' mode `addiur2 \$17,\$17,12'
|
.*:3042: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,12'
|
||||||
.*:3043: Error: Opcode not supported in the `insn32' mode `addiur2 \$17,\$17,16'
|
.*:3043: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,16'
|
||||||
.*:3044: Error: Opcode not supported in the `insn32' mode `addiur2 \$17,\$17,20'
|
.*:3044: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,20'
|
||||||
.*:3045: Error: Opcode not supported in the `insn32' mode `addiur2 \$17,\$17,24'
|
.*:3045: Error: opcode not supported in the `insn32' mode `addiur2 \$17,\$17,24'
|
||||||
.*:3047: Error: Opcode not supported in the `insn32' mode `addiusp 2<<2'
|
.*:3047: Error: opcode not supported in the `insn32' mode `addiusp 2<<2'
|
||||||
.*:3048: Error: Opcode not supported in the `insn32' mode `addiusp 3<<2'
|
.*:3048: Error: opcode not supported in the `insn32' mode `addiusp 3<<2'
|
||||||
.*:3049: Error: Opcode not supported in the `insn32' mode `addiusp 254<<2'
|
.*:3049: Error: opcode not supported in the `insn32' mode `addiusp 254<<2'
|
||||||
.*:3050: Error: Opcode not supported in the `insn32' mode `addiusp 255<<2'
|
.*:3050: Error: opcode not supported in the `insn32' mode `addiusp 255<<2'
|
||||||
.*:3051: Error: Opcode not supported in the `insn32' mode `addiusp 256<<2'
|
.*:3051: Error: opcode not supported in the `insn32' mode `addiusp 256<<2'
|
||||||
.*:3052: Error: Opcode not supported in the `insn32' mode `addiusp 257<<2'
|
.*:3052: Error: opcode not supported in the `insn32' mode `addiusp 257<<2'
|
||||||
.*:3053: Error: Opcode not supported in the `insn32' mode `addiusp -3<<2'
|
.*:3053: Error: opcode not supported in the `insn32' mode `addiusp -3<<2'
|
||||||
.*:3054: Error: Opcode not supported in the `insn32' mode `addiusp -4<<2'
|
.*:3054: Error: opcode not supported in the `insn32' mode `addiusp -4<<2'
|
||||||
.*:3055: Error: Opcode not supported in the `insn32' mode `addiusp -255<<2'
|
.*:3055: Error: opcode not supported in the `insn32' mode `addiusp -255<<2'
|
||||||
.*:3056: Error: Opcode not supported in the `insn32' mode `addiusp -256<<2'
|
.*:3056: Error: opcode not supported in the `insn32' mode `addiusp -256<<2'
|
||||||
.*:3057: Error: Opcode not supported in the `insn32' mode `addiusp -257<<2'
|
.*:3057: Error: opcode not supported in the `insn32' mode `addiusp -257<<2'
|
||||||
.*:3058: Error: Opcode not supported in the `insn32' mode `addiusp -258<<2'
|
.*:3058: Error: opcode not supported in the `insn32' mode `addiusp -258<<2'
|
||||||
.*:3060: Error: Opcode not supported in the `insn32' mode `addius5 \$0,0'
|
.*:3060: Error: opcode not supported in the `insn32' mode `addius5 \$0,0'
|
||||||
.*:3061: Error: Opcode not supported in the `insn32' mode `addius5 \$2,0'
|
.*:3061: Error: opcode not supported in the `insn32' mode `addius5 \$2,0'
|
||||||
.*:3062: Error: Opcode not supported in the `insn32' mode `addius5 \$3,0'
|
.*:3062: Error: opcode not supported in the `insn32' mode `addius5 \$3,0'
|
||||||
.*:3063: Error: Opcode not supported in the `insn32' mode `addius5 \$30,0'
|
.*:3063: Error: opcode not supported in the `insn32' mode `addius5 \$30,0'
|
||||||
.*:3064: Error: Opcode not supported in the `insn32' mode `addius5 \$31,0'
|
.*:3064: Error: opcode not supported in the `insn32' mode `addius5 \$31,0'
|
||||||
.*:3065: Error: Opcode not supported in the `insn32' mode `addius5 \$31,1'
|
.*:3065: Error: opcode not supported in the `insn32' mode `addius5 \$31,1'
|
||||||
.*:3066: Error: Opcode not supported in the `insn32' mode `addius5 \$31,2'
|
.*:3066: Error: opcode not supported in the `insn32' mode `addius5 \$31,2'
|
||||||
.*:3067: Error: Opcode not supported in the `insn32' mode `addius5 \$31,3'
|
.*:3067: Error: opcode not supported in the `insn32' mode `addius5 \$31,3'
|
||||||
.*:3068: Error: Opcode not supported in the `insn32' mode `addius5 \$31,7'
|
.*:3068: Error: opcode not supported in the `insn32' mode `addius5 \$31,7'
|
||||||
.*:3069: Error: Opcode not supported in the `insn32' mode `addius5 \$31,-6'
|
.*:3069: Error: opcode not supported in the `insn32' mode `addius5 \$31,-6'
|
||||||
.*:3070: Error: Opcode not supported in the `insn32' mode `addius5 \$31,-7'
|
.*:3070: Error: opcode not supported in the `insn32' mode `addius5 \$31,-7'
|
||||||
.*:3071: Error: Opcode not supported in the `insn32' mode `addius5 \$31,-8'
|
.*:3071: Error: opcode not supported in the `insn32' mode `addius5 \$31,-8'
|
||||||
.*:4759: Warning: Divide by zero.
|
.*:4759: Warning: divide by zero
|
||||||
.*:4762: Warning: Divide by zero.
|
.*:4762: Warning: divide by zero
|
||||||
.*:4775: Warning: Divide by zero.
|
.*:4775: Warning: divide by zero
|
||||||
.*:5180: Warning: Divide by zero.
|
.*:5180: Warning: divide by zero
|
||||||
.*:5190: Warning: Divide by zero.
|
.*:5190: Warning: divide by zero
|
||||||
.*:5200: Warning: Divide by zero.
|
.*:5200: Warning: divide by zero
|
||||||
.*:5568: Error: Opcode not supported in the `insn32' mode `jalr16 \$2'
|
.*:5568: Error: opcode not supported in the `insn32' mode `jalr16 \$2'
|
||||||
.*:5572: Error: Opcode not supported in the `insn32' mode `jr16 \$2'
|
.*:5572: Error: opcode not supported in the `insn32' mode `jr16 \$2'
|
||||||
.*:5579: Error: Opcode not supported in the `insn32' mode `jals test_delay_slot'
|
.*:5579: Error: opcode not supported in the `insn32' mode `jals test_delay_slot'
|
||||||
.*:5580: Error: Opcode not supported in the `insn32' mode `jalrs16 \$2'
|
.*:5580: Error: opcode not supported in the `insn32' mode `jalrs16 \$2'
|
||||||
.*:5581: Error: Opcode not supported in the `insn32' mode `jalrs32 \$2'
|
.*:5581: Error: opcode not supported in the `insn32' mode `jalrs32 \$2'
|
||||||
.*:5582: Error: Opcode not supported in the `insn32' mode `jrs \$2'
|
.*:5582: Error: opcode not supported in the `insn32' mode `jrs \$2'
|
||||||
.*:5583: Error: Opcode not supported in the `insn32' mode `jalrs\.hb \$2'
|
.*:5583: Error: opcode not supported in the `insn32' mode `jalrs\.hb \$2'
|
||||||
.*:5584: Error: Opcode not supported in the `insn32' mode `jrs\.hb \$2'
|
.*:5584: Error: opcode not supported in the `insn32' mode `jrs\.hb \$2'
|
||||||
.*:5665: Error: Opcode not supported in the `insn32' mode `bals test_spec107'
|
.*:5665: Error: opcode not supported in the `insn32' mode `bals test_spec107'
|
||||||
.*:5667: Error: Opcode not supported in the `insn32' mode `bgezals \$2,test_spec107'
|
.*:5667: Error: opcode not supported in the `insn32' mode `bgezals \$2,test_spec107'
|
||||||
.*:5669: Error: Opcode not supported in the `insn32' mode `bltzals \$2,test_spec107'
|
.*:5669: Error: opcode not supported in the `insn32' mode `bltzals \$2,test_spec107'
|
||||||
|
|||||||
@ -1,3 +1,3 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:8: Error: Opcode not supported on this processor: .* \(.*\) `add.d \$f2,\$f2,\$f2'
|
.*:8: Error: opcode not supported on this processor: .* \(.*\) `add.d \$f2,\$f2,\$f2'
|
||||||
.*:17: Error: Opcode not supported on this processor: .* \(.*\) `add.d \$f2,\$f2,\$f2'
|
.*:17: Error: opcode not supported on this processor: .* \(.*\) `add.d \$f2,\$f2,\$f2'
|
||||||
|
|||||||
@ -1,5 +1,5 @@
|
|||||||
Assembler messages:
|
Assembler messages:
|
||||||
Warning: -mfp32 used with a 64-bit ABI
|
Warning: -mfp32 used with a 64-bit ABI
|
||||||
.*:92: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
|
.*:92: Warning: macro instruction expanded into multiple instructions in a branch delay slot
|
||||||
.*:96: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
|
.*:96: Warning: macro instruction expanded into multiple instructions in a branch delay slot
|
||||||
.*:100: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
|
.*:100: Warning: macro instruction expanded into multiple instructions in a branch delay slot
|
||||||
|
|||||||
@ -1,4 +1,4 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:92: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
|
.*:92: Warning: macro instruction expanded into multiple instructions in a branch delay slot
|
||||||
.*:96: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
|
.*:96: Warning: macro instruction expanded into multiple instructions in a branch delay slot
|
||||||
.*:100: Warning: Macro instruction expanded into multiple instructions in a branch delay slot
|
.*:100: Warning: macro instruction expanded into multiple instructions in a branch delay slot
|
||||||
|
|||||||
@ -1,5 +1,5 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:7: Error: Opcode not supported on this processor: .* \(.*\) `add.s \$f2,\$f2,\$f2'
|
.*:7: Error: opcode not supported on this processor: .* \(.*\) `add.s \$f2,\$f2,\$f2'
|
||||||
.*:8: Error: Opcode not supported on this processor: .* \(.*\) `add.d \$f2,\$f2,\$f2'
|
.*:8: Error: opcode not supported on this processor: .* \(.*\) `add.d \$f2,\$f2,\$f2'
|
||||||
.*:16: Error: Opcode not supported on this processor: .* \(.*\) `add.s \$f2,\$f2,\$f2'
|
.*:16: Error: opcode not supported on this processor: .* \(.*\) `add.s \$f2,\$f2,\$f2'
|
||||||
.*:17: Error: Opcode not supported on this processor: .* \(.*\) `add.d \$f2,\$f2,\$f2'
|
.*:17: Error: opcode not supported on this processor: .* \(.*\) `add.d \$f2,\$f2,\$f2'
|
||||||
|
|||||||
@ -1,19 +1,19 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:5: Error: Opcode not supported on this processor: .* \(.*\) `ldc1 \$f2,d'
|
.*:5: Error: opcode not supported on this processor: .* \(.*\) `ldc1 \$f2,d'
|
||||||
.*:6: Error: Opcode not supported on this processor: .* \(.*\) `ldc1 \$22,d'
|
.*:6: Error: opcode not supported on this processor: .* \(.*\) `ldc1 \$22,d'
|
||||||
.*:7: Error: Opcode not supported on this processor: .* \(.*\) `l.d \$f2,d'
|
.*:7: Error: opcode not supported on this processor: .* \(.*\) `l.d \$f2,d'
|
||||||
.*:8: Error: Opcode not supported on this processor: .* \(.*\) `li.d \$f2,1.2'
|
.*:8: Error: opcode not supported on this processor: .* \(.*\) `li.d \$f2,1.2'
|
||||||
.*:9: Error: Opcode not supported on this processor: .* \(.*\) `li.d \$22,1.2'
|
.*:9: Error: opcode not supported on this processor: .* \(.*\) `li.d \$22,1.2'
|
||||||
.*:11: Error: Opcode not supported on this processor: .* \(.*\) `sdc1 \$f2,d'
|
.*:11: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$f2,d'
|
||||||
.*:12: Error: Opcode not supported on this processor: .* \(.*\) `sdc1 \$22,d'
|
.*:12: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$22,d'
|
||||||
.*:13: Error: Opcode not supported on this processor: .* \(.*\) `s.d \$f2,d'
|
.*:13: Error: opcode not supported on this processor: .* \(.*\) `s.d \$f2,d'
|
||||||
.*:15: Error: Opcode not supported on this processor: .* \(.*\) `trunc.w.d \$f4,\$f6,\$4'
|
.*:15: Error: opcode not supported on this processor: .* \(.*\) `trunc.w.d \$f4,\$f6,\$4'
|
||||||
.*:18: Error: Opcode not supported on this processor: .* \(.*\) `lwc1 \$f2,d'
|
.*:18: Error: opcode not supported on this processor: .* \(.*\) `lwc1 \$f2,d'
|
||||||
.*:19: Error: Opcode not supported on this processor: .* \(.*\) `lwc1 \$22,d'
|
.*:19: Error: opcode not supported on this processor: .* \(.*\) `lwc1 \$22,d'
|
||||||
.*:20: Error: Opcode not supported on this processor: .* \(.*\) `l.s \$f2,d'
|
.*:20: Error: opcode not supported on this processor: .* \(.*\) `l.s \$f2,d'
|
||||||
.*:21: Error: Opcode not supported on this processor: .* \(.*\) `li.s \$f2,1.2'
|
.*:21: Error: opcode not supported on this processor: .* \(.*\) `li.s \$f2,1.2'
|
||||||
.*:22: Error: Opcode not supported on this processor: .* \(.*\) `li.s \$22,1.2'
|
.*:22: Error: opcode not supported on this processor: .* \(.*\) `li.s \$22,1.2'
|
||||||
.*:24: Error: Opcode not supported on this processor: .* \(.*\) `sdc1 \$f2,d'
|
.*:24: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$f2,d'
|
||||||
.*:25: Error: Opcode not supported on this processor: .* \(.*\) `sdc1 \$22,d'
|
.*:25: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$22,d'
|
||||||
.*:26: Error: Opcode not supported on this processor: .* \(.*\) `s.d \$f2,d'
|
.*:26: Error: opcode not supported on this processor: .* \(.*\) `s.d \$f2,d'
|
||||||
.*:28: Error: Opcode not supported on this processor: .* \(.*\) `trunc.w.s \$f4,\$f6,\$4'
|
.*:28: Error: opcode not supported on this processor: .* \(.*\) `trunc.w.s \$f4,\$f6,\$4'
|
||||||
|
|||||||
@ -1,10 +1,10 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:5: Error: Opcode not supported on this processor: .* \(.*\) `ldc1 \$f2,d'
|
.*:5: Error: opcode not supported on this processor: .* \(.*\) `ldc1 \$f2,d'
|
||||||
.*:6: Error: Opcode not supported on this processor: .* \(.*\) `ldc1 \$22,d'
|
.*:6: Error: opcode not supported on this processor: .* \(.*\) `ldc1 \$22,d'
|
||||||
.*:7: Error: Opcode not supported on this processor: .* \(.*\) `l.d \$f2,d'
|
.*:7: Error: opcode not supported on this processor: .* \(.*\) `l.d \$f2,d'
|
||||||
.*:8: Error: Opcode not supported on this processor: .* \(.*\) `li.d \$f2,1.2'
|
.*:8: Error: opcode not supported on this processor: .* \(.*\) `li.d \$f2,1.2'
|
||||||
.*:9: Error: Opcode not supported on this processor: .* \(.*\) `li.d \$22,1.2'
|
.*:9: Error: opcode not supported on this processor: .* \(.*\) `li.d \$22,1.2'
|
||||||
.*:11: Error: Opcode not supported on this processor: .* \(.*\) `sdc1 \$f2,d'
|
.*:11: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$f2,d'
|
||||||
.*:12: Error: Opcode not supported on this processor: .* \(.*\) `sdc1 \$22,d'
|
.*:12: Error: opcode not supported on this processor: .* \(.*\) `sdc1 \$22,d'
|
||||||
.*:13: Error: Opcode not supported on this processor: .* \(.*\) `s.d \$f2,d'
|
.*:13: Error: opcode not supported on this processor: .* \(.*\) `s.d \$f2,d'
|
||||||
.*:15: Error: Opcode not supported on this processor: .* \(.*\) `trunc.w.d \$f4,\$f6,\$4'
|
.*:15: Error: opcode not supported on this processor: .* \(.*\) `trunc.w.d \$f4,\$f6,\$4'
|
||||||
|
|||||||
@ -1,3 +1,3 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:6: Error: Opcode not supported on this processor: .* \(.*\) `add.s \$f0,\$f2,\$f4'
|
.*:6: Error: opcode not supported on this processor: .* \(.*\) `add.s \$f0,\$f2,\$f4'
|
||||||
.*:7: Error: Opcode not supported on this processor: .* \(.*\) `cfc1 \$2,\$0'
|
.*:7: Error: opcode not supported on this processor: .* \(.*\) `cfc1 \$2,\$0'
|
||||||
|
|||||||
@ -1,3 +1,3 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*: Error: Opcode not supported on this processor: .* (.*) `sew \$4'
|
.*: Error: opcode not supported on this processor: .* (.*) `sew \$4'
|
||||||
.*: Error: Opcode not supported on this processor: .* (.*) `zew \$4'
|
.*: Error: opcode not supported on this processor: .* (.*) `zew \$4'
|
||||||
|
|||||||
@ -1,5 +1,5 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:2: Error: Illegal operands `save \$3,100'
|
.*:2: Error: invalid operands `save \$3,100'
|
||||||
.*:3: Error: missing frame size `save \$4'
|
.*:3: Error: missing frame size `save \$4'
|
||||||
.*:4: Error: frame size specified twice `save \$4,100,200'
|
.*:4: Error: frame size specified twice `save \$4,100,200'
|
||||||
.*:5: Error: operand 2 must be constant `save \$4,foo'
|
.*:5: Error: operand 2 must be constant `save \$4,foo'
|
||||||
@ -8,6 +8,6 @@
|
|||||||
.*:10: Error: invalid frame size `save \$4,12'
|
.*:10: Error: invalid frame size `save \$4,12'
|
||||||
.*:11: Error: invalid frame size `save \$4,2048'
|
.*:11: Error: invalid frame size `save \$4,2048'
|
||||||
.*:12: Error: invalid frame size `save \$4,2052'
|
.*:12: Error: invalid frame size `save \$4,2052'
|
||||||
.*:14: Error: Illegal operands `save \$4,\$6,0'
|
.*:14: Error: invalid operands `save \$4,\$6,0'
|
||||||
.*:15: Error: Illegal operands `save 0,\$5,\$7'
|
.*:15: Error: invalid operands `save 0,\$5,\$7'
|
||||||
.*:18: Error: Illegal operands `save \$16,\$18,\$20,0'
|
.*:18: Error: invalid operands `save \$16,\$18,\$20,0'
|
||||||
|
|||||||
@ -1,8 +1,8 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:5: Error: Opcode not supported on this processor: .* \(.*\) `li.s \$f1,1.0'
|
.*:5: Error: opcode not supported on this processor: .* \(.*\) `li.s \$f1,1.0'
|
||||||
.*:6: Error: Opcode not supported on this processor: .* \(.*\) `li.s \$f3,1.9'
|
.*:6: Error: opcode not supported on this processor: .* \(.*\) `li.s \$f3,1.9'
|
||||||
.*:7: Error: Opcode not supported on this processor: .* \(.*\) `add.s \$f5,\$f1,\$f3'
|
.*:7: Error: opcode not supported on this processor: .* \(.*\) `add.s \$f5,\$f1,\$f3'
|
||||||
.*:8: Error: Opcode not supported on this processor: .* \(.*\) `cvt.d.s \$f8,\$f7'
|
.*:8: Error: opcode not supported on this processor: .* \(.*\) `cvt.d.s \$f8,\$f7'
|
||||||
.*:9: Error: Opcode not supported on this processor: .* \(.*\) `cvt.d.w \$f8,\$f7'
|
.*:9: Error: opcode not supported on this processor: .* \(.*\) `cvt.d.w \$f8,\$f7'
|
||||||
.*:10: Error: Opcode not supported on this processor: .* \(.*\) `cvt.s.d \$f7,\$f8'
|
.*:10: Error: opcode not supported on this processor: .* \(.*\) `cvt.s.d \$f7,\$f8'
|
||||||
.*:11: Error: Opcode not supported on this processor: .* \(.*\) `trunc.w.d \$f7,\$f8'
|
.*:11: Error: opcode not supported on this processor: .* \(.*\) `trunc.w.d \$f7,\$f8'
|
||||||
|
|||||||
@ -1,3 +1,3 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:12: Error: Opcode not supported on this processor: .* \(.*\) `mfhc1 \$17,\$f0'
|
.*:12: Error: opcode not supported on this processor: .* \(.*\) `mfhc1 \$17,\$f0'
|
||||||
.*:13: Error: Opcode not supported on this processor: .* \(.*\) `mthc1 \$17,\$f0'
|
.*:13: Error: opcode not supported on this processor: .* \(.*\) `mthc1 \$17,\$f0'
|
||||||
|
|||||||
@ -11,5 +11,5 @@
|
|||||||
.*:39: Error: operand 4 out of range `ins \$4,\$5,0,33'
|
.*:39: Error: operand 4 out of range `ins \$4,\$5,0,33'
|
||||||
.*:42: Error: operand 4 out of range `ins \$4,\$5,0,0'
|
.*:42: Error: operand 4 out of range `ins \$4,\$5,0,0'
|
||||||
.*:45: Error: operand 4 out of range `ins \$4,\$5,31,2'
|
.*:45: Error: operand 4 out of range `ins \$4,\$5,31,2'
|
||||||
.*:54: Warning: Float register should be even, was 1
|
.*:54: Warning: float register should be even, was 1
|
||||||
.*:57: Warning: Float register should be even, was 1
|
.*:57: Warning: float register should be even, was 1
|
||||||
|
|||||||
@ -1,3 +1,3 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:5: Error: Opcode not supported on this processor: .* \(.*\) `bc1fl \$fcc1,text_label'
|
.*:5: Error: opcode not supported on this processor: .* \(.*\) `bc1fl \$fcc1,text_label'
|
||||||
.*:6: Error: Opcode not supported on this processor: .* \(.*\) `bc1tl \$fcc2,text_label'
|
.*:6: Error: opcode not supported on this processor: .* \(.*\) `bc1tl \$fcc2,text_label'
|
||||||
|
|||||||
@ -1,33 +1,33 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:4: Error: Opcode not supported on this processor: .* \(.*\) `bc1f text_label'
|
.*:4: Error: opcode not supported on this processor: .* \(.*\) `bc1f text_label'
|
||||||
.*:5: Error: Opcode not supported on this processor: .* \(.*\) `bc1f \$fcc1,text_label'
|
.*:5: Error: opcode not supported on this processor: .* \(.*\) `bc1f \$fcc1,text_label'
|
||||||
.*:6: Error: Opcode not supported on this processor: .* \(.*\) `bc1t \$fcc1,text_label'
|
.*:6: Error: opcode not supported on this processor: .* \(.*\) `bc1t \$fcc1,text_label'
|
||||||
.*:7: Error: Opcode not supported on this processor: .* \(.*\) `c.f.d \$f4,\$f6'
|
.*:7: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$f4,\$f6'
|
||||||
.*:8: Error: Opcode not supported on this processor: .* \(.*\) `c.f.d \$fcc1,\$f4,\$f6'
|
.*:8: Error: opcode not supported on this processor: .* \(.*\) `c.f.d \$fcc1,\$f4,\$f6'
|
||||||
.*:9: Error: Opcode not supported on this processor: .* \(.*\) `ldxc1 \$f2,\$4\(\$5\)'
|
.*:9: Error: opcode not supported on this processor: .* \(.*\) `ldxc1 \$f2,\$4\(\$5\)'
|
||||||
.*:10: Error: Opcode not supported on this processor: .* \(.*\) `lwxc1 \$f2,\$4\(\$5\)'
|
.*:10: Error: opcode not supported on this processor: .* \(.*\) `lwxc1 \$f2,\$4\(\$5\)'
|
||||||
.*:11: Error: Opcode not supported on this processor: .* \(.*\) `madd.d \$f0,\$f2,\$f4,\$f6'
|
.*:11: Error: opcode not supported on this processor: .* \(.*\) `madd.d \$f0,\$f2,\$f4,\$f6'
|
||||||
.*:13: Error: Opcode not supported on this processor: .* \(.*\) `madd.s \$f10,\$f8,\$f2,\$f0'
|
.*:13: Error: opcode not supported on this processor: .* \(.*\) `madd.s \$f10,\$f8,\$f2,\$f0'
|
||||||
.*:14: Error: Opcode not supported on this processor: .* \(.*\) `movf \$4,\$5,\$fcc4'
|
.*:14: Error: opcode not supported on this processor: .* \(.*\) `movf \$4,\$5,\$fcc4'
|
||||||
.*:15: Error: Opcode not supported on this processor: .* \(.*\) `movf.d \$f4,\$f6,\$fcc0'
|
.*:15: Error: opcode not supported on this processor: .* \(.*\) `movf.d \$f4,\$f6,\$fcc0'
|
||||||
.*:16: Error: Opcode not supported on this processor: .* \(.*\) `movf.s \$f4,\$f6,\$fcc0'
|
.*:16: Error: opcode not supported on this processor: .* \(.*\) `movf.s \$f4,\$f6,\$fcc0'
|
||||||
.*:17: Error: Opcode not supported on this processor: .* \(.*\) `movn.d \$f4,\$f6,\$6'
|
.*:17: Error: opcode not supported on this processor: .* \(.*\) `movn.d \$f4,\$f6,\$6'
|
||||||
.*:18: Error: Opcode not supported on this processor: .* \(.*\) `movn.s \$f4,\$f6,\$6'
|
.*:18: Error: opcode not supported on this processor: .* \(.*\) `movn.s \$f4,\$f6,\$6'
|
||||||
.*:19: Error: Opcode not supported on this processor: .* \(.*\) `movt \$4,\$5,\$fcc4'
|
.*:19: Error: opcode not supported on this processor: .* \(.*\) `movt \$4,\$5,\$fcc4'
|
||||||
.*:20: Error: Opcode not supported on this processor: .* \(.*\) `movt.d \$f4,\$f6,\$fcc0'
|
.*:20: Error: opcode not supported on this processor: .* \(.*\) `movt.d \$f4,\$f6,\$fcc0'
|
||||||
.*:21: Error: Opcode not supported on this processor: .* \(.*\) `movt.s \$f4,\$f6,\$fcc0'
|
.*:21: Error: opcode not supported on this processor: .* \(.*\) `movt.s \$f4,\$f6,\$fcc0'
|
||||||
.*:22: Error: Opcode not supported on this processor: .* \(.*\) `movz.d \$f4,\$f6,\$6'
|
.*:22: Error: opcode not supported on this processor: .* \(.*\) `movz.d \$f4,\$f6,\$6'
|
||||||
.*:23: Error: Opcode not supported on this processor: .* \(.*\) `movz.s \$f4,\$f6,\$6'
|
.*:23: Error: opcode not supported on this processor: .* \(.*\) `movz.s \$f4,\$f6,\$6'
|
||||||
.*:24: Error: Opcode not supported on this processor: .* \(.*\) `msub.d \$f0,\$f2,\$f4,\$f6'
|
.*:24: Error: opcode not supported on this processor: .* \(.*\) `msub.d \$f0,\$f2,\$f4,\$f6'
|
||||||
.*:25: Error: Opcode not supported on this processor: .* \(.*\) `msub.s \$f0,\$f2,\$f4,\$f6'
|
.*:25: Error: opcode not supported on this processor: .* \(.*\) `msub.s \$f0,\$f2,\$f4,\$f6'
|
||||||
.*:26: Error: Opcode not supported on this processor: .* \(.*\) `nmadd.d \$f0,\$f2,\$f4,\$f6'
|
.*:26: Error: opcode not supported on this processor: .* \(.*\) `nmadd.d \$f0,\$f2,\$f4,\$f6'
|
||||||
.*:27: Error: Opcode not supported on this processor: .* \(.*\) `nmadd.s \$f0,\$f2,\$f4,\$f6'
|
.*:27: Error: opcode not supported on this processor: .* \(.*\) `nmadd.s \$f0,\$f2,\$f4,\$f6'
|
||||||
.*:28: Error: Opcode not supported on this processor: .* \(.*\) `nmsub.d \$f0,\$f2,\$f4,\$f6'
|
.*:28: Error: opcode not supported on this processor: .* \(.*\) `nmsub.d \$f0,\$f2,\$f4,\$f6'
|
||||||
.*:29: Error: Opcode not supported on this processor: .* \(.*\) `nmsub.s \$f0,\$f2,\$f4,\$f6'
|
.*:29: Error: opcode not supported on this processor: .* \(.*\) `nmsub.s \$f0,\$f2,\$f4,\$f6'
|
||||||
.*:31: Error: Opcode not supported on this processor: .* \(.*\) `prefx 4,\$4\(\$5\)'
|
.*:31: Error: opcode not supported on this processor: .* \(.*\) `prefx 4,\$4\(\$5\)'
|
||||||
.*:32: Error: Opcode not supported on this processor: .* \(.*\) `recip.d \$f4,\$f6'
|
.*:32: Error: opcode not supported on this processor: .* \(.*\) `recip.d \$f4,\$f6'
|
||||||
.*:33: Error: Opcode not supported on this processor: .* \(.*\) `recip.s \$f4,\$f6'
|
.*:33: Error: opcode not supported on this processor: .* \(.*\) `recip.s \$f4,\$f6'
|
||||||
.*:34: Error: Opcode not supported on this processor: .* \(.*\) `rsqrt.d \$f4,\$f6'
|
.*:34: Error: opcode not supported on this processor: .* \(.*\) `rsqrt.d \$f4,\$f6'
|
||||||
.*:35: Error: Opcode not supported on this processor: .* \(.*\) `rsqrt.s \$f4,\$f6'
|
.*:35: Error: opcode not supported on this processor: .* \(.*\) `rsqrt.s \$f4,\$f6'
|
||||||
.*:36: Error: Opcode not supported on this processor: .* \(.*\) `sdxc1 \$f4,\$4\(\$5\)'
|
.*:36: Error: opcode not supported on this processor: .* \(.*\) `sdxc1 \$f4,\$4\(\$5\)'
|
||||||
.*:37: Error: Opcode not supported on this processor: .* \(.*\) `swxc1 \$f4,\$4\(\$5\)'
|
.*:37: Error: opcode not supported on this processor: .* \(.*\) `swxc1 \$f4,\$4\(\$5\)'
|
||||||
|
|||||||
@ -1,3 +1,3 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:61: Warning: Condition code register should be even for c.eq.ps, was 3
|
.*:61: Warning: condition code register should be even for c.eq.ps, was 3
|
||||||
.*:62: Warning: Condition code register should be even for movf.ps, was 3
|
.*:62: Warning: condition code register should be even for movf.ps, was 3
|
||||||
|
|||||||
@ -1,5 +1,5 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:150: Warning: Condition code register should be even for bc1any2f, was 1
|
.*:150: Warning: condition code register should be even for bc1any2f, was 1
|
||||||
.*:152: Warning: Condition code register should be even for bc1any2t, was 3
|
.*:152: Warning: condition code register should be even for bc1any2t, was 3
|
||||||
.*:154: Warning: Condition code register should be 0 or 4 for bc1any4f, was 1
|
.*:154: Warning: condition code register should be 0 or 4 for bc1any4f, was 1
|
||||||
.*:156: Warning: Condition code register should be 0 or 4 for bc1any4t, was 2
|
.*:156: Warning: condition code register should be 0 or 4 for bc1any4t, was 2
|
||||||
|
|||||||
@ -1,2 +1,2 @@
|
|||||||
.*\.s: Assembler messages:
|
.*\.s: Assembler messages:
|
||||||
.*\.s:1: Error: Bad .nan directive
|
.*\.s:1: Error: bad .nan directive
|
||||||
|
|||||||
@ -1,2 +1,2 @@
|
|||||||
Assembler messages:
|
Assembler messages:
|
||||||
Fatal error: Invalid NaN setting -mnan=foo
|
Fatal error: invalid NaN setting -mnan=foo
|
||||||
|
|||||||
@ -1,2 +1,2 @@
|
|||||||
.*\.s: Assembler messages:
|
.*\.s: Assembler messages:
|
||||||
.*\.s:2: Error: Macro used \$at after "\.set noat"
|
.*\.s:2: Error: macro used \$at after "\.set noat"
|
||||||
|
|||||||
@ -1,2 +1,2 @@
|
|||||||
.*\.s: Assembler messages:
|
.*\.s: Assembler messages:
|
||||||
.*\.s:2: Error: Macro used \$at after "\.set noat"
|
.*\.s:2: Error: macro used \$at after "\.set noat"
|
||||||
|
|||||||
@ -1,2 +1,2 @@
|
|||||||
.*\.s: Assembler messages:
|
.*\.s: Assembler messages:
|
||||||
.*\.s:2: Error: Macro used \$at after "\.set noat"
|
.*\.s:2: Error: macro used \$at after "\.set noat"
|
||||||
|
|||||||
@ -1,2 +1,2 @@
|
|||||||
.*\.s: Assembler messages:
|
.*\.s: Assembler messages:
|
||||||
.*\.s:2: Error: Macro used \$at after "\.set noat"
|
.*\.s:2: Error: macro used \$at after "\.set noat"
|
||||||
|
|||||||
@ -1,2 +1,2 @@
|
|||||||
.*\.s: Assembler messages:
|
.*\.s: Assembler messages:
|
||||||
.*\.s:2: Error: Macro used \$at after "\.set noat"
|
.*\.s:2: Error: macro used \$at after "\.set noat"
|
||||||
|
|||||||
@ -1,2 +1,2 @@
|
|||||||
.*\.s: Assembler messages:
|
.*\.s: Assembler messages:
|
||||||
.*\.s:2: Error: Macro used \$at after "\.set noat"
|
.*\.s:2: Error: macro used \$at after "\.set noat"
|
||||||
|
|||||||
@ -8,26 +8,26 @@
|
|||||||
.*:18: Error: operand 4 out of range `cins32 \$17,\$20,7,25'
|
.*:18: Error: operand 4 out of range `cins32 \$17,\$20,7,25'
|
||||||
.*:20: Error: operand 3 out of range `cins \$24,\$10,64,8'
|
.*:20: Error: operand 3 out of range `cins \$24,\$10,64,8'
|
||||||
.*:21: Error: operand 4 out of range `cins \$21,\$30,50,14'
|
.*:21: Error: operand 4 out of range `cins \$21,\$30,50,14'
|
||||||
.*:23: Error: Opcode not supported on this processor.*
|
.*:23: Error: opcode not supported on this processor.*
|
||||||
.*:24: Error: Opcode not supported on this processor.*
|
.*:24: Error: opcode not supported on this processor.*
|
||||||
.*:25: Error: Opcode not supported on this processor.*
|
.*:25: Error: opcode not supported on this processor.*
|
||||||
.*:26: Error: Opcode not supported on this processor.*
|
.*:26: Error: opcode not supported on this processor.*
|
||||||
.*:27: Error: Opcode not supported on this processor.*
|
.*:27: Error: opcode not supported on this processor.*
|
||||||
.*:28: Error: Opcode not supported on this processor.*
|
.*:28: Error: opcode not supported on this processor.*
|
||||||
.*:29: Error: Opcode not supported on this processor.*
|
.*:29: Error: opcode not supported on this processor.*
|
||||||
.*:30: Error: Opcode not supported on this processor.*
|
.*:30: Error: opcode not supported on this processor.*
|
||||||
.*:31: Error: Opcode not supported on this processor.*
|
.*:31: Error: opcode not supported on this processor.*
|
||||||
.*:32: Error: Opcode not supported on this processor.*
|
.*:32: Error: opcode not supported on this processor.*
|
||||||
.*:33: Error: Opcode not supported on this processor.*
|
.*:33: Error: opcode not supported on this processor.*
|
||||||
.*:34: Error: Opcode not supported on this processor.*
|
.*:34: Error: opcode not supported on this processor.*
|
||||||
.*:35: Error: Opcode not supported on this processor.*
|
.*:35: Error: opcode not supported on this processor.*
|
||||||
.*:36: Error: Opcode not supported on this processor.*
|
.*:36: Error: opcode not supported on this processor.*
|
||||||
.*:37: Error: Opcode not supported on this processor.*
|
.*:37: Error: opcode not supported on this processor.*
|
||||||
.*:39: Error: Opcode not supported on this processor.*
|
.*:39: Error: opcode not supported on this processor.*
|
||||||
.*:40: Error: Opcode not supported on this processor.*
|
.*:40: Error: opcode not supported on this processor.*
|
||||||
.*:41: Error: Opcode not supported on this processor.*
|
.*:41: Error: opcode not supported on this processor.*
|
||||||
.*:42: Error: Opcode not supported on this processor.*
|
.*:42: Error: opcode not supported on this processor.*
|
||||||
.*:43: Error: Opcode not supported on this processor.*
|
.*:43: Error: opcode not supported on this processor.*
|
||||||
.*:45: Error: operand 2 out of range `dmfc2 \$2,0x10000'
|
.*:45: Error: operand 2 out of range `dmfc2 \$2,0x10000'
|
||||||
.*:46: Error: operand 2 out of range `dmtc2 \$2,0x12345'
|
.*:46: Error: operand 2 out of range `dmtc2 \$2,0x12345'
|
||||||
.*:47: Error: operand 2 must be an immediate expression `dmfc2 \$9,\$12'
|
.*:47: Error: operand 2 must be an immediate expression `dmfc2 \$9,\$12'
|
||||||
|
|||||||
File diff suppressed because it is too large
Load Diff
@ -1,5 +1,5 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*: Error: Opcode not supported on this processor: r5900 \(mips3\) `ll \$5,0\(\$6\)'
|
.*: Error: opcode not supported on this processor: r5900 \(mips3\) `ll \$5,0\(\$6\)'
|
||||||
.*: Error: Opcode not supported on this processor: r5900 \(mips3\) `sc \$5,0\(\$6\)'
|
.*: Error: opcode not supported on this processor: r5900 \(mips3\) `sc \$5,0\(\$6\)'
|
||||||
.*: Error: Opcode not supported on this processor: r5900 \(mips3\) `lld \$5,0\(\$6\)'
|
.*: Error: opcode not supported on this processor: r5900 \(mips3\) `lld \$5,0\(\$6\)'
|
||||||
.*: Error: Opcode not supported on this processor: r5900 \(mips3\) `scd \$5,0\(\$6\)'
|
.*: Error: opcode not supported on this processor: r5900 \(mips3\) `scd \$5,0\(\$6\)'
|
||||||
|
|||||||
@ -1,7 +1,7 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:6: Warning: Relaxed out-of-range branch into a jump
|
.*:6: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:11: Warning: Relaxed out-of-range branch into a jump
|
.*:11: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:7: Error: Branch out of range
|
.*:7: Error: branch out of range
|
||||||
.*:8: Error: Branch out of range
|
.*:8: Error: branch out of range
|
||||||
.*:9: Error: Branch out of range
|
.*:9: Error: branch out of range
|
||||||
.*:10: Error: Branch out of range
|
.*:10: Error: branch out of range
|
||||||
|
|||||||
@ -1,5 +1,5 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:6: Warning: Relaxed out-of-range branch into a jump
|
.*:6: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:9: Warning: Relaxed out-of-range branch into a jump
|
.*:9: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:7: Error: Branch out of range
|
.*:7: Error: branch out of range
|
||||||
.*:8: Error: Branch out of range
|
.*:8: Error: branch out of range
|
||||||
|
|||||||
@ -1,24 +1,24 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:9: Warning: Relaxed out-of-range branch into a jump
|
.*:9: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:14: Warning: Relaxed out-of-range branch into a jump
|
.*:14: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:19: Warning: Relaxed out-of-range branch into a jump
|
.*:19: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:24: Warning: Relaxed out-of-range branch into a jump
|
.*:24: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:28: Warning: Relaxed out-of-range branch into a jump
|
.*:28: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:33: Warning: Relaxed out-of-range branch into a jump
|
.*:33: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:37: Warning: Relaxed out-of-range branch into a jump
|
.*:37: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:42: Warning: Relaxed out-of-range branch into a jump
|
.*:42: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:46: Warning: Relaxed out-of-range branch into a jump
|
.*:46: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:51: Warning: Relaxed out-of-range branch into a jump
|
.*:51: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:55: Warning: Relaxed out-of-range branch into a jump
|
.*:55: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:62: Warning: Relaxed out-of-range branch into a jump
|
.*:62: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:68: Warning: Relaxed out-of-range branch into a jump
|
.*:68: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:73: Warning: Relaxed out-of-range branch into a jump
|
.*:73: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:79: Warning: Relaxed out-of-range branch into a jump
|
.*:79: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:85: Warning: Relaxed out-of-range branch into a jump
|
.*:85: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:96: Warning: Relaxed out-of-range branch into a jump
|
.*:96: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:101: Warning: Relaxed out-of-range branch into a jump
|
.*:101: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:106: Warning: Relaxed out-of-range branch into a jump
|
.*:106: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:111: Warning: Relaxed out-of-range branch into a jump
|
.*:111: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:116: Warning: Relaxed out-of-range branch into a jump
|
.*:116: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:121: Warning: Relaxed out-of-range branch into a jump
|
.*:121: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:126: Warning: Relaxed out-of-range branch into a jump
|
.*:126: Warning: relaxed out-of-range branch into a jump
|
||||||
|
|||||||
@ -1,10 +1,10 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:9: Warning: Relaxed out-of-range branch into a jump
|
.*:9: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:13: Warning: Relaxed out-of-range branch into a jump
|
.*:13: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:18: Warning: Relaxed out-of-range branch into a jump
|
.*:18: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:22: Warning: Relaxed out-of-range branch into a jump
|
.*:22: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:27: Warning: Relaxed out-of-range branch into a jump
|
.*:27: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:31: Warning: Relaxed out-of-range branch into a jump
|
.*:31: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:36: Warning: Relaxed out-of-range branch into a jump
|
.*:36: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:40: Warning: Relaxed out-of-range branch into a jump
|
.*:40: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:45: Warning: Relaxed out-of-range branch into a jump
|
.*:45: Warning: relaxed out-of-range branch into a jump
|
||||||
|
|||||||
@ -1,45 +1,45 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:9: Warning: Relaxed out-of-range branch into a jump
|
.*:9: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:10: Warning: Relaxed out-of-range branch into a jump
|
.*:10: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:11: Warning: Relaxed out-of-range branch into a jump
|
.*:11: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:12: Warning: Relaxed out-of-range branch into a jump
|
.*:12: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:13: Warning: Relaxed out-of-range branch into a jump
|
.*:13: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:14: Warning: Relaxed out-of-range branch into a jump
|
.*:14: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:15: Warning: Relaxed out-of-range branch into a jump
|
.*:15: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:16: Warning: Relaxed out-of-range branch into a jump
|
.*:16: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:17: Warning: Relaxed out-of-range branch into a jump
|
.*:17: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:18: Warning: Relaxed out-of-range branch into a jump
|
.*:18: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:20: Warning: Relaxed out-of-range branch into a jump
|
.*:20: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:21: Warning: Relaxed out-of-range branch into a jump
|
.*:21: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:23: Warning: Relaxed out-of-range branch into a jump
|
.*:23: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:24: Warning: Relaxed out-of-range branch into a jump
|
.*:24: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:25: Warning: Relaxed out-of-range branch into a jump
|
.*:25: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:26: Warning: Relaxed out-of-range branch into a jump
|
.*:26: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:27: Warning: Relaxed out-of-range branch into a jump
|
.*:27: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:28: Warning: Relaxed out-of-range branch into a jump
|
.*:28: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:29: Warning: Relaxed out-of-range branch into a jump
|
.*:29: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:30: Warning: Relaxed out-of-range branch into a jump
|
.*:30: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:32: Warning: Relaxed out-of-range branch into a jump
|
.*:32: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:33: Warning: Relaxed out-of-range branch into a jump
|
.*:33: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:37: Warning: Relaxed out-of-range branch into a jump
|
.*:37: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:38: Warning: Relaxed out-of-range branch into a jump
|
.*:38: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:39: Warning: Relaxed out-of-range branch into a jump
|
.*:39: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:40: Warning: Relaxed out-of-range branch into a jump
|
.*:40: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:41: Warning: Relaxed out-of-range branch into a jump
|
.*:41: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:42: Warning: Relaxed out-of-range branch into a jump
|
.*:42: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:43: Warning: Relaxed out-of-range branch into a jump
|
.*:43: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:44: Warning: Relaxed out-of-range branch into a jump
|
.*:44: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:45: Warning: Relaxed out-of-range branch into a jump
|
.*:45: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:46: Warning: Relaxed out-of-range branch into a jump
|
.*:46: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:48: Warning: Relaxed out-of-range branch into a jump
|
.*:48: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:49: Warning: Relaxed out-of-range branch into a jump
|
.*:49: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:51: Warning: Relaxed out-of-range branch into a jump
|
.*:51: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:52: Warning: Relaxed out-of-range branch into a jump
|
.*:52: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:53: Warning: Relaxed out-of-range branch into a jump
|
.*:53: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:54: Warning: Relaxed out-of-range branch into a jump
|
.*:54: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:55: Warning: Relaxed out-of-range branch into a jump
|
.*:55: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:56: Warning: Relaxed out-of-range branch into a jump
|
.*:56: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:57: Warning: Relaxed out-of-range branch into a jump
|
.*:57: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:58: Warning: Relaxed out-of-range branch into a jump
|
.*:58: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:60: Warning: Relaxed out-of-range branch into a jump
|
.*:60: Warning: relaxed out-of-range branch into a jump
|
||||||
.*:61: Warning: Relaxed out-of-range branch into a jump
|
.*:61: Warning: relaxed out-of-range branch into a jump
|
||||||
|
|||||||
@ -1,3 +1,3 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:146: Warning: Condition code register should be even for c.eq.ps, was 3
|
.*:146: Warning: condition code register should be even for c.eq.ps, was 3
|
||||||
.*:147: Warning: Condition code register should be even for movf.ps, was 3
|
.*:147: Warning: condition code register should be even for movf.ps, was 3
|
||||||
|
|||||||
@ -1,11 +1,11 @@
|
|||||||
.*: Assembler messages:
|
.*: Assembler messages:
|
||||||
.*:6: Error: bad expression
|
.*:6: Error: bad expression
|
||||||
.*:6: Error: Illegal operands `addiu \$4,\$28,%dtprel\(tlsvar\)'
|
.*:6: Error: invalid operands `addiu \$4,\$28,%dtprel\(tlsvar\)'
|
||||||
.*:7: Error: bad expression
|
.*:7: Error: bad expression
|
||||||
.*:7: Error: Illegal operands `addiu \$4,\$28,%tprel\(tlsvar\)'
|
.*:7: Error: invalid operands `addiu \$4,\$28,%tprel\(tlsvar\)'
|
||||||
.*:8: Error: bad expression
|
.*:8: Error: bad expression
|
||||||
.*:8: Error: missing '\)'
|
.*:8: Error: missing '\)'
|
||||||
.*:8: Error: Illegal operands `addiu \$4,\$28,%lo\(%gottprel\(tlsvar\)\)'
|
.*:8: Error: invalid operands `addiu \$4,\$28,%lo\(%gottprel\(tlsvar\)\)'
|
||||||
.*:9: Error: bad expression
|
.*:9: Error: bad expression
|
||||||
.*:9: Error: missing '\)'
|
.*:9: Error: missing '\)'
|
||||||
.*:9: Error: Illegal operands `addiu \$4,\$28,%hi\(%gottprel\(tlsvar\)\)'
|
.*:9: Error: invalid operands `addiu \$4,\$28,%hi\(%gottprel\(tlsvar\)\)'
|
||||||
|
|||||||
@ -3,13 +3,13 @@
|
|||||||
.*:7: Error: operand 3 must be scalar `srl.ob \$f2,\$f4,\$f6'
|
.*:7: Error: operand 3 must be scalar `srl.ob \$f2,\$f4,\$f6'
|
||||||
.*:10: Error: operand 2 must be an immediate `rzu.ob \$f2,\$f6\[1\]'
|
.*:10: Error: operand 2 must be an immediate `rzu.ob \$f2,\$f6\[1\]'
|
||||||
.*:11: Error: operand 2 must be an immediate `rzu.ob \$f2,\$f6'
|
.*:11: Error: operand 2 must be an immediate `rzu.ob \$f2,\$f6'
|
||||||
.*:14: Error: Illegal operands `add.ob \$v2,\$f4,\$f6'
|
.*:14: Error: invalid operands `add.ob \$v2,\$f4,\$f6'
|
||||||
.*:15: Error: Illegal operands `add.ob \$f2,\$v4,\$f6'
|
.*:15: Error: invalid operands `add.ob \$f2,\$v4,\$f6'
|
||||||
.*:16: Error: Illegal operands `add.ob \$f2,\$f4,\$v6'
|
.*:16: Error: invalid operands `add.ob \$f2,\$f4,\$v6'
|
||||||
.*:17: Error: Illegal operands `add.ob \$v2,\$v4,\$v6'
|
.*:17: Error: invalid operands `add.ob \$v2,\$v4,\$v6'
|
||||||
.*:20: Error: Illegal operands `add.ob \$v2,\$f4,\$f6\[1\]'
|
.*:20: Error: invalid operands `add.ob \$v2,\$f4,\$f6\[1\]'
|
||||||
.*:21: Error: Illegal operands `add.ob \$f2,\$v4,\$f6\[1\]'
|
.*:21: Error: invalid operands `add.ob \$f2,\$v4,\$f6\[1\]'
|
||||||
.*:22: Error: Illegal operands `add.ob \$f2,\$f4,\$v6\[1\]'
|
.*:22: Error: invalid operands `add.ob \$f2,\$f4,\$v6\[1\]'
|
||||||
.*:23: Error: Illegal operands `add.ob \$v2,\$v4,\$v6\[1\]'
|
.*:23: Error: invalid operands `add.ob \$v2,\$v4,\$v6\[1\]'
|
||||||
.*:25: Error: Vector element must be constant `add.ob \$f2,\$f4,\$f6\[foo\]'
|
.*:25: Error: vector element must be constant `add.ob \$f2,\$f4,\$f6\[foo\]'
|
||||||
.*:26: Error: Missing `\]' `add.ob \$f2,\$f4,\$f6\[1}'
|
.*:26: Error: missing `\]' `add.ob \$f2,\$f4,\$f6\[1}'
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user