Commit Graph

14 Commits

Author SHA1 Message Date
MatCat
11862865f8 Support for negative and overflow, ISA work, display registers for clearing and forcing update (on SIM only for force update), memory editor, and more 2021-04-15 00:37:00 -07:00
MatCat
24161774d9 WIP to branch instuctions, implementing OVERFLOW status register flag, implamented Thread Interupt feature 2021-04-13 01:43:35 -07:00
MatCat
55cfeb3c15 Refacotred isa file formats, added more instructions 2021-04-10 15:33:40 -07:00
MatCat
a76e01aca1 Refactoring of the display and some 24 bit instructions 2021-04-09 01:39:21 -07:00
MatCat
d21c723894 Working on ISA documentation 2021-04-07 23:07:32 -07:00
MatCat
1a61c1d43b Added line controller to RAM 2021-04-07 01:51:21 -07:00
MatCat
44cdd9c219 Added cycle count to interval runs 2021-04-07 01:29:12 -07:00
MatCat
a3f5382437 Memory now follows the location, shows red when writing to RAM and GREEN when reading, yellow when the address bus just happens to be sitting on the address but not actively reading or writing. 2021-04-05 23:49:23 -07:00
MatCat
3943201db1 Added many instructions and some UI improvements 2021-04-05 02:49:12 -07:00
MatCat
50260f060e Added reset button 2021-04-04 03:40:30 -07:00
MatCat
3d050b8b55 Added a bunch of branching instructions, some stack instructions, and added stack example to the demo 2021-04-04 03:26:28 -07:00
MatCat
f67b5c3e64 Added interface and demo code to run 2021-04-04 02:16:38 -07:00
MatCat
bf769d0855 Added microcode compiler 2021-04-03 20:36:17 -07:00
MatCat
f116826575 First Commit 2021-04-03 19:06:56 -07:00