MatCat
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11862865f8
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Support for negative and overflow, ISA work, display registers for clearing and forcing update (on SIM only for force update), memory editor, and more
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2021-04-15 00:37:00 -07:00 |
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MatCat
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24161774d9
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WIP to branch instuctions, implementing OVERFLOW status register flag, implamented Thread Interupt feature
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2021-04-13 01:43:35 -07:00 |
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MatCat
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55cfeb3c15
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Refacotred isa file formats, added more instructions
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2021-04-10 15:33:40 -07:00 |
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MatCat
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a76e01aca1
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Refactoring of the display and some 24 bit instructions
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2021-04-09 01:39:21 -07:00 |
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MatCat
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d21c723894
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Working on ISA documentation
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2021-04-07 23:07:32 -07:00 |
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MatCat
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1a61c1d43b
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Added line controller to RAM
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2021-04-07 01:51:21 -07:00 |
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MatCat
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44cdd9c219
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Added cycle count to interval runs
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2021-04-07 01:29:12 -07:00 |
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MatCat
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a3f5382437
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Memory now follows the location, shows red when writing to RAM and GREEN when reading, yellow when the address bus just happens to be sitting on the address but not actively reading or writing.
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2021-04-05 23:49:23 -07:00 |
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MatCat
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3943201db1
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Added many instructions and some UI improvements
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2021-04-05 02:49:12 -07:00 |
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MatCat
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50260f060e
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Added reset button
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2021-04-04 03:40:30 -07:00 |
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MatCat
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3d050b8b55
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Added a bunch of branching instructions, some stack instructions, and added stack example to the demo
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2021-04-04 03:26:28 -07:00 |
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MatCat
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f67b5c3e64
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Added interface and demo code to run
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2021-04-04 02:16:38 -07:00 |
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MatCat
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bf769d0855
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Added microcode compiler
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2021-04-03 20:36:17 -07:00 |
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MatCat
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f116826575
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First Commit
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2021-04-03 19:06:56 -07:00 |
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