MatCat.OpenSource/8SA1Sim
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Refacotred ISA opcodes

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MatCat 2021-04-10 11:47:52 -07:00
parent dfd3736e70
commit baf56330a3
1 changed files with 1 additions and 1 deletions
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js/main.js
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@ -49,7 +49,7 @@ cpu.RAM[0xEE] = is_JMP_i.Bytecode;
cpu.RAM[0xEF] = v_printloop;
cpu.RAM[0xF0] = is_PLAB.Bytecode;
cpu.RAM[0xF1] = is_PLA.Bytecode; // return
cpu.RAM[0xF2] = is_PRTS.Bytecode;
cpu.RAM[0xF2] = is_RTS_paged.Bytecode;
stringToRAM("Welcome to the MatCat 8SA1 Computer Simulator!\n\nThis is a full hardware simulation of the computer to allow for easy development testing. It is currently a heavy work in progress as it is very early alpha, so check back often for new features!\n\n\nThis demo can be seen in the examples folder on the git page at: \nhttps://mygit.space/MatCat.OpenSource/8SA1Sim",cpu.RAM,0x100);