Added a bunch of new indirect and absolute instructions
This commit is contained in:
MatCat
parent
0e06cfc332
commit
108b967a87
44
examples/printstring.asm
Normal file
44
examples/printstring.asm
Normal file
@ -0,0 +1,44 @@
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; printstring.asm
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;
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; This is a simple demonstration routine for the emulator to take a null terminated string from RAM
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; and display it out to the emulators text printer.
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; The routine takes a simple argument on the stack with the address of the string.
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; The routine will use the DISPLAY variable set in .data
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;
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; Version: 0.2.0
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GLOBAL START
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GLOBAL PRINTSTRING
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SECTION .text
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START: LDAB MYSTRING ; Put string address into AB
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PHAB ; and push to the stack
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JSR PRINTSTRING ; Call PRINTSTRING routine
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SECTION .printstring
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PRINTSTRING: PLAB
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PLCD
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PHAB ; Get the address of the string ^^^
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LDAB $DISPLAY ; Set the output address
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PHAB
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PRINTLOOP: LDAB CD
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CMP %A,%B
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BEQ RETURN ; If we pull a 0, or null then we are done
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STAL [SP]
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ADD %C,$1 ; Increment our string location by 1
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BCS ROLLOVER ; If it rolls over we need to go handle high byte
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PLAB
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ADD %A,$1 ; Icrement our output by 1
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PHAB
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JMP PRINTLOOP ; Loop back and keep reading in the string
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ROLLOVER: ADD %D, $1
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PLAB
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ADD %B, $1
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PHAB
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JMP PRINTLOOP ; Loop back and keep reading in the string
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RETURN: PLAB ; To return we need to clean up our stack use first
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RTS
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SECTION .data
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DISPLAY equ 8000h
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MYSTRING DB "Lorem ipsum dolor sit amet, consectetur adipiscing elit. Nunc maximus erat mollis, fermentum quam at, blandit turpis. Pellentesque arcu tortor, smoke weed guam sagittis ac, posuere ut ipsum. Nulla facilisi. Mauris eget urna id sem porttitor consequat ultrices porttitor magna. Quisque condimentum porta viverra. Suspendisse ac condimentum ante. Duis accumsan augue urna, at ultricies nunc accumsan eget. Nullam eleifend.", 0
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134
js/cpu.js
134
js/cpu.js
@ -33,6 +33,7 @@ const CONTROL_OEM2 = 0b00000000100000000000000000000000; // Outpu
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const CONTROL_OEM3 = 0b00000001000000000000000000000000; // Output Enable MUX 3
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const CONTROL_OEM3 = 0b00000001000000000000000000000000; // Output Enable MUX 3
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const CONTROL_OEM4 = 0b00000010000000000000000000000000; // Output Enable MUX 4
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const CONTROL_OEM4 = 0b00000010000000000000000000000000; // Output Enable MUX 4
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const CONTROL_OEME = 0b00000100000000000000000000000000; // Output Enable MUX Enable
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const CONTROL_OEME = 0b00000100000000000000000000000000; // Output Enable MUX Enable
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const CONTROL_AE = 0b00001000000000000000000000000000; // ALU Enable
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const CONTROL_RI = 0b00010000000000000000000000000000; // RAM Input Enable
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const CONTROL_RI = 0b00010000000000000000000000000000; // RAM Input Enable
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const CONTROL_IRI = 0b00100000000000000000000000000000; // Instruction Register Input Enable
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const CONTROL_IRI = 0b00100000000000000000000000000000; // Instruction Register Input Enable
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const CONTROL_MCL0 = 0b01000000000000000000000000000000; // Microcode Counter to 0
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const CONTROL_MCL0 = 0b01000000000000000000000000000000; // Microcode Counter to 0
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@ -61,7 +62,6 @@ const OECONTROL_CD = 0b10010 // GPD to HIGH, GPC to LOW
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const OECONTROL_DA = 0b10011 // GPA to HIGH, GPD to LOW
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const OECONTROL_DA = 0b10011 // GPA to HIGH, GPD to LOW
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const OECONTROL_DB = 0b10100 // GPB to HIGH, GPD to LOW
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const OECONTROL_DB = 0b10100 // GPB to HIGH, GPD to LOW
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const OECONTROL_DC = 0b10101 // GPC to HIGH, GPD to LOW
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const OECONTROL_DC = 0b10101 // GPC to HIGH, GPD to LOW
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const OECONTROL_AE = 0b11100 // ALU Enable
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const OECONTROL_AO = 0b11101 // ALU Output to LOW
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const OECONTROL_AO = 0b11101 // ALU Output to LOW
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const OECONTROL_SR = 0b11110 // Status Register to LOW
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const OECONTROL_SR = 0b11110 // Status Register to LOW
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const OECONTROL_RO = 0b11111 // RAM to DATABUS Enable
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const OECONTROL_RO = 0b11111 // RAM to DATABUS Enable
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@ -351,6 +351,7 @@ class CPU_8SA1 {
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if (this.MC_Controls & CONTROL_RCIH) this.GPC_In_HIGH_CLK();
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if (this.MC_Controls & CONTROL_RCIH) this.GPC_In_HIGH_CLK();
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if (this.MC_Controls & CONTROL_RDIL) this.GPD_In_LOW_CLK();
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if (this.MC_Controls & CONTROL_RDIL) this.GPD_In_LOW_CLK();
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if (this.MC_Controls & CONTROL_RDIH) this.GPD_In_HIGH_CLK();
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if (this.MC_Controls & CONTROL_RDIH) this.GPD_In_HIGH_CLK();
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if (this.MC_Controls & CONTROL_AE ) this.ALU_CLK();
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}
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}
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@ -359,6 +360,71 @@ class CPU_8SA1 {
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this._FetchDecode_CLK_neg();
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this._FetchDecode_CLK_neg();
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}
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}
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ALU_CLK() {
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//console.log("ALU Enable");
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let ALU_A = this.DATABUS & BITMASK_8;
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let ALU_B = (this.DATABUS & (BITMASK_8 << 8)) >> 8;
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let ALU_Result = 0;
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let ALUMUX = (this.MC_Controls & CONTROL_ALUM1) ? 0b10 : 0;
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ALUMUX |= (this.MC_Controls & CONTROL_ALUM0) ? 0b01 : 0;
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//console.log(`ALU: A=${ALU_A}, B=${ALU_B}, MUX: ${ALUMUX}`);
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if (this.MC_Controls & CONTROL_ALUI) console.log("ALU Inverting B");
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let SHIFTING = false;
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if (this.MC_Controls & CONTROL_ALUSL) SHIFTING = true;
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if (this.MC_Controls & CONTROL_ALUSR) SHIFTING = true;
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switch (ALUMUX) {
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case 0: { // ADD
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if (this.MC_Controls & CONTROL_ALUI) ALU_B = ~ALU_B;
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ALU_Result = ALU_A + ALU_B;
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if (this.MC_Controls & CONTROL_ALUC && !SHIFTING) ALU_Result += 1;
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break;
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}
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case 1: { // AND
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ALU_Result = ALU_A & ALU_B;
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if (this.MC_Controls & CONTROL_ALUI) ALU_Result = ~ALU_Result;
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if (this.MC_Controls & CONTROL_ALUC && !SHIFTING) ALU_Result += 1;
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break;
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}
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case 2: { // OR
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ALU_Result = ALU_A | ALU_B;
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if (this.MC_Controls & CONTROL_ALUI) ALU_Result = ~ALU_Result;
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if (this.MC_Controls & CONTROL_ALUC && !SHIFTING) ALU_Result += 1;
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break;
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}
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case 3: { // XOR
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ALU_Result = ALU_A ^ ALU_B;
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if (this.MC_Controls & CONTROL_ALUI) ALU_Result = ~ALU_Result;
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if (this.MC_Controls & CONTROL_ALUC && !SHIFTING) ALU_Result += 1;
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break;
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}
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}
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if (this.MC_Controls & CONTROL_ALUSL) ALU_Result = ALU_Result << 1;
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if ((this.MC_Controls & CONTROL_ALUSL) && (this.MC_Controls & CONTROL_ALUC)) ALU_Result = ALU_Result | 0b00000001;
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if (this.MC_Controls & CONTROL_ALUSR) ALU_Result = ALU_Result >> 1;
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if ((this.MC_Controls & CONTROL_ALUSR) && (this.MC_Controls & CONTROL_ALUC)) ALU_Result = ALU_Result | 0b10000000;
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if (ALU_Result & 0b100000000) {
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// We have a carry
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this.SR = this.SR | 0b00000001;
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} else {
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this.SR = this.SR & 0b11111110;
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}
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if (ALU_Result === 0) {
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// We have a ZERO
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this.SR = this.SR | 0b00000010;
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} else {
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this.SR = this.SR & 0b11111101;
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}
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this.ALUSUM = ALU_Result & BITMASK_8;
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}
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_FetchDecode_CLK_neg() {
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_FetchDecode_CLK_neg() {
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// We actually setup all of our fetch and decode logic during the clocks low phase
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// We actually setup all of our fetch and decode logic during the clocks low phase
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this.DATABUS = 0;
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this.DATABUS = 0;
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@ -482,72 +548,6 @@ class CPU_8SA1 {
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this.DATABUS = ((this.GPC & BITMASK_8) << 8) | (this.GPD & BITMASK_8);
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this.DATABUS = ((this.GPC & BITMASK_8) << 8) | (this.GPD & BITMASK_8);
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break;
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break;
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}
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}
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case OECONTROL_AE: {
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//console.log("ALU Enable");
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this.DATABUS = (this.GPB << 8) | this.GPA;
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let ALU_A = this.DATABUS & BITMASK_8;
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let ALU_B = (this.DATABUS & (BITMASK_8 << 8)) >> 8;
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let ALU_Result = 0;
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let ALUMUX = (MC_Controls & CONTROL_ALUM1) ? 0b10 : 0;
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ALUMUX |= (MC_Controls & CONTROL_ALUM0) ? 0b01 : 0;
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//console.log(`ALU: A=${ALU_A}, B=${ALU_B}, MUX: ${ALUMUX}`);
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if (MC_Controls & CONTROL_ALUI) console.log("ALU Inverting B");
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let SHIFTING = false;
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if (MC_Controls & CONTROL_ALUSL) SHIFTING = true;
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if (MC_Controls & CONTROL_ALUSR) SHIFTING = true;
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switch (ALUMUX) {
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case 0: { // ADD
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if (MC_Controls & CONTROL_ALUI) ALU_B = ~ALU_B;
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ALU_Result = ALU_A + ALU_B;
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if (MC_Controls & CONTROL_ALUC && !SHIFTING) ALU_Result += 1;
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break;
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}
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case 1: { // AND
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ALU_Result = ALU_A & ALU_B;
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if (MC_Controls & CONTROL_ALUI) ALU_Result = ~ALU_Result;
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if (MC_Controls & CONTROL_ALUC && !SHIFTING) ALU_Result += 1;
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break;
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}
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case 2: { // OR
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ALU_Result = ALU_A | ALU_B;
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if (MC_Controls & CONTROL_ALUI) ALU_Result = ~ALU_Result;
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if (MC_Controls & CONTROL_ALUC && !SHIFTING) ALU_Result += 1;
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break;
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}
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case 3: { // XOR
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ALU_Result = ALU_A ^ ALU_B;
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if (MC_Controls & CONTROL_ALUI) ALU_Result = ~ALU_Result;
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if (MC_Controls & CONTROL_ALUC && !SHIFTING) ALU_Result += 1;
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break;
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}
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}
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if (MC_Controls & CONTROL_ALUSL) ALU_Result = ALU_Result << 1;
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if ((MC_Controls & CONTROL_ALUSL) && (MC_Controls & CONTROL_ALUC)) ALU_Result = ALU_Result | 0b00000001;
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if (MC_Controls & CONTROL_ALUSR) ALU_Result = ALU_Result >> 1;
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if ((MC_Controls & CONTROL_ALUSR) && (MC_Controls & CONTROL_ALUC)) ALU_Result = ALU_Result | 0b10000000;
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if (ALU_Result & 0b100000000) {
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// We have a carry
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this.SR = this.SR | 0b00000001;
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} else {
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this.SR = this.SR & 0b11111110;
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}
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if (ALU_Result === 0) {
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// We have a ZERO
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this.SR = this.SR | 0b00000010;
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} else {
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this.SR = this.SR & 0b11111101;
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}
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this.ALUSUM = ALU_Result & BITMASK_8;
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break;
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}
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case OECONTROL_AO: {
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case OECONTROL_AO: {
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this.DATABUS = (this.DATABUS & (BITMASK_8 << 8)) | this.ALUSUM;
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this.DATABUS = (this.DATABUS & (BITMASK_8 << 8)) | this.ALUSUM;
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//console.log("DATABUS = SUM");
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//console.log("DATABUS = SUM");
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45
js/main.js
45
js/main.js
@ -35,12 +35,8 @@ cpu.RAM[3] = 0;
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cpu.RAM[4] = is_CMP.Bytecode;
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cpu.RAM[4] = is_CMP.Bytecode;
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*/
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*/
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cpu.RAM[0] = is_LDAB_i.Bytecode;
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cpu.RAM[1] = 0x0100;
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cpu.RAM[2] = is_PHAB.Bytecode;
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cpu.RAM[3] = is_JSR.Bytecode;
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cpu.RAM[4] = 0x00D0;
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/*
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cpu.RAM[0xD0] = is_PLAB.Bytecode;
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cpu.RAM[0xD0] = is_PLAB.Bytecode;
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cpu.RAM[0xD1] = is_PLCD.Bytecode;
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cpu.RAM[0xD1] = is_PLCD.Bytecode;
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cpu.RAM[0xD2] = is_PHAB.Bytecode;
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cpu.RAM[0xD2] = is_PHAB.Bytecode;
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@ -86,7 +82,46 @@ cpu.RAM[0xF9] = is_JMP_i.Bytecode;
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cpu.RAM[0xFA] = 0x00D5;
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cpu.RAM[0xFA] = 0x00D5;
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cpu.RAM[0xFB] = is_PLAB.Bytecode;
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cpu.RAM[0xFB] = is_PLAB.Bytecode;
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cpu.RAM[0xFC] = is_RTS.Bytecode;
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cpu.RAM[0xFC] = is_RTS.Bytecode;
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*/
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cpu.RAM[0] = is_LDAB_i.Bytecode;
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cpu.RAM[1] = 0x0100;
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cpu.RAM[2] = is_PHAB.Bytecode;
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cpu.RAM[3] = is_JSR.Bytecode;
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cpu.RAM[4] = 0x00D0;
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cpu.RAM[0xD0] = is_PLAB.Bytecode;
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cpu.RAM[0xD1] = is_PLCD.Bytecode;
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cpu.RAM[0xD2] = is_PHAB.Bytecode;
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cpu.RAM[0xD3] = is_LDAB_i.Bytecode;
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cpu.RAM[0xD4] = 0x8000;
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cpu.RAM[0xD5] = is_PHAB.Bytecode;
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cpu.RAM[0xD6] = is_LDAB_GPCD.Bytecode; // printloop
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cpu.RAM[0xD7] = is_CMP_gpab.Bytecode;
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cpu.RAM[0xD8] = is_BEQ_i.Bytecode;
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cpu.RAM[0xD9] = 0x00ED;
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cpu.RAM[0xDA] = is_STAL_spin.Bytecode;
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cpu.RAM[0xDB] = is_ADD_gpci.Bytecode
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cpu.RAM[0xDC] = 1;
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cpu.RAM[0xDD] = is_BCS_i.Bytecode;
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cpu.RAM[0xDE] = 0x00E5;
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cpu.RAM[0xDF] = is_PLAB.Bytecode;
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cpu.RAM[0xE0] = is_ADD_gpai.Bytecode;
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cpu.RAM[0xE1] = 1;
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cpu.RAM[0xE2] = is_PHAB.Bytecode;
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cpu.RAM[0xE3] = is_JMP_i.Bytecode;
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cpu.RAM[0xE4] = 0x00D6;
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cpu.RAM[0xE5] = is_ADD_gpdi.Bytecode; // rollover
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cpu.RAM[0xE6] = 1;
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cpu.RAM[0xE7] = is_PLAB.Bytecode;
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cpu.RAM[0xE8] = is_ADD_gpbi.Bytecode;
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cpu.RAM[0xE9] = 1;
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cpu.RAM[0xEA] = is_PHAB.Bytecode;
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cpu.RAM[0xEB] = is_JMP_i.Bytecode;
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cpu.RAM[0xEC] = 0x00D6;
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cpu.RAM[0xED] = is_PLAB.Bytecode; // return
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cpu.RAM[0xEE] = is_RTS.Bytecode;
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stringToRAM("Lorem ipsum dolor sit amet, consectetur adipiscing elit. Nunc maximus erat mollis, fermentum quam at, blandit turpis. Pellentesque arcu tortor, smoke weed guam sagittis ac, posuere ut ipsum. Nulla facilisi. Mauris eget urna id sem porttitor consequat ultrices porttitor magna. Quisque condimentum porta viverra. Suspendisse ac condimentum ante. Duis accumsan augue urna, at ultricies nunc accumsan eget. Nullam eleifend.",cpu.RAM,0x100);
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stringToRAM("Lorem ipsum dolor sit amet, consectetur adipiscing elit. Nunc maximus erat mollis, fermentum quam at, blandit turpis. Pellentesque arcu tortor, smoke weed guam sagittis ac, posuere ut ipsum. Nulla facilisi. Mauris eget urna id sem porttitor consequat ultrices porttitor magna. Quisque condimentum porta viverra. Suspendisse ac condimentum ante. Duis accumsan augue urna, at ultricies nunc accumsan eget. Nullam eleifend.",cpu.RAM,0x100);
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